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sky2: TSO support for EC_U
[linux-2.6/s3c2410-cpufreq.git] / drivers / serial / sunzilog.c
blob244f796dc62595a80f1bc34cea3cfe60b5a8239a
1 /* sunzilog.c: Zilog serial driver for Sparc systems.
2 *
3 * Driver for Zilog serial chips found on Sun workstations and
4 * servers. This driver could actually be made more generic.
5 *
6 * This is based on the old drivers/sbus/char/zs.c code. A lot
7 * of code has been simply moved over directly from there but
8 * much has been rewritten. Credits therefore go out to Eddie
9 * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
10 * work there.
11 *
12 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net)
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/sched.h>
18 #include <linux/errno.h>
19 #include <linux/delay.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22 #include <linux/major.h>
23 #include <linux/string.h>
24 #include <linux/ptrace.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
27 #include <linux/circ_buf.h>
28 #include <linux/serial.h>
29 #include <linux/sysrq.h>
30 #include <linux/console.h>
31 #include <linux/spinlock.h>
32 #ifdef CONFIG_SERIO
33 #include <linux/serio.h>
34 #endif
35 #include <linux/init.h>
36
37 #include <asm/io.h>
38 #include <asm/irq.h>
39 #include <asm/prom.h>
40 #include <asm/of_device.h>
41
42 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
43 #define SUPPORT_SYSRQ
44 #endif
45
46 #include <linux/serial_core.h>
47
48 #include "suncore.h"
49 #include "sunzilog.h"
50
51 /* On 32-bit sparcs we need to delay after register accesses
52 * to accommodate sun4 systems, but we do not need to flush writes.
53 * On 64-bit sparc we only need to flush single writes to ensure
54 * completion.
55 */
56 #ifndef CONFIG_SPARC64
57 #define ZSDELAY() udelay(5)
58 #define ZSDELAY_LONG() udelay(20)
59 #define ZS_WSYNC(channel) do { } while (0)
60 #else
61 #define ZSDELAY()
62 #define ZSDELAY_LONG()
63 #define ZS_WSYNC(__channel) \
64 readb(&((__channel)->control))
65 #endif
66
67 static int num_sunzilog;
68 #define NUM_SUNZILOG num_sunzilog
69 #define NUM_CHANNELS (NUM_SUNZILOG * 2)
70
71 #define ZS_CLOCK 4915200 /* Zilog input clock rate. */
72 #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
73
74 /*
75 * We wrap our port structure around the generic uart_port.
76 */
77 struct uart_sunzilog_port {
78 struct uart_port port;
79
80 /* IRQ servicing chain. */
81 struct uart_sunzilog_port *next;
82
83 /* Current values of Zilog write registers. */
84 unsigned char curregs[NUM_ZSREGS];
85
86 unsigned int flags;
87 #define SUNZILOG_FLAG_CONS_KEYB 0x00000001
88 #define SUNZILOG_FLAG_CONS_MOUSE 0x00000002
89 #define SUNZILOG_FLAG_IS_CONS 0x00000004
90 #define SUNZILOG_FLAG_IS_KGDB 0x00000008
91 #define SUNZILOG_FLAG_MODEM_STATUS 0x00000010
92 #define SUNZILOG_FLAG_IS_CHANNEL_A 0x00000020
93 #define SUNZILOG_FLAG_REGS_HELD 0x00000040
94 #define SUNZILOG_FLAG_TX_STOPPED 0x00000080
95 #define SUNZILOG_FLAG_TX_ACTIVE 0x00000100
96
97 unsigned int cflag;
98
99 unsigned char parity_mask;
100 unsigned char prev_status;
101
102 #ifdef CONFIG_SERIO
103 struct serio serio;
104 int serio_open;
105 #endif
106 };
107
108 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))
109 #define UART_ZILOG(PORT) ((struct uart_sunzilog_port *)(PORT))
110
111 #define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
112 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
113 #define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
114 #define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
115 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
116 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
117 #define ZS_REGS_HELD(UP) ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
118 #define ZS_TX_STOPPED(UP) ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
119 #define ZS_TX_ACTIVE(UP) ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
120
121 /* Reading and writing Zilog8530 registers. The delays are to make this
122 * driver work on the Sun4 which needs a settling delay after each chip
123 * register access, other machines handle this in hardware via auxiliary
124 * flip-flops which implement the settle time we do in software.
125 *
126 * The port lock must be held and local IRQs must be disabled
127 * when {read,write}_zsreg is invoked.
128 */
129 static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
130 unsigned char reg)
131 {
132 unsigned char retval;
133
134 writeb(reg, &channel->control);
135 ZSDELAY();
136 retval = readb(&channel->control);
137 ZSDELAY();
138
139 return retval;
140 }
141
142 static void write_zsreg(struct zilog_channel __iomem *channel,
143 unsigned char reg, unsigned char value)
144 {
145 writeb(reg, &channel->control);
146 ZSDELAY();
147 writeb(value, &channel->control);
148 ZSDELAY();
149 }
150
151 static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
152 {
153 int i;
154
155 for (i = 0; i < 32; i++) {
156 unsigned char regval;
157
158 regval = readb(&channel->control);
159 ZSDELAY();
160 if (regval & Rx_CH_AV)
161 break;
162
163 regval = read_zsreg(channel, R1);
164 readb(&channel->data);
165 ZSDELAY();
166
167 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
168 writeb(ERR_RES, &channel->control);
169 ZSDELAY();
170 ZS_WSYNC(channel);
171 }
172 }
173 }
174
175 /* This function must only be called when the TX is not busy. The UART
176 * port lock must be held and local interrupts disabled.
177 */
178 static void __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
179 {
180 int i;
181
182 /* Let pending transmits finish. */
183 for (i = 0; i < 1000; i++) {
184 unsigned char stat = read_zsreg(channel, R1);
185 if (stat & ALL_SNT)
186 break;
187 udelay(100);
188 }
189
190 writeb(ERR_RES, &channel->control);
191 ZSDELAY();
192 ZS_WSYNC(channel);
193
194 sunzilog_clear_fifo(channel);
195
196 /* Disable all interrupts. */
197 write_zsreg(channel, R1,
198 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
199
200 /* Set parity, sync config, stop bits, and clock divisor. */
201 write_zsreg(channel, R4, regs[R4]);
202
203 /* Set misc. TX/RX control bits. */
204 write_zsreg(channel, R10, regs[R10]);
205
206 /* Set TX/RX controls sans the enable bits. */
207 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
208 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
209
210 /* Synchronous mode config. */
211 write_zsreg(channel, R6, regs[R6]);
212 write_zsreg(channel, R7, regs[R7]);
213
214 /* Don't mess with the interrupt vector (R2, unused by us) and
215 * master interrupt control (R9). We make sure this is setup
216 * properly at probe time then never touch it again.
217 */
218
219 /* Disable baud generator. */
220 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
221
222 /* Clock mode control. */
223 write_zsreg(channel, R11, regs[R11]);
224
225 /* Lower and upper byte of baud rate generator divisor. */
226 write_zsreg(channel, R12, regs[R12]);
227 write_zsreg(channel, R13, regs[R13]);
228
229 /* Now rewrite R14, with BRENAB (if set). */
230 write_zsreg(channel, R14, regs[R14]);
231
232 /* External status interrupt control. */
233 write_zsreg(channel, R15, regs[R15]);
234
235 /* Reset external status interrupts. */
236 write_zsreg(channel, R0, RES_EXT_INT);
237 write_zsreg(channel, R0, RES_EXT_INT);
238
239 /* Rewrite R3/R5, this time without enables masked. */
240 write_zsreg(channel, R3, regs[R3]);
241 write_zsreg(channel, R5, regs[R5]);
242
243 /* Rewrite R1, this time without IRQ enabled masked. */
244 write_zsreg(channel, R1, regs[R1]);
245 }
246
247 /* Reprogram the Zilog channel HW registers with the copies found in the
248 * software state struct. If the transmitter is busy, we defer this update
249 * until the next TX complete interrupt. Else, we do it right now.
250 *
251 * The UART port lock must be held and local interrupts disabled.
252 */
253 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
254 struct zilog_channel __iomem *channel)
255 {
256 if (!ZS_REGS_HELD(up)) {
257 if (ZS_TX_ACTIVE(up)) {
258 up->flags |= SUNZILOG_FLAG_REGS_HELD;
259 } else {
260 __load_zsregs(channel, up->curregs);
261 }
262 }
263 }
264
265 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
266 {
267 unsigned int cur_cflag = up->cflag;
268 int brg, new_baud;
269
270 up->cflag &= ~CBAUD;
271 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
272
273 brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
274 up->curregs[R12] = (brg & 0xff);
275 up->curregs[R13] = (brg >> 8) & 0xff;
276 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
277 }
278
279 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
280 unsigned char ch, int is_break)
281 {
282 if (ZS_IS_KEYB(up)) {
283 /* Stop-A is handled by drivers/char/keyboard.c now. */
284 #ifdef CONFIG_SERIO
285 if (up->serio_open)
286 serio_interrupt(&up->serio, ch, 0);
287 #endif
288 } else if (ZS_IS_MOUSE(up)) {
289 int ret = suncore_mouse_baud_detection(ch, is_break);
290
291 switch (ret) {
292 case 2:
293 sunzilog_change_mouse_baud(up);
294 /* fallthru */
295 case 1:
296 break;
297
298 case 0:
299 #ifdef CONFIG_SERIO
300 if (up->serio_open)
301 serio_interrupt(&up->serio, ch, 0);
302 #endif
303 break;
304 };
305 }
306 }
307
308 static struct tty_struct *
309 sunzilog_receive_chars(struct uart_sunzilog_port *up,
310 struct zilog_channel __iomem *channel)
311 {
312 struct tty_struct *tty;
313 unsigned char ch, r1, flag;
314
315 tty = NULL;
316 if (up->port.info != NULL && /* Unopened serial console */
317 up->port.info->tty != NULL) /* Keyboard || mouse */
318 tty = up->port.info->tty;
319
320 for (;;) {
321
322 r1 = read_zsreg(channel, R1);
323 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
324 writeb(ERR_RES, &channel->control);
325 ZSDELAY();
326 ZS_WSYNC(channel);
327 }
328
329 ch = readb(&channel->control);
330 ZSDELAY();
331
332 /* This funny hack depends upon BRK_ABRT not interfering
333 * with the other bits we care about in R1.
334 */
335 if (ch & BRK_ABRT)
336 r1 |= BRK_ABRT;
337
338 if (!(ch & Rx_CH_AV))
339 break;
340
341 ch = readb(&channel->data);
342 ZSDELAY();
343
344 ch &= up->parity_mask;
345
346 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
347 sunzilog_kbdms_receive_chars(up, ch, 0);
348 continue;
349 }
350
351 if (tty == NULL) {
352 uart_handle_sysrq_char(&up->port, ch);
353 continue;
354 }
355
356 /* A real serial line, record the character and status. */
357 flag = TTY_NORMAL;
358 up->port.icount.rx++;
359 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
360 if (r1 & BRK_ABRT) {
361 r1 &= ~(PAR_ERR | CRC_ERR);
362 up->port.icount.brk++;
363 if (uart_handle_break(&up->port))
364 continue;
365 }
366 else if (r1 & PAR_ERR)
367 up->port.icount.parity++;
368 else if (r1 & CRC_ERR)
369 up->port.icount.frame++;
370 if (r1 & Rx_OVR)
371 up->port.icount.overrun++;
372 r1 &= up->port.read_status_mask;
373 if (r1 & BRK_ABRT)
374 flag = TTY_BREAK;
375 else if (r1 & PAR_ERR)
376 flag = TTY_PARITY;
377 else if (r1 & CRC_ERR)
378 flag = TTY_FRAME;
379 }
380 if (uart_handle_sysrq_char(&up->port, ch))
381 continue;
382
383 if (up->port.ignore_status_mask == 0xff ||
384 (r1 & up->port.ignore_status_mask) == 0) {
385 tty_insert_flip_char(tty, ch, flag);
386 }
387 if (r1 & Rx_OVR)
388 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
389 }
390
391 return tty;
392 }
393
394 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
395 struct zilog_channel __iomem *channel)
396 {
397 unsigned char status;
398
399 status = readb(&channel->control);
400 ZSDELAY();
401
402 writeb(RES_EXT_INT, &channel->control);
403 ZSDELAY();
404 ZS_WSYNC(channel);
405
406 if (status & BRK_ABRT) {
407 if (ZS_IS_MOUSE(up))
408 sunzilog_kbdms_receive_chars(up, 0, 1);
409 if (ZS_IS_CONS(up)) {
410 /* Wait for BREAK to deassert to avoid potentially
411 * confusing the PROM.
412 */
413 while (1) {
414 status = readb(&channel->control);
415 ZSDELAY();
416 if (!(status & BRK_ABRT))
417 break;
418 }
419 sun_do_break();
420 return;
421 }
422 }
423
424 if (ZS_WANTS_MODEM_STATUS(up)) {
425 if (status & SYNC)
426 up->port.icount.dsr++;
427
428 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
429 * But it does not tell us which bit has changed, we have to keep
430 * track of this ourselves.
431 */
432 if ((status ^ up->prev_status) ^ DCD)
433 uart_handle_dcd_change(&up->port,
434 (status & DCD));
435 if ((status ^ up->prev_status) ^ CTS)
436 uart_handle_cts_change(&up->port,
437 (status & CTS));
438
439 wake_up_interruptible(&up->port.info->delta_msr_wait);
440 }
441
442 up->prev_status = status;
443 }
444
445 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
446 struct zilog_channel __iomem *channel)
447 {
448 struct circ_buf *xmit;
449
450 if (ZS_IS_CONS(up)) {
451 unsigned char status = readb(&channel->control);
452 ZSDELAY();
453
454 /* TX still busy? Just wait for the next TX done interrupt.
455 *
456 * It can occur because of how we do serial console writes. It would
457 * be nice to transmit console writes just like we normally would for
458 * a TTY line. (ie. buffered and TX interrupt driven). That is not
459 * easy because console writes cannot sleep. One solution might be
460 * to poll on enough port->xmit space becomming free. -DaveM
461 */
462 if (!(status & Tx_BUF_EMP))
463 return;
464 }
465
466 up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
467
468 if (ZS_REGS_HELD(up)) {
469 __load_zsregs(channel, up->curregs);
470 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
471 }
472
473 if (ZS_TX_STOPPED(up)) {
474 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
475 goto ack_tx_int;
476 }
477
478 if (up->port.x_char) {
479 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
480 writeb(up->port.x_char, &channel->data);
481 ZSDELAY();
482 ZS_WSYNC(channel);
483
484 up->port.icount.tx++;
485 up->port.x_char = 0;
486 return;
487 }
488
489 if (up->port.info == NULL)
490 goto ack_tx_int;
491 xmit = &up->port.info->xmit;
492 if (uart_circ_empty(xmit))
493 goto ack_tx_int;
494
495 if (uart_tx_stopped(&up->port))
496 goto ack_tx_int;
497
498 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
499 writeb(xmit->buf[xmit->tail], &channel->data);
500 ZSDELAY();
501 ZS_WSYNC(channel);
502
503 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
504 up->port.icount.tx++;
505
506 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
507 uart_write_wakeup(&up->port);
508
509 return;
510
511 ack_tx_int:
512 writeb(RES_Tx_P, &channel->control);
513 ZSDELAY();
514 ZS_WSYNC(channel);
515 }
516
517 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
518 {
519 struct uart_sunzilog_port *up = dev_id;
520
521 while (up) {
522 struct zilog_channel __iomem *channel
523 = ZILOG_CHANNEL_FROM_PORT(&up->port);
524 struct tty_struct *tty;
525 unsigned char r3;
526
527 spin_lock(&up->port.lock);
528 r3 = read_zsreg(channel, R3);
529
530 /* Channel A */
531 tty = NULL;
532 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
533 writeb(RES_H_IUS, &channel->control);
534 ZSDELAY();
535 ZS_WSYNC(channel);
536
537 if (r3 & CHARxIP)
538 tty = sunzilog_receive_chars(up, channel);
539 if (r3 & CHAEXT)
540 sunzilog_status_handle(up, channel);
541 if (r3 & CHATxIP)
542 sunzilog_transmit_chars(up, channel);
543 }
544 spin_unlock(&up->port.lock);
545
546 if (tty)
547 tty_flip_buffer_push(tty);
548
549 /* Channel B */
550 up = up->next;
551 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
552
553 spin_lock(&up->port.lock);
554 tty = NULL;
555 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
556 writeb(RES_H_IUS, &channel->control);
557 ZSDELAY();
558 ZS_WSYNC(channel);
559
560 if (r3 & CHBRxIP)
561 tty = sunzilog_receive_chars(up, channel);
562 if (r3 & CHBEXT)
563 sunzilog_status_handle(up, channel);
564 if (r3 & CHBTxIP)
565 sunzilog_transmit_chars(up, channel);
566 }
567 spin_unlock(&up->port.lock);
568
569 if (tty)
570 tty_flip_buffer_push(tty);
571
572 up = up->next;
573 }
574
575 return IRQ_HANDLED;
576 }
577
578 /* A convenient way to quickly get R0 status. The caller must _not_ hold the
579 * port lock, it is acquired here.
580 */
581 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
582 {
583 struct zilog_channel __iomem *channel;
584 unsigned char status;
585
586 channel = ZILOG_CHANNEL_FROM_PORT(port);
587 status = readb(&channel->control);
588 ZSDELAY();
589
590 return status;
591 }
592
593 /* The port lock is not held. */
594 static unsigned int sunzilog_tx_empty(struct uart_port *port)
595 {
596 unsigned long flags;
597 unsigned char status;
598 unsigned int ret;
599
600 spin_lock_irqsave(&port->lock, flags);
601
602 status = sunzilog_read_channel_status(port);
603
604 spin_unlock_irqrestore(&port->lock, flags);
605
606 if (status & Tx_BUF_EMP)
607 ret = TIOCSER_TEMT;
608 else
609 ret = 0;
610
611 return ret;
612 }
613
614 /* The port lock is held and interrupts are disabled. */
615 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
616 {
617 unsigned char status;
618 unsigned int ret;
619
620 status = sunzilog_read_channel_status(port);
621
622 ret = 0;
623 if (status & DCD)
624 ret |= TIOCM_CAR;
625 if (status & SYNC)
626 ret |= TIOCM_DSR;
627 if (status & CTS)
628 ret |= TIOCM_CTS;
629
630 return ret;
631 }
632
633 /* The port lock is held and interrupts are disabled. */
634 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
635 {
636 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
637 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
638 unsigned char set_bits, clear_bits;
639
640 set_bits = clear_bits = 0;
641
642 if (mctrl & TIOCM_RTS)
643 set_bits |= RTS;
644 else
645 clear_bits |= RTS;
646 if (mctrl & TIOCM_DTR)
647 set_bits |= DTR;
648 else
649 clear_bits |= DTR;
650
651 /* NOTE: Not subject to 'transmitter active' rule. */
652 up->curregs[R5] |= set_bits;
653 up->curregs[R5] &= ~clear_bits;
654 write_zsreg(channel, R5, up->curregs[R5]);
655 }
656
657 /* The port lock is held and interrupts are disabled. */
658 static void sunzilog_stop_tx(struct uart_port *port)
659 {
660 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
661
662 up->flags |= SUNZILOG_FLAG_TX_STOPPED;
663 }
664
665 /* The port lock is held and interrupts are disabled. */
666 static void sunzilog_start_tx(struct uart_port *port)
667 {
668 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
669 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
670 unsigned char status;
671
672 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
673 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
674
675 status = readb(&channel->control);
676 ZSDELAY();
677
678 /* TX busy? Just wait for the TX done interrupt. */
679 if (!(status & Tx_BUF_EMP))
680 return;
681
682 /* Send the first character to jump-start the TX done
683 * IRQ sending engine.
684 */
685 if (port->x_char) {
686 writeb(port->x_char, &channel->data);
687 ZSDELAY();
688 ZS_WSYNC(channel);
689
690 port->icount.tx++;
691 port->x_char = 0;
692 } else {
693 struct circ_buf *xmit = &port->info->xmit;
694
695 writeb(xmit->buf[xmit->tail], &channel->data);
696 ZSDELAY();
697 ZS_WSYNC(channel);
698
699 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
700 port->icount.tx++;
701
702 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
703 uart_write_wakeup(&up->port);
704 }
705 }
706
707 /* The port lock is held. */
708 static void sunzilog_stop_rx(struct uart_port *port)
709 {
710 struct uart_sunzilog_port *up = UART_ZILOG(port);
711 struct zilog_channel __iomem *channel;
712
713 if (ZS_IS_CONS(up))
714 return;
715
716 channel = ZILOG_CHANNEL_FROM_PORT(port);
717
718 /* Disable all RX interrupts. */
719 up->curregs[R1] &= ~RxINT_MASK;
720 sunzilog_maybe_update_regs(up, channel);
721 }
722
723 /* The port lock is held. */
724 static void sunzilog_enable_ms(struct uart_port *port)
725 {
726 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
727 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
728 unsigned char new_reg;
729
730 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
731 if (new_reg != up->curregs[R15]) {
732 up->curregs[R15] = new_reg;
733
734 /* NOTE: Not subject to 'transmitter active' rule. */
735 write_zsreg(channel, R15, up->curregs[R15]);
736 }
737 }
738
739 /* The port lock is not held. */
740 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
741 {
742 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
743 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
744 unsigned char set_bits, clear_bits, new_reg;
745 unsigned long flags;
746
747 set_bits = clear_bits = 0;
748
749 if (break_state)
750 set_bits |= SND_BRK;
751 else
752 clear_bits |= SND_BRK;
753
754 spin_lock_irqsave(&port->lock, flags);
755
756 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
757 if (new_reg != up->curregs[R5]) {
758 up->curregs[R5] = new_reg;
759
760 /* NOTE: Not subject to 'transmitter active' rule. */
761 write_zsreg(channel, R5, up->curregs[R5]);
762 }
763
764 spin_unlock_irqrestore(&port->lock, flags);
765 }
766
767 static void __sunzilog_startup(struct uart_sunzilog_port *up)
768 {
769 struct zilog_channel __iomem *channel;
770
771 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
772 up->prev_status = readb(&channel->control);
773
774 /* Enable receiver and transmitter. */
775 up->curregs[R3] |= RxENAB;
776 up->curregs[R5] |= TxENAB;
777
778 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
779 sunzilog_maybe_update_regs(up, channel);
780 }
781
782 static int sunzilog_startup(struct uart_port *port)
783 {
784 struct uart_sunzilog_port *up = UART_ZILOG(port);
785 unsigned long flags;
786
787 if (ZS_IS_CONS(up))
788 return 0;
789
790 spin_lock_irqsave(&port->lock, flags);
791 __sunzilog_startup(up);
792 spin_unlock_irqrestore(&port->lock, flags);
793 return 0;
794 }
795
796 /*
797 * The test for ZS_IS_CONS is explained by the following e-mail:
798 *****
799 * From: Russell King <rmk@arm.linux.org.uk>
800 * Date: Sun, 8 Dec 2002 10:18:38 +0000
801 *
802 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
803 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
804 * > and I noticed that something is not right with reference
805 * > counting in this case. It seems that when the console
806 * > is open by kernel initially, this is not accounted
807 * > as an open, and uart_startup is not called.
808 *
809 * That is correct. We are unable to call uart_startup when the serial
810 * console is initialised because it may need to allocate memory (as
811 * request_irq does) and the memory allocators may not have been
812 * initialised.
813 *
814 * 1. initialise the port into a state where it can send characters in the
815 * console write method.
816 *
817 * 2. don't do the actual hardware shutdown in your shutdown() method (but
818 * do the normal software shutdown - ie, free irqs etc)
819 *****
820 */
821 static void sunzilog_shutdown(struct uart_port *port)
822 {
823 struct uart_sunzilog_port *up = UART_ZILOG(port);
824 struct zilog_channel __iomem *channel;
825 unsigned long flags;
826
827 if (ZS_IS_CONS(up))
828 return;
829
830 spin_lock_irqsave(&port->lock, flags);
831
832 channel = ZILOG_CHANNEL_FROM_PORT(port);
833
834 /* Disable receiver and transmitter. */
835 up->curregs[R3] &= ~RxENAB;
836 up->curregs[R5] &= ~TxENAB;
837
838 /* Disable all interrupts and BRK assertion. */
839 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
840 up->curregs[R5] &= ~SND_BRK;
841 sunzilog_maybe_update_regs(up, channel);
842
843 spin_unlock_irqrestore(&port->lock, flags);
844 }
845
846 /* Shared by TTY driver and serial console setup. The port lock is held
847 * and local interrupts are disabled.
848 */
849 static void
850 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
851 unsigned int iflag, int brg)
852 {
853
854 up->curregs[R10] = NRZ;
855 up->curregs[R11] = TCBR | RCBR;
856
857 /* Program BAUD and clock source. */
858 up->curregs[R4] &= ~XCLK_MASK;
859 up->curregs[R4] |= X16CLK;
860 up->curregs[R12] = brg & 0xff;
861 up->curregs[R13] = (brg >> 8) & 0xff;
862 up->curregs[R14] = BRSRC | BRENAB;
863
864 /* Character size, stop bits, and parity. */
865 up->curregs[3] &= ~RxN_MASK;
866 up->curregs[5] &= ~TxN_MASK;
867 switch (cflag & CSIZE) {
868 case CS5:
869 up->curregs[3] |= Rx5;
870 up->curregs[5] |= Tx5;
871 up->parity_mask = 0x1f;
872 break;
873 case CS6:
874 up->curregs[3] |= Rx6;
875 up->curregs[5] |= Tx6;
876 up->parity_mask = 0x3f;
877 break;
878 case CS7:
879 up->curregs[3] |= Rx7;
880 up->curregs[5] |= Tx7;
881 up->parity_mask = 0x7f;
882 break;
883 case CS8:
884 default:
885 up->curregs[3] |= Rx8;
886 up->curregs[5] |= Tx8;
887 up->parity_mask = 0xff;
888 break;
889 };
890 up->curregs[4] &= ~0x0c;
891 if (cflag & CSTOPB)
892 up->curregs[4] |= SB2;
893 else
894 up->curregs[4] |= SB1;
895 if (cflag & PARENB)
896 up->curregs[4] |= PAR_ENAB;
897 else
898 up->curregs[4] &= ~PAR_ENAB;
899 if (!(cflag & PARODD))
900 up->curregs[4] |= PAR_EVEN;
901 else
902 up->curregs[4] &= ~PAR_EVEN;
903
904 up->port.read_status_mask = Rx_OVR;
905 if (iflag & INPCK)
906 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
907 if (iflag & (BRKINT | PARMRK))
908 up->port.read_status_mask |= BRK_ABRT;
909
910 up->port.ignore_status_mask = 0;
911 if (iflag & IGNPAR)
912 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
913 if (iflag & IGNBRK) {
914 up->port.ignore_status_mask |= BRK_ABRT;
915 if (iflag & IGNPAR)
916 up->port.ignore_status_mask |= Rx_OVR;
917 }
918
919 if ((cflag & CREAD) == 0)
920 up->port.ignore_status_mask = 0xff;
921 }
922
923 /* The port lock is not held. */
924 static void
925 sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
926 struct ktermios *old)
927 {
928 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
929 unsigned long flags;
930 int baud, brg;
931
932 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
933
934 spin_lock_irqsave(&up->port.lock, flags);
935
936 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
937
938 sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
939
940 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
941 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
942 else
943 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
944
945 up->cflag = termios->c_cflag;
946
947 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
948
949 uart_update_timeout(port, termios->c_cflag, baud);
950
951 spin_unlock_irqrestore(&up->port.lock, flags);
952 }
953
954 static const char *sunzilog_type(struct uart_port *port)
955 {
956 return "zs";
957 }
958
959 /* We do not request/release mappings of the registers here, this
960 * happens at early serial probe time.
961 */
962 static void sunzilog_release_port(struct uart_port *port)
963 {
964 }
965
966 static int sunzilog_request_port(struct uart_port *port)
967 {
968 return 0;
969 }
970
971 /* These do not need to do anything interesting either. */
972 static void sunzilog_config_port(struct uart_port *port, int flags)
973 {
974 }
975
976 /* We do not support letting the user mess with the divisor, IRQ, etc. */
977 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
978 {
979 return -EINVAL;
980 }
981
982 static struct uart_ops sunzilog_pops = {
983 .tx_empty = sunzilog_tx_empty,
984 .set_mctrl = sunzilog_set_mctrl,
985 .get_mctrl = sunzilog_get_mctrl,
986 .stop_tx = sunzilog_stop_tx,
987 .start_tx = sunzilog_start_tx,
988 .stop_rx = sunzilog_stop_rx,
989 .enable_ms = sunzilog_enable_ms,
990 .break_ctl = sunzilog_break_ctl,
991 .startup = sunzilog_startup,
992 .shutdown = sunzilog_shutdown,
993 .set_termios = sunzilog_set_termios,
994 .type = sunzilog_type,
995 .release_port = sunzilog_release_port,
996 .request_port = sunzilog_request_port,
997 .config_port = sunzilog_config_port,
998 .verify_port = sunzilog_verify_port,
999 };
1000
1001 static struct uart_sunzilog_port *sunzilog_port_table;
1002 static struct zilog_layout __iomem **sunzilog_chip_regs;
1003
1004 static struct uart_sunzilog_port *sunzilog_irq_chain;
1005
1006 static struct uart_driver sunzilog_reg = {
1007 .owner = THIS_MODULE,
1008 .driver_name = "ttyS",
1009 .dev_name = "ttyS",
1010 .major = TTY_MAJOR,
1011 };
1012
1013 static int __init sunzilog_alloc_tables(void)
1014 {
1015 struct uart_sunzilog_port *up;
1016 unsigned long size;
1017 int i;
1018
1019 size = NUM_CHANNELS * sizeof(struct uart_sunzilog_port);
1020 sunzilog_port_table = kzalloc(size, GFP_KERNEL);
1021 if (!sunzilog_port_table)
1022 return -ENOMEM;
1023
1024 for (i = 0; i < NUM_CHANNELS; i++) {
1025 up = &sunzilog_port_table[i];
1026
1027 spin_lock_init(&up->port.lock);
1028
1029 if (i == 0)
1030 sunzilog_irq_chain = up;
1031
1032 if (i < NUM_CHANNELS - 1)
1033 up->next = up + 1;
1034 else
1035 up->next = NULL;
1036 }
1037
1038 size = NUM_SUNZILOG * sizeof(struct zilog_layout __iomem *);
1039 sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
1040 if (!sunzilog_chip_regs) {
1041 kfree(sunzilog_port_table);
1042 sunzilog_irq_chain = NULL;
1043 return -ENOMEM;
1044 }
1045
1046 return 0;
1047 }
1048
1049 static void sunzilog_free_tables(void)
1050 {
1051 kfree(sunzilog_port_table);
1052 sunzilog_irq_chain = NULL;
1053 kfree(sunzilog_chip_regs);
1054 }
1055
1056 #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
1057
1058 static void sunzilog_putchar(struct uart_port *port, int ch)
1059 {
1060 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
1061 int loops = ZS_PUT_CHAR_MAX_DELAY;
1062
1063 /* This is a timed polling loop so do not switch the explicit
1064 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
1065 */
1066 do {
1067 unsigned char val = readb(&channel->control);
1068 if (val & Tx_BUF_EMP) {
1069 ZSDELAY();
1070 break;
1071 }
1072 udelay(5);
1073 } while (--loops);
1074
1075 writeb(ch, &channel->data);
1076 ZSDELAY();
1077 ZS_WSYNC(channel);
1078 }
1079
1080 #ifdef CONFIG_SERIO
1081
1082 static DEFINE_SPINLOCK(sunzilog_serio_lock);
1083
1084 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1085 {
1086 struct uart_sunzilog_port *up = serio->port_data;
1087 unsigned long flags;
1088
1089 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1090
1091 sunzilog_putchar(&up->port, ch);
1092
1093 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1094
1095 return 0;
1096 }
1097
1098 static int sunzilog_serio_open(struct serio *serio)
1099 {
1100 struct uart_sunzilog_port *up = serio->port_data;
1101 unsigned long flags;
1102 int ret;
1103
1104 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1105 if (!up->serio_open) {
1106 up->serio_open = 1;
1107 ret = 0;
1108 } else
1109 ret = -EBUSY;
1110 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1111
1112 return ret;
1113 }
1114
1115 static void sunzilog_serio_close(struct serio *serio)
1116 {
1117 struct uart_sunzilog_port *up = serio->port_data;
1118 unsigned long flags;
1119
1120 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1121 up->serio_open = 0;
1122 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1123 }
1124
1125 #endif /* CONFIG_SERIO */
1126
1127 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1128 static void
1129 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1130 {
1131 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1132 unsigned long flags;
1133
1134 spin_lock_irqsave(&up->port.lock, flags);
1135 uart_console_write(&up->port, s, count, sunzilog_putchar);
1136 udelay(2);
1137 spin_unlock_irqrestore(&up->port.lock, flags);
1138 }
1139
1140 static int __init sunzilog_console_setup(struct console *con, char *options)
1141 {
1142 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1143 unsigned long flags;
1144 int baud, brg;
1145
1146 if (up->port.type != PORT_SUNZILOG)
1147 return -1;
1148
1149 printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1150 (sunzilog_reg.minor - 64) + con->index, con->index);
1151
1152 /* Get firmware console settings. */
1153 sunserial_console_termios(con);
1154
1155 /* Firmware console speed is limited to 150-->38400 baud so
1156 * this hackish cflag thing is OK.
1157 */
1158 switch (con->cflag & CBAUD) {
1159 case B150: baud = 150; break;
1160 case B300: baud = 300; break;
1161 case B600: baud = 600; break;
1162 case B1200: baud = 1200; break;
1163 case B2400: baud = 2400; break;
1164 case B4800: baud = 4800; break;
1165 default: case B9600: baud = 9600; break;
1166 case B19200: baud = 19200; break;
1167 case B38400: baud = 38400; break;
1168 };
1169
1170 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1171
1172 spin_lock_irqsave(&up->port.lock, flags);
1173
1174 up->curregs[R15] = BRKIE;
1175 sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1176
1177 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1178 __sunzilog_startup(up);
1179
1180 spin_unlock_irqrestore(&up->port.lock, flags);
1181
1182 return 0;
1183 }
1184
1185 static struct console sunzilog_console_ops = {
1186 .name = "ttyS",
1187 .write = sunzilog_console_write,
1188 .device = uart_console_device,
1189 .setup = sunzilog_console_setup,
1190 .flags = CON_PRINTBUFFER,
1191 .index = -1,
1192 .data = &sunzilog_reg,
1193 };
1194
1195 static inline struct console *SUNZILOG_CONSOLE(void)
1196 {
1197 int i;
1198
1199 if (con_is_present())
1200 return NULL;
1201
1202 for (i = 0; i < NUM_CHANNELS; i++) {
1203 int this_minor = sunzilog_reg.minor + i;
1204
1205 if ((this_minor - 64) == (serial_console - 1))
1206 break;
1207 }
1208 if (i == NUM_CHANNELS)
1209 return NULL;
1210
1211 sunzilog_console_ops.index = i;
1212 sunzilog_port_table[i].flags |= SUNZILOG_FLAG_IS_CONS;
1213
1214 return &sunzilog_console_ops;
1215 }
1216
1217 #else
1218 #define SUNZILOG_CONSOLE() (NULL)
1219 #endif
1220
1221 static void __init sunzilog_init_kbdms(struct uart_sunzilog_port *up, int channel)
1222 {
1223 int baud, brg;
1224
1225 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1226 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1227 baud = 1200;
1228 } else {
1229 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1230 baud = 4800;
1231 }
1232
1233 up->curregs[R15] = BRKIE;
1234 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1235 sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1236 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1237 __sunzilog_startup(up);
1238 }
1239
1240 #ifdef CONFIG_SERIO
1241 static void __init sunzilog_register_serio(struct uart_sunzilog_port *up)
1242 {
1243 struct serio *serio = &up->serio;
1244
1245 serio->port_data = up;
1246
1247 serio->id.type = SERIO_RS232;
1248 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1249 serio->id.proto = SERIO_SUNKBD;
1250 strlcpy(serio->name, "zskbd", sizeof(serio->name));
1251 } else {
1252 serio->id.proto = SERIO_SUN;
1253 serio->id.extra = 1;
1254 strlcpy(serio->name, "zsms", sizeof(serio->name));
1255 }
1256 strlcpy(serio->phys,
1257 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1258 "zs/serio0" : "zs/serio1"),
1259 sizeof(serio->phys));
1260
1261 serio->write = sunzilog_serio_write;
1262 serio->open = sunzilog_serio_open;
1263 serio->close = sunzilog_serio_close;
1264 serio->dev.parent = up->port.dev;
1265
1266 serio_register_port(serio);
1267 }
1268 #endif
1269
1270 static void __devinit sunzilog_init_hw(struct uart_sunzilog_port *up)
1271 {
1272 struct zilog_channel __iomem *channel;
1273 unsigned long flags;
1274 int baud, brg;
1275
1276 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1277
1278 spin_lock_irqsave(&up->port.lock, flags);
1279 if (ZS_IS_CHANNEL_A(up)) {
1280 write_zsreg(channel, R9, FHWRES);
1281 ZSDELAY_LONG();
1282 (void) read_zsreg(channel, R0);
1283 }
1284
1285 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1286 SUNZILOG_FLAG_CONS_MOUSE)) {
1287 sunzilog_init_kbdms(up, up->port.line);
1288 up->curregs[R9] |= (NV | MIE);
1289 write_zsreg(channel, R9, up->curregs[R9]);
1290 } else {
1291 /* Normal serial TTY. */
1292 up->parity_mask = 0xff;
1293 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1294 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1295 up->curregs[R3] = RxENAB | Rx8;
1296 up->curregs[R5] = TxENAB | Tx8;
1297 up->curregs[R9] = NV | MIE;
1298 up->curregs[R10] = NRZ;
1299 up->curregs[R11] = TCBR | RCBR;
1300 baud = 9600;
1301 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1302 up->curregs[R12] = (brg & 0xff);
1303 up->curregs[R13] = (brg >> 8) & 0xff;
1304 up->curregs[R14] = BRSRC | BRENAB;
1305 __load_zsregs(channel, up->curregs);
1306 write_zsreg(channel, R9, up->curregs[R9]);
1307 }
1308
1309 spin_unlock_irqrestore(&up->port.lock, flags);
1310
1311 #ifdef CONFIG_SERIO
1312 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1313 SUNZILOG_FLAG_CONS_MOUSE))
1314 sunzilog_register_serio(up);
1315 #endif
1316 }
1317
1318 static int zilog_irq = -1;
1319
1320 static int __devinit zs_probe(struct of_device *op, const struct of_device_id *match)
1321 {
1322 static int inst;
1323 struct uart_sunzilog_port *up;
1324 struct zilog_layout __iomem *rp;
1325 int keyboard_mouse;
1326 int err;
1327
1328 keyboard_mouse = 0;
1329 if (of_find_property(op->node, "keyboard", NULL))
1330 keyboard_mouse = 1;
1331
1332 sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
1333 sizeof(struct zilog_layout),
1334 "zs");
1335 if (!sunzilog_chip_regs[inst])
1336 return -ENOMEM;
1337
1338 rp = sunzilog_chip_regs[inst];
1339
1340 if (zilog_irq == -1)
1341 zilog_irq = op->irqs[0];
1342
1343 up = &sunzilog_port_table[inst * 2];
1344
1345 /* Channel A */
1346 up[0].port.mapbase = op->resource[0].start + 0x00;
1347 up[0].port.membase = (void __iomem *) &rp->channelA;
1348 up[0].port.iotype = UPIO_MEM;
1349 up[0].port.irq = op->irqs[0];
1350 up[0].port.uartclk = ZS_CLOCK;
1351 up[0].port.fifosize = 1;
1352 up[0].port.ops = &sunzilog_pops;
1353 up[0].port.type = PORT_SUNZILOG;
1354 up[0].port.flags = 0;
1355 up[0].port.line = (inst * 2) + 0;
1356 up[0].port.dev = &op->dev;
1357 up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1358 if (keyboard_mouse)
1359 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1360 sunzilog_init_hw(&up[0]);
1361
1362 /* Channel B */
1363 up[1].port.mapbase = op->resource[0].start + 0x04;
1364 up[1].port.membase = (void __iomem *) &rp->channelB;
1365 up[1].port.iotype = UPIO_MEM;
1366 up[1].port.irq = op->irqs[0];
1367 up[1].port.uartclk = ZS_CLOCK;
1368 up[1].port.fifosize = 1;
1369 up[1].port.ops = &sunzilog_pops;
1370 up[1].port.type = PORT_SUNZILOG;
1371 up[1].port.flags = 0;
1372 up[1].port.line = (inst * 2) + 1;
1373 up[1].port.dev = &op->dev;
1374 up[1].flags |= 0;
1375 if (keyboard_mouse)
1376 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1377 sunzilog_init_hw(&up[1]);
1378
1379 if (!keyboard_mouse) {
1380 err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1381 if (err) {
1382 of_iounmap(&op->resource[0],
1383 rp, sizeof(struct zilog_layout));
1384 return err;
1385 }
1386 err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1387 if (err) {
1388 uart_remove_one_port(&sunzilog_reg, &up[0].port);
1389 of_iounmap(&op->resource[0],
1390 rp, sizeof(struct zilog_layout));
1391 return err;
1392 }
1393 } else {
1394 printk(KERN_INFO "%s: Keyboard at MMIO %lx (irq = %d) "
1395 "is a zs\n",
1396 op->dev.bus_id, up[0].port.mapbase, op->irqs[0]);
1397 printk(KERN_INFO "%s: Mouse at MMIO %lx (irq = %d) "
1398 "is a zs\n",
1399 op->dev.bus_id, up[1].port.mapbase, op->irqs[0]);
1400 }
1401
1402 dev_set_drvdata(&op->dev, &up[0]);
1403
1404 inst++;
1405
1406 return 0;
1407 }
1408
1409 static void __devexit zs_remove_one(struct uart_sunzilog_port *up)
1410 {
1411 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1412 #ifdef CONFIG_SERIO
1413 serio_unregister_port(&up->serio);
1414 #endif
1415 } else
1416 uart_remove_one_port(&sunzilog_reg, &up->port);
1417 }
1418
1419 static int __devexit zs_remove(struct of_device *op)
1420 {
1421 struct uart_sunzilog_port *up = dev_get_drvdata(&op->dev);
1422 struct zilog_layout __iomem *regs;
1423
1424 zs_remove_one(&up[0]);
1425 zs_remove_one(&up[1]);
1426
1427 regs = sunzilog_chip_regs[up[0].port.line / 2];
1428 of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
1429
1430 dev_set_drvdata(&op->dev, NULL);
1431
1432 return 0;
1433 }
1434
1435 static struct of_device_id zs_match[] = {
1436 {
1437 .name = "zs",
1438 },
1439 {},
1440 };
1441 MODULE_DEVICE_TABLE(of, zs_match);
1442
1443 static struct of_platform_driver zs_driver = {
1444 .name = "zs",
1445 .match_table = zs_match,
1446 .probe = zs_probe,
1447 .remove = __devexit_p(zs_remove),
1448 };
1449
1450 static int __init sunzilog_init(void)
1451 {
1452 struct device_node *dp;
1453 int err, uart_count;
1454 int num_keybms;
1455
1456 NUM_SUNZILOG = 0;
1457 num_keybms = 0;
1458 for_each_node_by_name(dp, "zs") {
1459 NUM_SUNZILOG++;
1460 if (of_find_property(dp, "keyboard", NULL))
1461 num_keybms++;
1462 }
1463
1464 uart_count = 0;
1465 if (NUM_SUNZILOG) {
1466 int uart_count;
1467
1468 err = sunzilog_alloc_tables();
1469 if (err)
1470 goto out;
1471
1472 uart_count = (NUM_SUNZILOG * 2) - (2 * num_keybms);
1473
1474 sunzilog_reg.nr = uart_count;
1475 sunzilog_reg.minor = sunserial_current_minor;
1476 err = uart_register_driver(&sunzilog_reg);
1477 if (err)
1478 goto out_free_tables;
1479
1480 sunzilog_reg.tty_driver->name_base = sunzilog_reg.minor - 64;
1481 sunzilog_reg.cons = SUNZILOG_CONSOLE();
1482
1483 sunserial_current_minor += uart_count;
1484 }
1485
1486 err = of_register_driver(&zs_driver, &of_bus_type);
1487 if (err)
1488 goto out_unregister_uart;
1489
1490 if (zilog_irq != -1) {
1491 err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
1492 "zs", sunzilog_irq_chain);
1493 if (err)
1494 goto out_unregister_driver;
1495 }
1496
1497 out:
1498 return err;
1499
1500 out_unregister_driver:
1501 of_unregister_driver(&zs_driver);
1502
1503 out_unregister_uart:
1504 if (NUM_SUNZILOG) {
1505 uart_unregister_driver(&sunzilog_reg);
1506 sunzilog_reg.cons = NULL;
1507 }
1508
1509 out_free_tables:
1510 sunzilog_free_tables();
1511 goto out;
1512 }
1513
1514 static void __exit sunzilog_exit(void)
1515 {
1516 of_unregister_driver(&zs_driver);
1517
1518 if (zilog_irq != -1) {
1519 free_irq(zilog_irq, sunzilog_irq_chain);
1520 zilog_irq = -1;
1521 }
1522
1523 if (NUM_SUNZILOG) {
1524 uart_unregister_driver(&sunzilog_reg);
1525 sunzilog_free_tables();
1526 }
1527 }
1528
1529 module_init(sunzilog_init);
1530 module_exit(sunzilog_exit);
1531
1532 MODULE_AUTHOR("David S. Miller");
1533 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1534 MODULE_VERSION("2.0");
1535 MODULE_LICENSE("GPL");
cpufreq for S3C2410