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sky2: dont change LED after autoneg
[linux-2.6/s3c2410-cpufreq.git] / drivers / net / sky2.c
blob3c08db41cec46f076f28a78424ccd40f6658c74e
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/aer.h>
35 #include <linux/ip.h>
36 #include <net/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/in.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/debugfs.h>
44 #include <linux/mii.h>
45
46 #include <asm/irq.h>
47
48 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49 #define SKY2_VLAN_TAG_USED 1
50 #endif
51
52 #include "sky2.h"
53
54 #define DRV_NAME "sky2"
55 #define DRV_VERSION "1.19"
56 #define PFX DRV_NAME " "
57
58 /*
59 * The Yukon II chipset takes 64 bit command blocks (called list elements)
60 * that are organized into three (receive, transmit, status) different rings
61 * similar to Tigon3.
62 */
63
64 #define RX_LE_SIZE 1024
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define RX_SKB_ALIGN 8
69
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define TX_WATCHDOG (5 * HZ)
78 #define NAPI_WEIGHT 64
79 #define PHY_RETRIES 1000
80
81 #define SKY2_EEPROM_MAGIC 0x9955aabb
82
83
84 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85
86 static const u32 default_msg =
87 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
88 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
89 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90
91 static int debug = -1; /* defaults above */
92 module_param(debug, int, 0);
93 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
95 static int copybreak __read_mostly = 128;
96 module_param(copybreak, int, 0);
97 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98
99 static int disable_msi = 0;
100 module_param(disable_msi, int, 0);
101 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102
103 static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
137 { 0 }
138 };
139
140 MODULE_DEVICE_TABLE(pci, sky2_id_table);
141
142 /* Avoid conditionals by using array */
143 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
144 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
145 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
146
147 /* This driver supports yukon2 chipset only */
148 static const char *yukon2_name[] = {
149 "XL", /* 0xb3 */
150 "EC Ultra", /* 0xb4 */
151 "Extreme", /* 0xb5 */
152 "EC", /* 0xb6 */
153 "FE", /* 0xb7 */
154 "FE+", /* 0xb8 */
155 };
156
157 static void sky2_set_multicast(struct net_device *dev);
158
159 /* Access to PHY via serial interconnect */
160 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
161 {
162 int i;
163
164 gma_write16(hw, port, GM_SMI_DATA, val);
165 gma_write16(hw, port, GM_SMI_CTRL,
166 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
167
168 for (i = 0; i < PHY_RETRIES; i++) {
169 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
170 if (ctrl == 0xffff)
171 goto io_error;
172
173 if (!(ctrl & GM_SMI_CT_BUSY))
174 return 0;
175
176 udelay(10);
177 }
178
179 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
180 return -ETIMEDOUT;
181
182 io_error:
183 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
184 return -EIO;
185 }
186
187 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
188 {
189 int i;
190
191 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
192 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
193
194 for (i = 0; i < PHY_RETRIES; i++) {
195 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
196 if (ctrl == 0xffff)
197 goto io_error;
198
199 if (ctrl & GM_SMI_CT_RD_VAL) {
200 *val = gma_read16(hw, port, GM_SMI_DATA);
201 return 0;
202 }
203
204 udelay(10);
205 }
206
207 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
208 return -ETIMEDOUT;
209 io_error:
210 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
211 return -EIO;
212 }
213
214 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
215 {
216 u16 v;
217 __gm_phy_read(hw, port, reg, &v);
218 return v;
219 }
220
221
222 static void sky2_power_on(struct sky2_hw *hw)
223 {
224 /* switch power to VCC (WA for VAUX problem) */
225 sky2_write8(hw, B0_POWER_CTRL,
226 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
227
228 /* disable Core Clock Division, */
229 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
230
231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
232 /* enable bits are inverted */
233 sky2_write8(hw, B2_Y2_CLK_GATE,
234 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
235 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
236 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
237 else
238 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
239
240 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
241 struct pci_dev *pdev = hw->pdev;
242 u32 reg;
243
244 pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
245
246 pci_read_config_dword(pdev, PCI_DEV_REG4, &reg);
247 /* set all bits to 0 except bits 15..12 and 8 */
248 reg &= P_ASPM_CONTROL_MSK;
249 pci_write_config_dword(pdev, PCI_DEV_REG4, reg);
250
251 pci_read_config_dword(pdev, PCI_DEV_REG5, &reg);
252 /* set all bits to 0 except bits 28 & 27 */
253 reg &= P_CTL_TIM_VMAIN_AV_MSK;
254 pci_write_config_dword(pdev, PCI_DEV_REG5, reg);
255
256 pci_write_config_dword(pdev, PCI_CFG_REG_1, 0);
257
258 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
259 reg = sky2_read32(hw, B2_GP_IO);
260 reg |= GLB_GPIO_STAT_RACE_DIS;
261 sky2_write32(hw, B2_GP_IO, reg);
262
263 sky2_read32(hw, B2_GP_IO);
264 }
265 }
266
267 static void sky2_power_aux(struct sky2_hw *hw)
268 {
269 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
270 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
271 else
272 /* enable bits are inverted */
273 sky2_write8(hw, B2_Y2_CLK_GATE,
274 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
275 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
276 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
277
278 /* switch power to VAUX */
279 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
280 sky2_write8(hw, B0_POWER_CTRL,
281 (PC_VAUX_ENA | PC_VCC_ENA |
282 PC_VAUX_ON | PC_VCC_OFF));
283 }
284
285 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
286 {
287 u16 reg;
288
289 /* disable all GMAC IRQ's */
290 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
291 /* disable PHY IRQs */
292 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
293
294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
295 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
298
299 reg = gma_read16(hw, port, GM_RX_CTRL);
300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
301 gma_write16(hw, port, GM_RX_CTRL, reg);
302 }
303
304 /* flow control to advertise bits */
305 static const u16 copper_fc_adv[] = {
306 [FC_NONE] = 0,
307 [FC_TX] = PHY_M_AN_ASP,
308 [FC_RX] = PHY_M_AN_PC,
309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
310 };
311
312 /* flow control to advertise bits when using 1000BaseX */
313 static const u16 fiber_fc_adv[] = {
314 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
315 [FC_TX] = PHY_M_P_ASYM_MD_X,
316 [FC_RX] = PHY_M_P_SYM_MD_X,
317 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
318 };
319
320 /* flow control to GMA disable bits */
321 static const u16 gm_fc_disable[] = {
322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
323 [FC_TX] = GM_GPCR_FC_RX_DIS,
324 [FC_RX] = GM_GPCR_FC_TX_DIS,
325 [FC_BOTH] = 0,
326 };
327
328
329 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
330 {
331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
333
334 if (sky2->autoneg == AUTONEG_ENABLE &&
335 !(hw->flags & SKY2_HW_NEWER_PHY)) {
336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
337
338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
339 PHY_M_EC_MAC_S_MSK);
340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
341
342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
343 if (hw->chip_id == CHIP_ID_YUKON_EC)
344 /* set downshift counter to 3x and enable downshift */
345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
346 else
347 /* set master & slave downshift counter to 1x */
348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
349
350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
351 }
352
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
354 if (sky2_is_copper(hw)) {
355 if (!(hw->flags & SKY2_HW_GIGABIT)) {
356 /* enable automatic crossover */
357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
358
359 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
360 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
361 u16 spec;
362
363 /* Enable Class A driver for FE+ A0 */
364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
365 spec |= PHY_M_FESC_SEL_CL_A;
366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
367 }
368 } else {
369 /* disable energy detect */
370 ctrl &= ~PHY_M_PC_EN_DET_MSK;
371
372 /* enable automatic crossover */
373 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
374
375 /* downshift on PHY 88E1112 and 88E1149 is changed */
376 if (sky2->autoneg == AUTONEG_ENABLE
377 && (hw->flags & SKY2_HW_NEWER_PHY)) {
378 /* set downshift counter to 3x and enable downshift */
379 ctrl &= ~PHY_M_PC_DSC_MSK;
380 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
381 }
382 }
383 } else {
384 /* workaround for deviation #4.88 (CRC errors) */
385 /* disable Automatic Crossover */
386
387 ctrl &= ~PHY_M_PC_MDIX_MSK;
388 }
389
390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
391
392 /* special setup for PHY 88E1112 Fiber */
393 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
394 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
395
396 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl &= ~PHY_M_MAC_MD_MSK;
400 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
402
403 if (hw->pmd_type == 'P') {
404 /* select page 1 to access Fiber registers */
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
406
407 /* for SFP-module set SIGDET polarity to low */
408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
409 ctrl |= PHY_M_FIB_SIGD_POL;
410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
411 }
412
413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
414 }
415
416 ctrl = PHY_CT_RESET;
417 ct1000 = 0;
418 adv = PHY_AN_CSMA;
419 reg = 0;
420
421 if (sky2->autoneg == AUTONEG_ENABLE) {
422 if (sky2_is_copper(hw)) {
423 if (sky2->advertising & ADVERTISED_1000baseT_Full)
424 ct1000 |= PHY_M_1000C_AFD;
425 if (sky2->advertising & ADVERTISED_1000baseT_Half)
426 ct1000 |= PHY_M_1000C_AHD;
427 if (sky2->advertising & ADVERTISED_100baseT_Full)
428 adv |= PHY_M_AN_100_FD;
429 if (sky2->advertising & ADVERTISED_100baseT_Half)
430 adv |= PHY_M_AN_100_HD;
431 if (sky2->advertising & ADVERTISED_10baseT_Full)
432 adv |= PHY_M_AN_10_FD;
433 if (sky2->advertising & ADVERTISED_10baseT_Half)
434 adv |= PHY_M_AN_10_HD;
435
436 adv |= copper_fc_adv[sky2->flow_mode];
437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2->advertising & ADVERTISED_1000baseT_Full)
439 adv |= PHY_M_AN_1000X_AFD;
440 if (sky2->advertising & ADVERTISED_1000baseT_Half)
441 adv |= PHY_M_AN_1000X_AHD;
442
443 adv |= fiber_fc_adv[sky2->flow_mode];
444 }
445
446 /* Restart Auto-negotiation */
447 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
448 } else {
449 /* forced speed/duplex settings */
450 ct1000 = PHY_M_1000C_MSE;
451
452 /* Disable auto update for duplex flow control and speed */
453 reg |= GM_GPCR_AU_ALL_DIS;
454
455 switch (sky2->speed) {
456 case SPEED_1000:
457 ctrl |= PHY_CT_SP1000;
458 reg |= GM_GPCR_SPEED_1000;
459 break;
460 case SPEED_100:
461 ctrl |= PHY_CT_SP100;
462 reg |= GM_GPCR_SPEED_100;
463 break;
464 }
465
466 if (sky2->duplex == DUPLEX_FULL) {
467 reg |= GM_GPCR_DUP_FULL;
468 ctrl |= PHY_CT_DUP_MD;
469 } else if (sky2->speed < SPEED_1000)
470 sky2->flow_mode = FC_NONE;
471
472
473 reg |= gm_fc_disable[sky2->flow_mode];
474
475 /* Forward pause packets to GMAC? */
476 if (sky2->flow_mode & FC_RX)
477 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
478 else
479 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
480 }
481
482 gma_write16(hw, port, GM_GP_CTRL, reg);
483
484 if (hw->flags & SKY2_HW_GIGABIT)
485 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
486
487 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
488 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
489
490 /* Setup Phy LED's */
491 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
492 ledover = 0;
493
494 switch (hw->chip_id) {
495 case CHIP_ID_YUKON_FE:
496 /* on 88E3082 these bits are at 11..9 (shifted left) */
497 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
498
499 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
500
501 /* delete ACT LED control bits */
502 ctrl &= ~PHY_M_FELP_LED1_MSK;
503 /* change ACT LED control to blink mode */
504 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
505 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
506 break;
507
508 case CHIP_ID_YUKON_FE_P:
509 /* Enable Link Partner Next Page */
510 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
511 ctrl |= PHY_M_PC_ENA_LIP_NP;
512
513 /* disable Energy Detect and enable scrambler */
514 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
515 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
516
517 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
518 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
519 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
520 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
521
522 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
523 break;
524
525 case CHIP_ID_YUKON_XL:
526 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
527
528 /* select page 3 to access LED control register */
529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
530
531 /* set LED Function Control register */
532 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
533 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
534 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
535 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
536 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
537
538 /* set Polarity Control register */
539 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
540 (PHY_M_POLC_LS1_P_MIX(4) |
541 PHY_M_POLC_IS0_P_MIX(4) |
542 PHY_M_POLC_LOS_CTRL(2) |
543 PHY_M_POLC_INIT_CTRL(2) |
544 PHY_M_POLC_STA1_CTRL(2) |
545 PHY_M_POLC_STA0_CTRL(2)));
546
547 /* restore page register */
548 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
549 break;
550
551 case CHIP_ID_YUKON_EC_U:
552 case CHIP_ID_YUKON_EX:
553 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
554
555 /* select page 3 to access LED control register */
556 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
557
558 /* set LED Function Control register */
559 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
560 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
561 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
562 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
563 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
564
565 /* set Blink Rate in LED Timer Control Register */
566 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
567 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
568 /* restore page register */
569 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
570 break;
571
572 default:
573 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
574 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
575 /* turn off the Rx LED (LED_RX) */
576 ledover &= ~PHY_M_LED_MO_RX;
577 }
578
579 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
580 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
581 /* apply fixes in PHY AFE */
582 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
583
584 /* increase differential signal amplitude in 10BASE-T */
585 gm_phy_write(hw, port, 0x18, 0xaa99);
586 gm_phy_write(hw, port, 0x17, 0x2011);
587
588 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
589 gm_phy_write(hw, port, 0x18, 0xa204);
590 gm_phy_write(hw, port, 0x17, 0x2002);
591
592 /* set page register to 0 */
593 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
594 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
595 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
596 /* apply workaround for integrated resistors calibration */
597 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
598 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
599 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
600 /* no effect on Yukon-XL */
601 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
602
603 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
604 /* turn on 100 Mbps LED (LED_LINK100) */
605 ledover |= PHY_M_LED_MO_100;
606 }
607
608 if (ledover)
609 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
610
611 }
612
613 /* Enable phy interrupt on auto-negotiation complete (or link up) */
614 if (sky2->autoneg == AUTONEG_ENABLE)
615 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
616 else
617 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
618 }
619
620 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
621 {
622 struct pci_dev *pdev = hw->pdev;
623 u32 reg1;
624 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
625 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
626
627 pci_read_config_dword(pdev, PCI_DEV_REG1, &reg1);
628 /* Turn on/off phy power saving */
629 if (onoff)
630 reg1 &= ~phy_power[port];
631 else
632 reg1 |= phy_power[port];
633
634 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
635 reg1 |= coma_mode[port];
636
637 pci_write_config_dword(pdev, PCI_DEV_REG1, reg1);
638 pci_read_config_dword(pdev, PCI_DEV_REG1, &reg1);
639
640 udelay(100);
641 }
642
643 /* Force a renegotiation */
644 static void sky2_phy_reinit(struct sky2_port *sky2)
645 {
646 spin_lock_bh(&sky2->phy_lock);
647 sky2_phy_init(sky2->hw, sky2->port);
648 spin_unlock_bh(&sky2->phy_lock);
649 }
650
651 /* Put device in state to listen for Wake On Lan */
652 static void sky2_wol_init(struct sky2_port *sky2)
653 {
654 struct sky2_hw *hw = sky2->hw;
655 unsigned port = sky2->port;
656 enum flow_control save_mode;
657 u16 ctrl;
658 u32 reg1;
659
660 /* Bring hardware out of reset */
661 sky2_write16(hw, B0_CTST, CS_RST_CLR);
662 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
663
664 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
665 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
666
667 /* Force to 10/100
668 * sky2_reset will re-enable on resume
669 */
670 save_mode = sky2->flow_mode;
671 ctrl = sky2->advertising;
672
673 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
674 sky2->flow_mode = FC_NONE;
675 sky2_phy_power(hw, port, 1);
676 sky2_phy_reinit(sky2);
677
678 sky2->flow_mode = save_mode;
679 sky2->advertising = ctrl;
680
681 /* Set GMAC to no flow control and auto update for speed/duplex */
682 gma_write16(hw, port, GM_GP_CTRL,
683 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
684 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
685
686 /* Set WOL address */
687 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
688 sky2->netdev->dev_addr, ETH_ALEN);
689
690 /* Turn on appropriate WOL control bits */
691 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
692 ctrl = 0;
693 if (sky2->wol & WAKE_PHY)
694 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
695 else
696 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
697
698 if (sky2->wol & WAKE_MAGIC)
699 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
700 else
701 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
702
703 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
704 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
705
706 /* Turn on legacy PCI-Express PME mode */
707 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
708 reg1 |= PCI_Y2_PME_LEGACY;
709 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
710
711 /* block receiver */
712 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
713
714 }
715
716 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
717 {
718 struct net_device *dev = hw->dev[port];
719
720 if (dev->mtu <= ETH_DATA_LEN)
721 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
722 TX_JUMBO_DIS | TX_STFW_ENA);
723
724 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
725 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
726 TX_STFW_ENA | TX_JUMBO_ENA);
727 else {
728 /* set Tx GMAC FIFO Almost Empty Threshold */
729 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
730 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
731
732 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
733 TX_JUMBO_ENA | TX_STFW_DIS);
734
735 /* Can't do offload because of lack of store/forward */
736 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
737 }
738 }
739
740 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
741 {
742 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
743 u16 reg;
744 u32 rx_reg;
745 int i;
746 const u8 *addr = hw->dev[port]->dev_addr;
747
748 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
749 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
750
751 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
752
753 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
754 /* WA DEV_472 -- looks like crossed wires on port 2 */
755 /* clear GMAC 1 Control reset */
756 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
757 do {
758 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
759 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
760 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
761 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
762 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
763 }
764
765 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
766
767 /* Enable Transmit FIFO Underrun */
768 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
769
770 spin_lock_bh(&sky2->phy_lock);
771 sky2_phy_init(hw, port);
772 spin_unlock_bh(&sky2->phy_lock);
773
774 /* MIB clear */
775 reg = gma_read16(hw, port, GM_PHY_ADDR);
776 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
777
778 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
779 gma_read16(hw, port, i);
780 gma_write16(hw, port, GM_PHY_ADDR, reg);
781
782 /* transmit control */
783 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
784
785 /* receive control reg: unicast + multicast + no FCS */
786 gma_write16(hw, port, GM_RX_CTRL,
787 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
788
789 /* transmit flow control */
790 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
791
792 /* transmit parameter */
793 gma_write16(hw, port, GM_TX_PARAM,
794 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
795 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
796 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
797 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
798
799 /* serial mode register */
800 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
801 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
802
803 if (hw->dev[port]->mtu > ETH_DATA_LEN)
804 reg |= GM_SMOD_JUMBO_ENA;
805
806 gma_write16(hw, port, GM_SERIAL_MODE, reg);
807
808 /* virtual address for data */
809 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
810
811 /* physical address: used for pause frames */
812 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
813
814 /* ignore counter overflows */
815 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
816 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
817 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
818
819 /* Configure Rx MAC FIFO */
820 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
821 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
822 if (hw->chip_id == CHIP_ID_YUKON_EX ||
823 hw->chip_id == CHIP_ID_YUKON_FE_P)
824 rx_reg |= GMF_RX_OVER_ON;
825
826 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
827
828 /* Flush Rx MAC FIFO on any flow control or error */
829 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
830
831 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
832 reg = RX_GMF_FL_THR_DEF + 1;
833 /* Another magic mystery workaround from sk98lin */
834 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
835 hw->chip_rev == CHIP_REV_YU_FE2_A0)
836 reg = 0x178;
837 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
838
839 /* Configure Tx MAC FIFO */
840 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
841 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
842
843 /* On chips without ram buffer, pause is controled by MAC level */
844 if (sky2_read8(hw, B2_E_0) == 0) {
845 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
846 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
847
848 sky2_set_tx_stfwd(hw, port);
849 }
850
851 }
852
853 /* Assign Ram Buffer allocation to queue */
854 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
855 {
856 u32 end;
857
858 /* convert from K bytes to qwords used for hw register */
859 start *= 1024/8;
860 space *= 1024/8;
861 end = start + space - 1;
862
863 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
864 sky2_write32(hw, RB_ADDR(q, RB_START), start);
865 sky2_write32(hw, RB_ADDR(q, RB_END), end);
866 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
867 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
868
869 if (q == Q_R1 || q == Q_R2) {
870 u32 tp = space - space/4;
871
872 /* On receive queue's set the thresholds
873 * give receiver priority when > 3/4 full
874 * send pause when down to 2K
875 */
876 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
877 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
878
879 tp = space - 2048/8;
880 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
881 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
882 } else {
883 /* Enable store & forward on Tx queue's because
884 * Tx FIFO is only 1K on Yukon
885 */
886 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
887 }
888
889 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
890 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
891 }
892
893 /* Setup Bus Memory Interface */
894 static void sky2_qset(struct sky2_hw *hw, u16 q)
895 {
896 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
897 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
898 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
899 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
900 }
901
902 /* Setup prefetch unit registers. This is the interface between
903 * hardware and driver list elements
904 */
905 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
906 u64 addr, u32 last)
907 {
908 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
909 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
910 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
911 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
912 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
913 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
914
915 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
916 }
917
918 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
919 {
920 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
921
922 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
923 le->ctrl = 0;
924 return le;
925 }
926
927 static void tx_init(struct sky2_port *sky2)
928 {
929 struct sky2_tx_le *le;
930
931 sky2->tx_prod = sky2->tx_cons = 0;
932 sky2->tx_tcpsum = 0;
933 sky2->tx_last_mss = 0;
934
935 le = get_tx_le(sky2);
936 le->addr = 0;
937 le->opcode = OP_ADDR64 | HW_OWNER;
938 sky2->tx_addr64 = 0;
939 }
940
941 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
942 struct sky2_tx_le *le)
943 {
944 return sky2->tx_ring + (le - sky2->tx_le);
945 }
946
947 /* Update chip's next pointer */
948 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
949 {
950 /* Make sure write' to descriptors are complete before we tell hardware */
951 wmb();
952 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
953
954 /* Synchronize I/O on since next processor may write to tail */
955 mmiowb();
956 }
957
958
959 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
960 {
961 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
962 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
963 le->ctrl = 0;
964 return le;
965 }
966
967 /* Build description to hardware for one receive segment */
968 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
969 dma_addr_t map, unsigned len)
970 {
971 struct sky2_rx_le *le;
972 u32 hi = upper_32_bits(map);
973
974 if (sky2->rx_addr64 != hi) {
975 le = sky2_next_rx(sky2);
976 le->addr = cpu_to_le32(hi);
977 le->opcode = OP_ADDR64 | HW_OWNER;
978 sky2->rx_addr64 = upper_32_bits(map + len);
979 }
980
981 le = sky2_next_rx(sky2);
982 le->addr = cpu_to_le32((u32) map);
983 le->length = cpu_to_le16(len);
984 le->opcode = op | HW_OWNER;
985 }
986
987 /* Build description to hardware for one possibly fragmented skb */
988 static void sky2_rx_submit(struct sky2_port *sky2,
989 const struct rx_ring_info *re)
990 {
991 int i;
992
993 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
994
995 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
996 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
997 }
998
999
1000 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1001 unsigned size)
1002 {
1003 struct sk_buff *skb = re->skb;
1004 int i;
1005
1006 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1007 pci_unmap_len_set(re, data_size, size);
1008
1009 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1010 re->frag_addr[i] = pci_map_page(pdev,
1011 skb_shinfo(skb)->frags[i].page,
1012 skb_shinfo(skb)->frags[i].page_offset,
1013 skb_shinfo(skb)->frags[i].size,
1014 PCI_DMA_FROMDEVICE);
1015 }
1016
1017 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1018 {
1019 struct sk_buff *skb = re->skb;
1020 int i;
1021
1022 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1023 PCI_DMA_FROMDEVICE);
1024
1025 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1026 pci_unmap_page(pdev, re->frag_addr[i],
1027 skb_shinfo(skb)->frags[i].size,
1028 PCI_DMA_FROMDEVICE);
1029 }
1030
1031 /* Tell chip where to start receive checksum.
1032 * Actually has two checksums, but set both same to avoid possible byte
1033 * order problems.
1034 */
1035 static void rx_set_checksum(struct sky2_port *sky2)
1036 {
1037 struct sky2_rx_le *le = sky2_next_rx(sky2);
1038
1039 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1040 le->ctrl = 0;
1041 le->opcode = OP_TCPSTART | HW_OWNER;
1042
1043 sky2_write32(sky2->hw,
1044 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1045 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1046 }
1047
1048 /*
1049 * The RX Stop command will not work for Yukon-2 if the BMU does not
1050 * reach the end of packet and since we can't make sure that we have
1051 * incoming data, we must reset the BMU while it is not doing a DMA
1052 * transfer. Since it is possible that the RX path is still active,
1053 * the RX RAM buffer will be stopped first, so any possible incoming
1054 * data will not trigger a DMA. After the RAM buffer is stopped, the
1055 * BMU is polled until any DMA in progress is ended and only then it
1056 * will be reset.
1057 */
1058 static void sky2_rx_stop(struct sky2_port *sky2)
1059 {
1060 struct sky2_hw *hw = sky2->hw;
1061 unsigned rxq = rxqaddr[sky2->port];
1062 int i;
1063
1064 /* disable the RAM Buffer receive queue */
1065 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1066
1067 for (i = 0; i < 0xffff; i++)
1068 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1069 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1070 goto stopped;
1071
1072 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1073 sky2->netdev->name);
1074 stopped:
1075 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1076
1077 /* reset the Rx prefetch unit */
1078 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1079 mmiowb();
1080 }
1081
1082 /* Clean out receive buffer area, assumes receiver hardware stopped */
1083 static void sky2_rx_clean(struct sky2_port *sky2)
1084 {
1085 unsigned i;
1086
1087 memset(sky2->rx_le, 0, RX_LE_BYTES);
1088 for (i = 0; i < sky2->rx_pending; i++) {
1089 struct rx_ring_info *re = sky2->rx_ring + i;
1090
1091 if (re->skb) {
1092 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1093 kfree_skb(re->skb);
1094 re->skb = NULL;
1095 }
1096 }
1097 }
1098
1099 /* Basic MII support */
1100 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1101 {
1102 struct mii_ioctl_data *data = if_mii(ifr);
1103 struct sky2_port *sky2 = netdev_priv(dev);
1104 struct sky2_hw *hw = sky2->hw;
1105 int err = -EOPNOTSUPP;
1106
1107 if (!netif_running(dev))
1108 return -ENODEV; /* Phy still in reset */
1109
1110 switch (cmd) {
1111 case SIOCGMIIPHY:
1112 data->phy_id = PHY_ADDR_MARV;
1113
1114 /* fallthru */
1115 case SIOCGMIIREG: {
1116 u16 val = 0;
1117
1118 spin_lock_bh(&sky2->phy_lock);
1119 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1120 spin_unlock_bh(&sky2->phy_lock);
1121
1122 data->val_out = val;
1123 break;
1124 }
1125
1126 case SIOCSMIIREG:
1127 if (!capable(CAP_NET_ADMIN))
1128 return -EPERM;
1129
1130 spin_lock_bh(&sky2->phy_lock);
1131 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1132 data->val_in);
1133 spin_unlock_bh(&sky2->phy_lock);
1134 break;
1135 }
1136 return err;
1137 }
1138
1139 #ifdef SKY2_VLAN_TAG_USED
1140 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1141 {
1142 struct sky2_port *sky2 = netdev_priv(dev);
1143 struct sky2_hw *hw = sky2->hw;
1144 u16 port = sky2->port;
1145
1146 netif_tx_lock_bh(dev);
1147 napi_disable(&hw->napi);
1148
1149 sky2->vlgrp = grp;
1150 if (grp) {
1151 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1152 RX_VLAN_STRIP_ON);
1153 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1154 TX_VLAN_TAG_ON);
1155 } else {
1156 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1157 RX_VLAN_STRIP_OFF);
1158 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1159 TX_VLAN_TAG_OFF);
1160 }
1161
1162 napi_enable(&hw->napi);
1163 netif_tx_unlock_bh(dev);
1164 }
1165 #endif
1166
1167 /*
1168 * Allocate an skb for receiving. If the MTU is large enough
1169 * make the skb non-linear with a fragment list of pages.
1170 *
1171 * It appears the hardware has a bug in the FIFO logic that
1172 * cause it to hang if the FIFO gets overrun and the receive buffer
1173 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1174 * aligned except if slab debugging is enabled.
1175 */
1176 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1177 {
1178 struct sk_buff *skb;
1179 unsigned long p;
1180 int i;
1181
1182 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1183 if (!skb)
1184 goto nomem;
1185
1186 p = (unsigned long) skb->data;
1187 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1188
1189 for (i = 0; i < sky2->rx_nfrags; i++) {
1190 struct page *page = alloc_page(GFP_ATOMIC);
1191
1192 if (!page)
1193 goto free_partial;
1194 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1195 }
1196
1197 return skb;
1198 free_partial:
1199 kfree_skb(skb);
1200 nomem:
1201 return NULL;
1202 }
1203
1204 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1205 {
1206 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1207 }
1208
1209 /*
1210 * Allocate and setup receiver buffer pool.
1211 * Normal case this ends up creating one list element for skb
1212 * in the receive ring. Worst case if using large MTU and each
1213 * allocation falls on a different 64 bit region, that results
1214 * in 6 list elements per ring entry.
1215 * One element is used for checksum enable/disable, and one
1216 * extra to avoid wrap.
1217 */
1218 static int sky2_rx_start(struct sky2_port *sky2)
1219 {
1220 struct sky2_hw *hw = sky2->hw;
1221 struct rx_ring_info *re;
1222 unsigned rxq = rxqaddr[sky2->port];
1223 unsigned i, size, space, thresh;
1224
1225 sky2->rx_put = sky2->rx_next = 0;
1226 sky2_qset(hw, rxq);
1227
1228 /* On PCI express lowering the watermark gives better performance */
1229 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1230 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1231
1232 /* These chips have no ram buffer?
1233 * MAC Rx RAM Read is controlled by hardware */
1234 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1235 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1236 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1237 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1238
1239 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1240
1241 if (!(hw->flags & SKY2_HW_NEW_LE))
1242 rx_set_checksum(sky2);
1243
1244 /* Space needed for frame data + headers rounded up */
1245 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1246
1247 /* Stopping point for hardware truncation */
1248 thresh = (size - 8) / sizeof(u32);
1249
1250 /* Account for overhead of skb - to avoid order > 0 allocation */
1251 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1252 + sizeof(struct skb_shared_info);
1253
1254 sky2->rx_nfrags = space >> PAGE_SHIFT;
1255 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1256
1257 if (sky2->rx_nfrags != 0) {
1258 /* Compute residue after pages */
1259 space = sky2->rx_nfrags << PAGE_SHIFT;
1260
1261 if (space < size)
1262 size -= space;
1263 else
1264 size = 0;
1265
1266 /* Optimize to handle small packets and headers */
1267 if (size < copybreak)
1268 size = copybreak;
1269 if (size < ETH_HLEN)
1270 size = ETH_HLEN;
1271 }
1272 sky2->rx_data_size = size;
1273
1274 /* Fill Rx ring */
1275 for (i = 0; i < sky2->rx_pending; i++) {
1276 re = sky2->rx_ring + i;
1277
1278 re->skb = sky2_rx_alloc(sky2);
1279 if (!re->skb)
1280 goto nomem;
1281
1282 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1283 sky2_rx_submit(sky2, re);
1284 }
1285
1286 /*
1287 * The receiver hangs if it receives frames larger than the
1288 * packet buffer. As a workaround, truncate oversize frames, but
1289 * the register is limited to 9 bits, so if you do frames > 2052
1290 * you better get the MTU right!
1291 */
1292 if (thresh > 0x1ff)
1293 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1294 else {
1295 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1296 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1297 }
1298
1299 /* Tell chip about available buffers */
1300 sky2_rx_update(sky2, rxq);
1301 return 0;
1302 nomem:
1303 sky2_rx_clean(sky2);
1304 return -ENOMEM;
1305 }
1306
1307 /* Bring up network interface. */
1308 static int sky2_up(struct net_device *dev)
1309 {
1310 struct sky2_port *sky2 = netdev_priv(dev);
1311 struct sky2_hw *hw = sky2->hw;
1312 unsigned port = sky2->port;
1313 u32 imask, ramsize;
1314 int cap, err = -ENOMEM;
1315 struct net_device *otherdev = hw->dev[sky2->port^1];
1316
1317 /*
1318 * On dual port PCI-X card, there is an problem where status
1319 * can be received out of order due to split transactions
1320 */
1321 if (otherdev && netif_running(otherdev) &&
1322 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1323 struct sky2_port *osky2 = netdev_priv(otherdev);
1324 u16 cmd;
1325
1326 pci_read_config_word(hw->pdev, cap + PCI_X_CMD, &cmd);
1327 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1328 pci_write_config_word(hw->pdev, cap + PCI_X_CMD, cmd);
1329
1330 sky2->rx_csum = 0;
1331 osky2->rx_csum = 0;
1332 }
1333
1334 if (netif_msg_ifup(sky2))
1335 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1336
1337 netif_carrier_off(dev);
1338
1339 /* must be power of 2 */
1340 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1341 TX_RING_SIZE *
1342 sizeof(struct sky2_tx_le),
1343 &sky2->tx_le_map);
1344 if (!sky2->tx_le)
1345 goto err_out;
1346
1347 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1348 GFP_KERNEL);
1349 if (!sky2->tx_ring)
1350 goto err_out;
1351
1352 tx_init(sky2);
1353
1354 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1355 &sky2->rx_le_map);
1356 if (!sky2->rx_le)
1357 goto err_out;
1358 memset(sky2->rx_le, 0, RX_LE_BYTES);
1359
1360 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1361 GFP_KERNEL);
1362 if (!sky2->rx_ring)
1363 goto err_out;
1364
1365 sky2_phy_power(hw, port, 1);
1366
1367 sky2_mac_init(hw, port);
1368
1369 /* Register is number of 4K blocks on internal RAM buffer. */
1370 ramsize = sky2_read8(hw, B2_E_0) * 4;
1371 if (ramsize > 0) {
1372 u32 rxspace;
1373
1374 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1375 if (ramsize < 16)
1376 rxspace = ramsize / 2;
1377 else
1378 rxspace = 8 + (2*(ramsize - 16))/3;
1379
1380 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1381 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1382
1383 /* Make sure SyncQ is disabled */
1384 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1385 RB_RST_SET);
1386 }
1387
1388 sky2_qset(hw, txqaddr[port]);
1389
1390 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1391 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1392 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1393
1394 /* Set almost empty threshold */
1395 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1396 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1397 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1398
1399 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1400 TX_RING_SIZE - 1);
1401
1402 err = sky2_rx_start(sky2);
1403 if (err)
1404 goto err_out;
1405
1406 /* Enable interrupts from phy/mac for port */
1407 imask = sky2_read32(hw, B0_IMSK);
1408 imask |= portirq_msk[port];
1409 sky2_write32(hw, B0_IMSK, imask);
1410
1411 return 0;
1412
1413 err_out:
1414 if (sky2->rx_le) {
1415 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1416 sky2->rx_le, sky2->rx_le_map);
1417 sky2->rx_le = NULL;
1418 }
1419 if (sky2->tx_le) {
1420 pci_free_consistent(hw->pdev,
1421 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1422 sky2->tx_le, sky2->tx_le_map);
1423 sky2->tx_le = NULL;
1424 }
1425 kfree(sky2->tx_ring);
1426 kfree(sky2->rx_ring);
1427
1428 sky2->tx_ring = NULL;
1429 sky2->rx_ring = NULL;
1430 return err;
1431 }
1432
1433 /* Modular subtraction in ring */
1434 static inline int tx_dist(unsigned tail, unsigned head)
1435 {
1436 return (head - tail) & (TX_RING_SIZE - 1);
1437 }
1438
1439 /* Number of list elements available for next tx */
1440 static inline int tx_avail(const struct sky2_port *sky2)
1441 {
1442 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1443 }
1444
1445 /* Estimate of number of transmit list elements required */
1446 static unsigned tx_le_req(const struct sk_buff *skb)
1447 {
1448 unsigned count;
1449
1450 count = sizeof(dma_addr_t) / sizeof(u32);
1451 count += skb_shinfo(skb)->nr_frags * count;
1452
1453 if (skb_is_gso(skb))
1454 ++count;
1455
1456 if (skb->ip_summed == CHECKSUM_PARTIAL)
1457 ++count;
1458
1459 return count;
1460 }
1461
1462 /*
1463 * Put one packet in ring for transmit.
1464 * A single packet can generate multiple list elements, and
1465 * the number of ring elements will probably be less than the number
1466 * of list elements used.
1467 */
1468 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1469 {
1470 struct sky2_port *sky2 = netdev_priv(dev);
1471 struct sky2_hw *hw = sky2->hw;
1472 struct sky2_tx_le *le = NULL;
1473 struct tx_ring_info *re;
1474 unsigned i, len;
1475 dma_addr_t mapping;
1476 u32 addr64;
1477 u16 mss;
1478 u8 ctrl;
1479
1480 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1481 return NETDEV_TX_BUSY;
1482
1483 if (unlikely(netif_msg_tx_queued(sky2)))
1484 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1485 dev->name, sky2->tx_prod, skb->len);
1486
1487 len = skb_headlen(skb);
1488 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1489 addr64 = upper_32_bits(mapping);
1490
1491 /* Send high bits if changed or crosses boundary */
1492 if (addr64 != sky2->tx_addr64 ||
1493 upper_32_bits(mapping + len) != sky2->tx_addr64) {
1494 le = get_tx_le(sky2);
1495 le->addr = cpu_to_le32(addr64);
1496 le->opcode = OP_ADDR64 | HW_OWNER;
1497 sky2->tx_addr64 = upper_32_bits(mapping + len);
1498 }
1499
1500 /* Check for TCP Segmentation Offload */
1501 mss = skb_shinfo(skb)->gso_size;
1502 if (mss != 0) {
1503
1504 if (!(hw->flags & SKY2_HW_NEW_LE))
1505 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1506
1507 if (mss != sky2->tx_last_mss) {
1508 le = get_tx_le(sky2);
1509 le->addr = cpu_to_le32(mss);
1510
1511 if (hw->flags & SKY2_HW_NEW_LE)
1512 le->opcode = OP_MSS | HW_OWNER;
1513 else
1514 le->opcode = OP_LRGLEN | HW_OWNER;
1515 sky2->tx_last_mss = mss;
1516 }
1517 }
1518
1519 ctrl = 0;
1520 #ifdef SKY2_VLAN_TAG_USED
1521 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1522 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1523 if (!le) {
1524 le = get_tx_le(sky2);
1525 le->addr = 0;
1526 le->opcode = OP_VLAN|HW_OWNER;
1527 } else
1528 le->opcode |= OP_VLAN;
1529 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1530 ctrl |= INS_VLAN;
1531 }
1532 #endif
1533
1534 /* Handle TCP checksum offload */
1535 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1536 /* On Yukon EX (some versions) encoding change. */
1537 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1538 ctrl |= CALSUM; /* auto checksum */
1539 else {
1540 const unsigned offset = skb_transport_offset(skb);
1541 u32 tcpsum;
1542
1543 tcpsum = offset << 16; /* sum start */
1544 tcpsum |= offset + skb->csum_offset; /* sum write */
1545
1546 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1547 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1548 ctrl |= UDPTCP;
1549
1550 if (tcpsum != sky2->tx_tcpsum) {
1551 sky2->tx_tcpsum = tcpsum;
1552
1553 le = get_tx_le(sky2);
1554 le->addr = cpu_to_le32(tcpsum);
1555 le->length = 0; /* initial checksum value */
1556 le->ctrl = 1; /* one packet */
1557 le->opcode = OP_TCPLISW | HW_OWNER;
1558 }
1559 }
1560 }
1561
1562 le = get_tx_le(sky2);
1563 le->addr = cpu_to_le32((u32) mapping);
1564 le->length = cpu_to_le16(len);
1565 le->ctrl = ctrl;
1566 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1567
1568 re = tx_le_re(sky2, le);
1569 re->skb = skb;
1570 pci_unmap_addr_set(re, mapaddr, mapping);
1571 pci_unmap_len_set(re, maplen, len);
1572
1573 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1574 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1575
1576 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1577 frag->size, PCI_DMA_TODEVICE);
1578 addr64 = upper_32_bits(mapping);
1579 if (addr64 != sky2->tx_addr64) {
1580 le = get_tx_le(sky2);
1581 le->addr = cpu_to_le32(addr64);
1582 le->ctrl = 0;
1583 le->opcode = OP_ADDR64 | HW_OWNER;
1584 sky2->tx_addr64 = addr64;
1585 }
1586
1587 le = get_tx_le(sky2);
1588 le->addr = cpu_to_le32((u32) mapping);
1589 le->length = cpu_to_le16(frag->size);
1590 le->ctrl = ctrl;
1591 le->opcode = OP_BUFFER | HW_OWNER;
1592
1593 re = tx_le_re(sky2, le);
1594 re->skb = skb;
1595 pci_unmap_addr_set(re, mapaddr, mapping);
1596 pci_unmap_len_set(re, maplen, frag->size);
1597 }
1598
1599 le->ctrl |= EOP;
1600
1601 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1602 netif_stop_queue(dev);
1603
1604 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1605
1606 dev->trans_start = jiffies;
1607 return NETDEV_TX_OK;
1608 }
1609
1610 /*
1611 * Free ring elements from starting at tx_cons until "done"
1612 *
1613 * NB: the hardware will tell us about partial completion of multi-part
1614 * buffers so make sure not to free skb to early.
1615 */
1616 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1617 {
1618 struct net_device *dev = sky2->netdev;
1619 struct pci_dev *pdev = sky2->hw->pdev;
1620 unsigned idx;
1621
1622 BUG_ON(done >= TX_RING_SIZE);
1623
1624 for (idx = sky2->tx_cons; idx != done;
1625 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1626 struct sky2_tx_le *le = sky2->tx_le + idx;
1627 struct tx_ring_info *re = sky2->tx_ring + idx;
1628
1629 switch(le->opcode & ~HW_OWNER) {
1630 case OP_LARGESEND:
1631 case OP_PACKET:
1632 pci_unmap_single(pdev,
1633 pci_unmap_addr(re, mapaddr),
1634 pci_unmap_len(re, maplen),
1635 PCI_DMA_TODEVICE);
1636 break;
1637 case OP_BUFFER:
1638 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1639 pci_unmap_len(re, maplen),
1640 PCI_DMA_TODEVICE);
1641 break;
1642 }
1643
1644 if (le->ctrl & EOP) {
1645 if (unlikely(netif_msg_tx_done(sky2)))
1646 printk(KERN_DEBUG "%s: tx done %u\n",
1647 dev->name, idx);
1648
1649 dev->stats.tx_packets++;
1650 dev->stats.tx_bytes += re->skb->len;
1651
1652 dev_kfree_skb_any(re->skb);
1653 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1654 }
1655 }
1656
1657 sky2->tx_cons = idx;
1658 smp_mb();
1659
1660 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1661 netif_wake_queue(dev);
1662 }
1663
1664 /* Cleanup all untransmitted buffers, assume transmitter not running */
1665 static void sky2_tx_clean(struct net_device *dev)
1666 {
1667 struct sky2_port *sky2 = netdev_priv(dev);
1668
1669 netif_tx_lock_bh(dev);
1670 sky2_tx_complete(sky2, sky2->tx_prod);
1671 netif_tx_unlock_bh(dev);
1672 }
1673
1674 /* Network shutdown */
1675 static int sky2_down(struct net_device *dev)
1676 {
1677 struct sky2_port *sky2 = netdev_priv(dev);
1678 struct sky2_hw *hw = sky2->hw;
1679 unsigned port = sky2->port;
1680 u16 ctrl;
1681 u32 imask;
1682
1683 /* Never really got started! */
1684 if (!sky2->tx_le)
1685 return 0;
1686
1687 if (netif_msg_ifdown(sky2))
1688 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1689
1690 /* Stop more packets from being queued */
1691 netif_stop_queue(dev);
1692
1693 /* Disable port IRQ */
1694 imask = sky2_read32(hw, B0_IMSK);
1695 imask &= ~portirq_msk[port];
1696 sky2_write32(hw, B0_IMSK, imask);
1697
1698 synchronize_irq(hw->pdev->irq);
1699
1700 sky2_gmac_reset(hw, port);
1701
1702 /* Stop transmitter */
1703 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1704 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1705
1706 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1707 RB_RST_SET | RB_DIS_OP_MD);
1708
1709 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1710 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1711 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1712
1713 /* Make sure no packets are pending */
1714 napi_synchronize(&hw->napi);
1715
1716 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1717
1718 /* Workaround shared GMAC reset */
1719 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1720 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1721 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1722
1723 /* Disable Force Sync bit and Enable Alloc bit */
1724 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1725 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1726
1727 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1728 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1729 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1730
1731 /* Reset the PCI FIFO of the async Tx queue */
1732 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1733 BMU_RST_SET | BMU_FIFO_RST);
1734
1735 /* Reset the Tx prefetch units */
1736 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1737 PREF_UNIT_RST_SET);
1738
1739 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1740
1741 sky2_rx_stop(sky2);
1742
1743 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1744 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1745
1746 sky2_phy_power(hw, port, 0);
1747
1748 netif_carrier_off(dev);
1749
1750 /* turn off LED's */
1751 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1752
1753 sky2_tx_clean(dev);
1754 sky2_rx_clean(sky2);
1755
1756 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1757 sky2->rx_le, sky2->rx_le_map);
1758 kfree(sky2->rx_ring);
1759
1760 pci_free_consistent(hw->pdev,
1761 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1762 sky2->tx_le, sky2->tx_le_map);
1763 kfree(sky2->tx_ring);
1764
1765 sky2->tx_le = NULL;
1766 sky2->rx_le = NULL;
1767
1768 sky2->rx_ring = NULL;
1769 sky2->tx_ring = NULL;
1770
1771 return 0;
1772 }
1773
1774 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1775 {
1776 if (hw->flags & SKY2_HW_FIBRE_PHY)
1777 return SPEED_1000;
1778
1779 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1780 if (aux & PHY_M_PS_SPEED_100)
1781 return SPEED_100;
1782 else
1783 return SPEED_10;
1784 }
1785
1786 switch (aux & PHY_M_PS_SPEED_MSK) {
1787 case PHY_M_PS_SPEED_1000:
1788 return SPEED_1000;
1789 case PHY_M_PS_SPEED_100:
1790 return SPEED_100;
1791 default:
1792 return SPEED_10;
1793 }
1794 }
1795
1796 static void sky2_link_up(struct sky2_port *sky2)
1797 {
1798 struct sky2_hw *hw = sky2->hw;
1799 unsigned port = sky2->port;
1800 u16 reg;
1801 static const char *fc_name[] = {
1802 [FC_NONE] = "none",
1803 [FC_TX] = "tx",
1804 [FC_RX] = "rx",
1805 [FC_BOTH] = "both",
1806 };
1807
1808 /* enable Rx/Tx */
1809 reg = gma_read16(hw, port, GM_GP_CTRL);
1810 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1811 gma_write16(hw, port, GM_GP_CTRL, reg);
1812
1813 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1814
1815 netif_carrier_on(sky2->netdev);
1816
1817 mod_timer(&hw->watchdog_timer, jiffies + 1);
1818
1819 /* Turn on link LED */
1820 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1821 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1822
1823 if (netif_msg_link(sky2))
1824 printk(KERN_INFO PFX
1825 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1826 sky2->netdev->name, sky2->speed,
1827 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1828 fc_name[sky2->flow_status]);
1829 }
1830
1831 static void sky2_link_down(struct sky2_port *sky2)
1832 {
1833 struct sky2_hw *hw = sky2->hw;
1834 unsigned port = sky2->port;
1835 u16 reg;
1836
1837 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1838
1839 reg = gma_read16(hw, port, GM_GP_CTRL);
1840 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1841 gma_write16(hw, port, GM_GP_CTRL, reg);
1842
1843 netif_carrier_off(sky2->netdev);
1844
1845 /* Turn on link LED */
1846 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1847
1848 if (netif_msg_link(sky2))
1849 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1850
1851 sky2_phy_init(hw, port);
1852 }
1853
1854 static enum flow_control sky2_flow(int rx, int tx)
1855 {
1856 if (rx)
1857 return tx ? FC_BOTH : FC_RX;
1858 else
1859 return tx ? FC_TX : FC_NONE;
1860 }
1861
1862 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1863 {
1864 struct sky2_hw *hw = sky2->hw;
1865 unsigned port = sky2->port;
1866 u16 advert, lpa;
1867
1868 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1869 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1870 if (lpa & PHY_M_AN_RF) {
1871 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1872 return -1;
1873 }
1874
1875 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1876 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1877 sky2->netdev->name);
1878 return -1;
1879 }
1880
1881 sky2->speed = sky2_phy_speed(hw, aux);
1882 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1883
1884 /* Since the pause result bits seem to in different positions on
1885 * different chips. look at registers.
1886 */
1887 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1888 /* Shift for bits in fiber PHY */
1889 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1890 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1891
1892 if (advert & ADVERTISE_1000XPAUSE)
1893 advert |= ADVERTISE_PAUSE_CAP;
1894 if (advert & ADVERTISE_1000XPSE_ASYM)
1895 advert |= ADVERTISE_PAUSE_ASYM;
1896 if (lpa & LPA_1000XPAUSE)
1897 lpa |= LPA_PAUSE_CAP;
1898 if (lpa & LPA_1000XPAUSE_ASYM)
1899 lpa |= LPA_PAUSE_ASYM;
1900 }
1901
1902 sky2->flow_status = FC_NONE;
1903 if (advert & ADVERTISE_PAUSE_CAP) {
1904 if (lpa & LPA_PAUSE_CAP)
1905 sky2->flow_status = FC_BOTH;
1906 else if (advert & ADVERTISE_PAUSE_ASYM)
1907 sky2->flow_status = FC_RX;
1908 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1909 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1910 sky2->flow_status = FC_TX;
1911 }
1912
1913 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1914 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1915 sky2->flow_status = FC_NONE;
1916
1917 if (sky2->flow_status & FC_TX)
1918 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1919 else
1920 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1921
1922 return 0;
1923 }
1924
1925 /* Interrupt from PHY */
1926 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1927 {
1928 struct net_device *dev = hw->dev[port];
1929 struct sky2_port *sky2 = netdev_priv(dev);
1930 u16 istatus, phystat;
1931
1932 if (!netif_running(dev))
1933 return;
1934
1935 spin_lock(&sky2->phy_lock);
1936 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1937 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1938
1939 if (netif_msg_intr(sky2))
1940 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1941 sky2->netdev->name, istatus, phystat);
1942
1943 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1944 if (sky2_autoneg_done(sky2, phystat) == 0)
1945 sky2_link_up(sky2);
1946 goto out;
1947 }
1948
1949 if (istatus & PHY_M_IS_LSP_CHANGE)
1950 sky2->speed = sky2_phy_speed(hw, phystat);
1951
1952 if (istatus & PHY_M_IS_DUP_CHANGE)
1953 sky2->duplex =
1954 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1955
1956 if (istatus & PHY_M_IS_LST_CHANGE) {
1957 if (phystat & PHY_M_PS_LINK_UP)
1958 sky2_link_up(sky2);
1959 else
1960 sky2_link_down(sky2);
1961 }
1962 out:
1963 spin_unlock(&sky2->phy_lock);
1964 }
1965
1966 /* Transmit timeout is only called if we are running, carrier is up
1967 * and tx queue is full (stopped).
1968 */
1969 static void sky2_tx_timeout(struct net_device *dev)
1970 {
1971 struct sky2_port *sky2 = netdev_priv(dev);
1972 struct sky2_hw *hw = sky2->hw;
1973
1974 if (netif_msg_timer(sky2))
1975 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1976
1977 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1978 dev->name, sky2->tx_cons, sky2->tx_prod,
1979 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1980 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1981
1982 /* can't restart safely under softirq */
1983 schedule_work(&hw->restart_work);
1984 }
1985
1986 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1987 {
1988 struct sky2_port *sky2 = netdev_priv(dev);
1989 struct sky2_hw *hw = sky2->hw;
1990 unsigned port = sky2->port;
1991 int err;
1992 u16 ctl, mode;
1993 u32 imask;
1994
1995 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1996 return -EINVAL;
1997
1998 if (new_mtu > ETH_DATA_LEN &&
1999 (hw->chip_id == CHIP_ID_YUKON_FE ||
2000 hw->chip_id == CHIP_ID_YUKON_FE_P))
2001 return -EINVAL;
2002
2003 if (!netif_running(dev)) {
2004 dev->mtu = new_mtu;
2005 return 0;
2006 }
2007
2008 imask = sky2_read32(hw, B0_IMSK);
2009 sky2_write32(hw, B0_IMSK, 0);
2010
2011 dev->trans_start = jiffies; /* prevent tx timeout */
2012 netif_stop_queue(dev);
2013 napi_disable(&hw->napi);
2014
2015 synchronize_irq(hw->pdev->irq);
2016
2017 if (sky2_read8(hw, B2_E_0) == 0)
2018 sky2_set_tx_stfwd(hw, port);
2019
2020 ctl = gma_read16(hw, port, GM_GP_CTRL);
2021 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2022 sky2_rx_stop(sky2);
2023 sky2_rx_clean(sky2);
2024
2025 dev->mtu = new_mtu;
2026
2027 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2028 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2029
2030 if (dev->mtu > ETH_DATA_LEN)
2031 mode |= GM_SMOD_JUMBO_ENA;
2032
2033 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2034
2035 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2036
2037 err = sky2_rx_start(sky2);
2038 sky2_write32(hw, B0_IMSK, imask);
2039
2040 napi_enable(&hw->napi);
2041
2042 if (err)
2043 dev_close(dev);
2044 else {
2045 gma_write16(hw, port, GM_GP_CTRL, ctl);
2046
2047 netif_wake_queue(dev);
2048 }
2049
2050 return err;
2051 }
2052
2053 /* For small just reuse existing skb for next receive */
2054 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2055 const struct rx_ring_info *re,
2056 unsigned length)
2057 {
2058 struct sk_buff *skb;
2059
2060 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2061 if (likely(skb)) {
2062 skb_reserve(skb, 2);
2063 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2064 length, PCI_DMA_FROMDEVICE);
2065 skb_copy_from_linear_data(re->skb, skb->data, length);
2066 skb->ip_summed = re->skb->ip_summed;
2067 skb->csum = re->skb->csum;
2068 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2069 length, PCI_DMA_FROMDEVICE);
2070 re->skb->ip_summed = CHECKSUM_NONE;
2071 skb_put(skb, length);
2072 }
2073 return skb;
2074 }
2075
2076 /* Adjust length of skb with fragments to match received data */
2077 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2078 unsigned int length)
2079 {
2080 int i, num_frags;
2081 unsigned int size;
2082
2083 /* put header into skb */
2084 size = min(length, hdr_space);
2085 skb->tail += size;
2086 skb->len += size;
2087 length -= size;
2088
2089 num_frags = skb_shinfo(skb)->nr_frags;
2090 for (i = 0; i < num_frags; i++) {
2091 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2092
2093 if (length == 0) {
2094 /* don't need this page */
2095 __free_page(frag->page);
2096 --skb_shinfo(skb)->nr_frags;
2097 } else {
2098 size = min(length, (unsigned) PAGE_SIZE);
2099
2100 frag->size = size;
2101 skb->data_len += size;
2102 skb->truesize += size;
2103 skb->len += size;
2104 length -= size;
2105 }
2106 }
2107 }
2108
2109 /* Normal packet - take skb from ring element and put in a new one */
2110 static struct sk_buff *receive_new(struct sky2_port *sky2,
2111 struct rx_ring_info *re,
2112 unsigned int length)
2113 {
2114 struct sk_buff *skb, *nskb;
2115 unsigned hdr_space = sky2->rx_data_size;
2116
2117 /* Don't be tricky about reusing pages (yet) */
2118 nskb = sky2_rx_alloc(sky2);
2119 if (unlikely(!nskb))
2120 return NULL;
2121
2122 skb = re->skb;
2123 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2124
2125 prefetch(skb->data);
2126 re->skb = nskb;
2127 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2128
2129 if (skb_shinfo(skb)->nr_frags)
2130 skb_put_frags(skb, hdr_space, length);
2131 else
2132 skb_put(skb, length);
2133 return skb;
2134 }
2135
2136 /*
2137 * Receive one packet.
2138 * For larger packets, get new buffer.
2139 */
2140 static struct sk_buff *sky2_receive(struct net_device *dev,
2141 u16 length, u32 status)
2142 {
2143 struct sky2_port *sky2 = netdev_priv(dev);
2144 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2145 struct sk_buff *skb = NULL;
2146 u16 count = (status & GMR_FS_LEN) >> 16;
2147
2148 #ifdef SKY2_VLAN_TAG_USED
2149 /* Account for vlan tag */
2150 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2151 count -= VLAN_HLEN;
2152 #endif
2153
2154 if (unlikely(netif_msg_rx_status(sky2)))
2155 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2156 dev->name, sky2->rx_next, status, length);
2157
2158 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2159 prefetch(sky2->rx_ring + sky2->rx_next);
2160
2161 /* This chip has hardware problems that generates bogus status.
2162 * So do only marginal checking and expect higher level protocols
2163 * to handle crap frames.
2164 */
2165 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2166 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2167 length != count)
2168 goto okay;
2169
2170 if (status & GMR_FS_ANY_ERR)
2171 goto error;
2172
2173 if (!(status & GMR_FS_RX_OK))
2174 goto resubmit;
2175
2176 /* if length reported by DMA does not match PHY, packet was truncated */
2177 if (length != count)
2178 goto len_error;
2179
2180 okay:
2181 if (length < copybreak)
2182 skb = receive_copy(sky2, re, length);
2183 else
2184 skb = receive_new(sky2, re, length);
2185 resubmit:
2186 sky2_rx_submit(sky2, re);
2187
2188 return skb;
2189
2190 len_error:
2191 /* Truncation of overlength packets
2192 causes PHY length to not match MAC length */
2193 ++dev->stats.rx_length_errors;
2194 if (netif_msg_rx_err(sky2) && net_ratelimit())
2195 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2196 dev->name, status, length);
2197 goto resubmit;
2198
2199 error:
2200 ++dev->stats.rx_errors;
2201 if (status & GMR_FS_RX_FF_OV) {
2202 dev->stats.rx_over_errors++;
2203 goto resubmit;
2204 }
2205
2206 if (netif_msg_rx_err(sky2) && net_ratelimit())
2207 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2208 dev->name, status, length);
2209
2210 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2211 dev->stats.rx_length_errors++;
2212 if (status & GMR_FS_FRAGMENT)
2213 dev->stats.rx_frame_errors++;
2214 if (status & GMR_FS_CRC_ERR)
2215 dev->stats.rx_crc_errors++;
2216
2217 goto resubmit;
2218 }
2219
2220 /* Transmit complete */
2221 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2222 {
2223 struct sky2_port *sky2 = netdev_priv(dev);
2224
2225 if (netif_running(dev)) {
2226 netif_tx_lock(dev);
2227 sky2_tx_complete(sky2, last);
2228 netif_tx_unlock(dev);
2229 }
2230 }
2231
2232 /* Process status response ring */
2233 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2234 {
2235 int work_done = 0;
2236 unsigned rx[2] = { 0, 0 };
2237
2238 rmb();
2239 do {
2240 struct sky2_port *sky2;
2241 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2242 unsigned port;
2243 struct net_device *dev;
2244 struct sk_buff *skb;
2245 u32 status;
2246 u16 length;
2247 u8 opcode = le->opcode;
2248
2249 if (!(opcode & HW_OWNER))
2250 break;
2251
2252 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2253
2254 port = le->css & CSS_LINK_BIT;
2255 dev = hw->dev[port];
2256 sky2 = netdev_priv(dev);
2257 length = le16_to_cpu(le->length);
2258 status = le32_to_cpu(le->status);
2259
2260 le->opcode = 0;
2261 switch (opcode & ~HW_OWNER) {
2262 case OP_RXSTAT:
2263 ++rx[port];
2264 skb = sky2_receive(dev, length, status);
2265 if (unlikely(!skb)) {
2266 dev->stats.rx_dropped++;
2267 break;
2268 }
2269
2270 /* This chip reports checksum status differently */
2271 if (hw->flags & SKY2_HW_NEW_LE) {
2272 if (sky2->rx_csum &&
2273 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2274 (le->css & CSS_TCPUDPCSOK))
2275 skb->ip_summed = CHECKSUM_UNNECESSARY;
2276 else
2277 skb->ip_summed = CHECKSUM_NONE;
2278 }
2279
2280 skb->protocol = eth_type_trans(skb, dev);
2281 dev->stats.rx_packets++;
2282 dev->stats.rx_bytes += skb->len;
2283 dev->last_rx = jiffies;
2284
2285 #ifdef SKY2_VLAN_TAG_USED
2286 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2287 vlan_hwaccel_receive_skb(skb,
2288 sky2->vlgrp,
2289 be16_to_cpu(sky2->rx_tag));
2290 } else
2291 #endif
2292 netif_receive_skb(skb);
2293
2294 /* Stop after net poll weight */
2295 if (++work_done >= to_do)
2296 goto exit_loop;
2297 break;
2298
2299 #ifdef SKY2_VLAN_TAG_USED
2300 case OP_RXVLAN:
2301 sky2->rx_tag = length;
2302 break;
2303
2304 case OP_RXCHKSVLAN:
2305 sky2->rx_tag = length;
2306 /* fall through */
2307 #endif
2308 case OP_RXCHKS:
2309 if (!sky2->rx_csum)
2310 break;
2311
2312 /* If this happens then driver assuming wrong format */
2313 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2314 if (net_ratelimit())
2315 printk(KERN_NOTICE "%s: unexpected"
2316 " checksum status\n",
2317 dev->name);
2318 break;
2319 }
2320
2321 /* Both checksum counters are programmed to start at
2322 * the same offset, so unless there is a problem they
2323 * should match. This failure is an early indication that
2324 * hardware receive checksumming won't work.
2325 */
2326 if (likely(status >> 16 == (status & 0xffff))) {
2327 skb = sky2->rx_ring[sky2->rx_next].skb;
2328 skb->ip_summed = CHECKSUM_COMPLETE;
2329 skb->csum = status & 0xffff;
2330 } else {
2331 printk(KERN_NOTICE PFX "%s: hardware receive "
2332 "checksum problem (status = %#x)\n",
2333 dev->name, status);
2334 sky2->rx_csum = 0;
2335 sky2_write32(sky2->hw,
2336 Q_ADDR(rxqaddr[port], Q_CSR),
2337 BMU_DIS_RX_CHKSUM);
2338 }
2339 break;
2340
2341 case OP_TXINDEXLE:
2342 /* TX index reports status for both ports */
2343 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2344 sky2_tx_done(hw->dev[0], status & 0xfff);
2345 if (hw->dev[1])
2346 sky2_tx_done(hw->dev[1],
2347 ((status >> 24) & 0xff)
2348 | (u16)(length & 0xf) << 8);
2349 break;
2350
2351 default:
2352 if (net_ratelimit())
2353 printk(KERN_WARNING PFX
2354 "unknown status opcode 0x%x\n", opcode);
2355 }
2356 } while (hw->st_idx != idx);
2357
2358 /* Fully processed status ring so clear irq */
2359 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2360
2361 exit_loop:
2362 if (rx[0])
2363 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2364
2365 if (rx[1])
2366 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2367
2368 return work_done;
2369 }
2370
2371 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2372 {
2373 struct net_device *dev = hw->dev[port];
2374
2375 if (net_ratelimit())
2376 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2377 dev->name, status);
2378
2379 if (status & Y2_IS_PAR_RD1) {
2380 if (net_ratelimit())
2381 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2382 dev->name);
2383 /* Clear IRQ */
2384 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2385 }
2386
2387 if (status & Y2_IS_PAR_WR1) {
2388 if (net_ratelimit())
2389 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2390 dev->name);
2391
2392 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2393 }
2394
2395 if (status & Y2_IS_PAR_MAC1) {
2396 if (net_ratelimit())
2397 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2398 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2399 }
2400
2401 if (status & Y2_IS_PAR_RX1) {
2402 if (net_ratelimit())
2403 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2404 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2405 }
2406
2407 if (status & Y2_IS_TCP_TXA1) {
2408 if (net_ratelimit())
2409 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2410 dev->name);
2411 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2412 }
2413 }
2414
2415 static void sky2_hw_intr(struct sky2_hw *hw)
2416 {
2417 struct pci_dev *pdev = hw->pdev;
2418 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2419 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2420
2421 status &= hwmsk;
2422
2423 if (status & Y2_IS_TIST_OV)
2424 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2425
2426 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2427 u16 pci_err;
2428
2429 pci_read_config_word(pdev, PCI_STATUS, &pci_err);
2430 if (net_ratelimit())
2431 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2432 pci_err);
2433
2434 pci_write_config_word(pdev, PCI_STATUS,
2435 pci_err | PCI_STATUS_ERROR_BITS);
2436 }
2437
2438 if (status & Y2_IS_PCI_EXP) {
2439 /* PCI-Express uncorrectable Error occurred */
2440 int pos = pci_find_aer_capability(hw->pdev);
2441 u32 err;
2442
2443 pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_STATUS, &err);
2444 if (net_ratelimit())
2445 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2446 pci_cleanup_aer_uncorrect_error_status(pdev);
2447 }
2448
2449 if (status & Y2_HWE_L1_MASK)
2450 sky2_hw_error(hw, 0, status);
2451 status >>= 8;
2452 if (status & Y2_HWE_L1_MASK)
2453 sky2_hw_error(hw, 1, status);
2454 }
2455
2456 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2457 {
2458 struct net_device *dev = hw->dev[port];
2459 struct sky2_port *sky2 = netdev_priv(dev);
2460 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2461
2462 if (netif_msg_intr(sky2))
2463 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2464 dev->name, status);
2465
2466 if (status & GM_IS_RX_CO_OV)
2467 gma_read16(hw, port, GM_RX_IRQ_SRC);
2468
2469 if (status & GM_IS_TX_CO_OV)
2470 gma_read16(hw, port, GM_TX_IRQ_SRC);
2471
2472 if (status & GM_IS_RX_FF_OR) {
2473 ++dev->stats.rx_fifo_errors;
2474 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2475 }
2476
2477 if (status & GM_IS_TX_FF_UR) {
2478 ++dev->stats.tx_fifo_errors;
2479 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2480 }
2481 }
2482
2483 /* This should never happen it is a bug. */
2484 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2485 u16 q, unsigned ring_size)
2486 {
2487 struct net_device *dev = hw->dev[port];
2488 struct sky2_port *sky2 = netdev_priv(dev);
2489 unsigned idx;
2490 const u64 *le = (q == Q_R1 || q == Q_R2)
2491 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2492
2493 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2494 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2495 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2496 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2497
2498 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2499 }
2500
2501 static int sky2_rx_hung(struct net_device *dev)
2502 {
2503 struct sky2_port *sky2 = netdev_priv(dev);
2504 struct sky2_hw *hw = sky2->hw;
2505 unsigned port = sky2->port;
2506 unsigned rxq = rxqaddr[port];
2507 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2508 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2509 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2510 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2511
2512 /* If idle and MAC or PCI is stuck */
2513 if (sky2->check.last == dev->last_rx &&
2514 ((mac_rp == sky2->check.mac_rp &&
2515 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2516 /* Check if the PCI RX hang */
2517 (fifo_rp == sky2->check.fifo_rp &&
2518 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2519 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2520 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2521 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2522 return 1;
2523 } else {
2524 sky2->check.last = dev->last_rx;
2525 sky2->check.mac_rp = mac_rp;
2526 sky2->check.mac_lev = mac_lev;
2527 sky2->check.fifo_rp = fifo_rp;
2528 sky2->check.fifo_lev = fifo_lev;
2529 return 0;
2530 }
2531 }
2532
2533 static void sky2_watchdog(unsigned long arg)
2534 {
2535 struct sky2_hw *hw = (struct sky2_hw *) arg;
2536
2537 /* Check for lost IRQ once a second */
2538 if (sky2_read32(hw, B0_ISRC)) {
2539 napi_schedule(&hw->napi);
2540 } else {
2541 int i, active = 0;
2542
2543 for (i = 0; i < hw->ports; i++) {
2544 struct net_device *dev = hw->dev[i];
2545 if (!netif_running(dev))
2546 continue;
2547 ++active;
2548
2549 /* For chips with Rx FIFO, check if stuck */
2550 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
2551 sky2_rx_hung(dev)) {
2552 pr_info(PFX "%s: receiver hang detected\n",
2553 dev->name);
2554 schedule_work(&hw->restart_work);
2555 return;
2556 }
2557 }
2558
2559 if (active == 0)
2560 return;
2561 }
2562
2563 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2564 }
2565
2566 /* Hardware/software error handling */
2567 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2568 {
2569 if (net_ratelimit())
2570 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2571
2572 if (status & Y2_IS_HW_ERR)
2573 sky2_hw_intr(hw);
2574
2575 if (status & Y2_IS_IRQ_MAC1)
2576 sky2_mac_intr(hw, 0);
2577
2578 if (status & Y2_IS_IRQ_MAC2)
2579 sky2_mac_intr(hw, 1);
2580
2581 if (status & Y2_IS_CHK_RX1)
2582 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2583
2584 if (status & Y2_IS_CHK_RX2)
2585 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2586
2587 if (status & Y2_IS_CHK_TXA1)
2588 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2589
2590 if (status & Y2_IS_CHK_TXA2)
2591 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2592 }
2593
2594 static int sky2_poll(struct napi_struct *napi, int work_limit)
2595 {
2596 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2597 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2598 int work_done = 0;
2599 u16 idx;
2600
2601 if (unlikely(status & Y2_IS_ERROR))
2602 sky2_err_intr(hw, status);
2603
2604 if (status & Y2_IS_IRQ_PHY1)
2605 sky2_phy_intr(hw, 0);
2606
2607 if (status & Y2_IS_IRQ_PHY2)
2608 sky2_phy_intr(hw, 1);
2609
2610 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2611 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2612
2613 if (work_done >= work_limit)
2614 goto done;
2615 }
2616
2617 /* Bug/Errata workaround?
2618 * Need to kick the TX irq moderation timer.
2619 */
2620 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2621 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2622 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2623 }
2624 napi_complete(napi);
2625 sky2_read32(hw, B0_Y2_SP_LISR);
2626 done:
2627
2628 return work_done;
2629 }
2630
2631 static irqreturn_t sky2_intr(int irq, void *dev_id)
2632 {
2633 struct sky2_hw *hw = dev_id;
2634 u32 status;
2635
2636 /* Reading this mask interrupts as side effect */
2637 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2638 if (status == 0 || status == ~0)
2639 return IRQ_NONE;
2640
2641 prefetch(&hw->st_le[hw->st_idx]);
2642
2643 napi_schedule(&hw->napi);
2644
2645 return IRQ_HANDLED;
2646 }
2647
2648 #ifdef CONFIG_NET_POLL_CONTROLLER
2649 static void sky2_netpoll(struct net_device *dev)
2650 {
2651 struct sky2_port *sky2 = netdev_priv(dev);
2652
2653 napi_schedule(&sky2->hw->napi);
2654 }
2655 #endif
2656
2657 /* Chip internal frequency for clock calculations */
2658 static u32 sky2_mhz(const struct sky2_hw *hw)
2659 {
2660 switch (hw->chip_id) {
2661 case CHIP_ID_YUKON_EC:
2662 case CHIP_ID_YUKON_EC_U:
2663 case CHIP_ID_YUKON_EX:
2664 return 125;
2665
2666 case CHIP_ID_YUKON_FE:
2667 return 100;
2668
2669 case CHIP_ID_YUKON_FE_P:
2670 return 50;
2671
2672 case CHIP_ID_YUKON_XL:
2673 return 156;
2674
2675 default:
2676 BUG();
2677 }
2678 }
2679
2680 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2681 {
2682 return sky2_mhz(hw) * us;
2683 }
2684
2685 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2686 {
2687 return clk / sky2_mhz(hw);
2688 }
2689
2690
2691 static int __devinit sky2_init(struct sky2_hw *hw)
2692 {
2693 int rc;
2694 u8 t8;
2695
2696 /* Enable all clocks and check for bad PCI access */
2697 rc = pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0);
2698 if (rc)
2699 return rc;
2700
2701 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2702
2703 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2704 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2705
2706 switch(hw->chip_id) {
2707 case CHIP_ID_YUKON_XL:
2708 hw->flags = SKY2_HW_GIGABIT
2709 | SKY2_HW_NEWER_PHY;
2710 if (hw->chip_rev < 3)
2711 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2712
2713 break;
2714
2715 case CHIP_ID_YUKON_EC_U:
2716 hw->flags = SKY2_HW_GIGABIT
2717 | SKY2_HW_NEWER_PHY
2718 | SKY2_HW_ADV_POWER_CTL;
2719 break;
2720
2721 case CHIP_ID_YUKON_EX:
2722 hw->flags = SKY2_HW_GIGABIT
2723 | SKY2_HW_NEWER_PHY
2724 | SKY2_HW_NEW_LE
2725 | SKY2_HW_ADV_POWER_CTL;
2726
2727 /* New transmit checksum */
2728 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2729 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2730 break;
2731
2732 case CHIP_ID_YUKON_EC:
2733 /* This rev is really old, and requires untested workarounds */
2734 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2735 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2736 return -EOPNOTSUPP;
2737 }
2738 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
2739 break;
2740
2741 case CHIP_ID_YUKON_FE:
2742 break;
2743
2744 case CHIP_ID_YUKON_FE_P:
2745 hw->flags = SKY2_HW_NEWER_PHY
2746 | SKY2_HW_NEW_LE
2747 | SKY2_HW_AUTO_TX_SUM
2748 | SKY2_HW_ADV_POWER_CTL;
2749 break;
2750 default:
2751 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2752 hw->chip_id);
2753 return -EOPNOTSUPP;
2754 }
2755
2756 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2757 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2758 hw->flags |= SKY2_HW_FIBRE_PHY;
2759
2760
2761 hw->ports = 1;
2762 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2763 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2764 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2765 ++hw->ports;
2766 }
2767
2768 return 0;
2769 }
2770
2771 static void sky2_reset(struct sky2_hw *hw)
2772 {
2773 struct pci_dev *pdev = hw->pdev;
2774 u16 status;
2775 int i, cap;
2776 u32 hwe_mask = Y2_HWE_ALL_MASK;
2777
2778 /* disable ASF */
2779 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2780 status = sky2_read16(hw, HCU_CCSR);
2781 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2782 HCU_CCSR_UC_STATE_MSK);
2783 sky2_write16(hw, HCU_CCSR, status);
2784 } else
2785 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2786 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2787
2788 /* do a SW reset */
2789 sky2_write8(hw, B0_CTST, CS_RST_SET);
2790 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2791
2792 /* allow writes to PCI config */
2793 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2794
2795 /* clear PCI errors, if any */
2796 pci_read_config_word(pdev, PCI_STATUS, &status);
2797 status |= PCI_STATUS_ERROR_BITS;
2798 pci_write_config_word(pdev, PCI_STATUS, status);
2799
2800 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2801
2802 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2803 if (cap) {
2804 /* Check for advanced error reporting */
2805 pci_cleanup_aer_uncorrect_error_status(pdev);
2806 pci_cleanup_aer_correct_error_status(pdev);
2807
2808 /* If error bit is stuck on ignore it */
2809 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2810 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2811
2812 else if (pci_enable_pcie_error_reporting(pdev))
2813 hwe_mask |= Y2_IS_PCI_EXP;
2814 }
2815
2816 sky2_power_on(hw);
2817
2818 for (i = 0; i < hw->ports; i++) {
2819 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2820 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2821
2822 if (hw->chip_id == CHIP_ID_YUKON_EX)
2823 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2824 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2825 | GMC_BYP_RETR_ON);
2826 }
2827
2828 /* Clear I2C IRQ noise */
2829 sky2_write32(hw, B2_I2C_IRQ, 1);
2830
2831 /* turn off hardware timer (unused) */
2832 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2833 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2834
2835 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2836
2837 /* Turn off descriptor polling */
2838 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2839
2840 /* Turn off receive timestamp */
2841 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2842 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2843
2844 /* enable the Tx Arbiters */
2845 for (i = 0; i < hw->ports; i++)
2846 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2847
2848 /* Initialize ram interface */
2849 for (i = 0; i < hw->ports; i++) {
2850 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2851
2852 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2853 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2854 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2855 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2856 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2857 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2858 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2859 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2860 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2861 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2862 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2863 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2864 }
2865
2866 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2867
2868 for (i = 0; i < hw->ports; i++)
2869 sky2_gmac_reset(hw, i);
2870
2871 memset(hw->st_le, 0, STATUS_LE_BYTES);
2872 hw->st_idx = 0;
2873
2874 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2875 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2876
2877 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2878 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2879
2880 /* Set the list last index */
2881 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2882
2883 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2884 sky2_write8(hw, STAT_FIFO_WM, 16);
2885
2886 /* set Status-FIFO ISR watermark */
2887 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2888 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2889 else
2890 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2891
2892 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2893 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2894 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2895
2896 /* enable status unit */
2897 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2898
2899 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2900 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2901 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2902 }
2903
2904 static void sky2_restart(struct work_struct *work)
2905 {
2906 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2907 struct net_device *dev;
2908 int i, err;
2909
2910 rtnl_lock();
2911 sky2_write32(hw, B0_IMSK, 0);
2912 sky2_read32(hw, B0_IMSK);
2913 napi_disable(&hw->napi);
2914
2915 for (i = 0; i < hw->ports; i++) {
2916 dev = hw->dev[i];
2917 if (netif_running(dev))
2918 sky2_down(dev);
2919 }
2920
2921 sky2_reset(hw);
2922 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2923 napi_enable(&hw->napi);
2924
2925 for (i = 0; i < hw->ports; i++) {
2926 dev = hw->dev[i];
2927 if (netif_running(dev)) {
2928 err = sky2_up(dev);
2929 if (err) {
2930 printk(KERN_INFO PFX "%s: could not restart %d\n",
2931 dev->name, err);
2932 dev_close(dev);
2933 }
2934 }
2935 }
2936
2937 rtnl_unlock();
2938 }
2939
2940 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2941 {
2942 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2943 }
2944
2945 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2946 {
2947 const struct sky2_port *sky2 = netdev_priv(dev);
2948
2949 wol->supported = sky2_wol_supported(sky2->hw);
2950 wol->wolopts = sky2->wol;
2951 }
2952
2953 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2954 {
2955 struct sky2_port *sky2 = netdev_priv(dev);
2956 struct sky2_hw *hw = sky2->hw;
2957
2958 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2959 return -EOPNOTSUPP;
2960
2961 sky2->wol = wol->wolopts;
2962
2963 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2964 hw->chip_id == CHIP_ID_YUKON_EX ||
2965 hw->chip_id == CHIP_ID_YUKON_FE_P)
2966 sky2_write32(hw, B0_CTST, sky2->wol
2967 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2968
2969 if (!netif_running(dev))
2970 sky2_wol_init(sky2);
2971 return 0;
2972 }
2973
2974 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2975 {
2976 if (sky2_is_copper(hw)) {
2977 u32 modes = SUPPORTED_10baseT_Half
2978 | SUPPORTED_10baseT_Full
2979 | SUPPORTED_100baseT_Half
2980 | SUPPORTED_100baseT_Full
2981 | SUPPORTED_Autoneg | SUPPORTED_TP;
2982
2983 if (hw->flags & SKY2_HW_GIGABIT)
2984 modes |= SUPPORTED_1000baseT_Half
2985 | SUPPORTED_1000baseT_Full;
2986 return modes;
2987 } else
2988 return SUPPORTED_1000baseT_Half
2989 | SUPPORTED_1000baseT_Full
2990 | SUPPORTED_Autoneg
2991 | SUPPORTED_FIBRE;
2992 }
2993
2994 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2995 {
2996 struct sky2_port *sky2 = netdev_priv(dev);
2997 struct sky2_hw *hw = sky2->hw;
2998
2999 ecmd->transceiver = XCVR_INTERNAL;
3000 ecmd->supported = sky2_supported_modes(hw);
3001 ecmd->phy_address = PHY_ADDR_MARV;
3002 if (sky2_is_copper(hw)) {
3003 ecmd->port = PORT_TP;
3004 ecmd->speed = sky2->speed;
3005 } else {
3006 ecmd->speed = SPEED_1000;
3007 ecmd->port = PORT_FIBRE;
3008 }
3009
3010 ecmd->advertising = sky2->advertising;
3011 ecmd->autoneg = sky2->autoneg;
3012 ecmd->duplex = sky2->duplex;
3013 return 0;
3014 }
3015
3016 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3017 {
3018 struct sky2_port *sky2 = netdev_priv(dev);
3019 const struct sky2_hw *hw = sky2->hw;
3020 u32 supported = sky2_supported_modes(hw);
3021
3022 if (ecmd->autoneg == AUTONEG_ENABLE) {
3023 ecmd->advertising = supported;
3024 sky2->duplex = -1;
3025 sky2->speed = -1;
3026 } else {
3027 u32 setting;
3028
3029 switch (ecmd->speed) {
3030 case SPEED_1000:
3031 if (ecmd->duplex == DUPLEX_FULL)
3032 setting = SUPPORTED_1000baseT_Full;
3033 else if (ecmd->duplex == DUPLEX_HALF)
3034 setting = SUPPORTED_1000baseT_Half;
3035 else
3036 return -EINVAL;
3037 break;
3038 case SPEED_100:
3039 if (ecmd->duplex == DUPLEX_FULL)
3040 setting = SUPPORTED_100baseT_Full;
3041 else if (ecmd->duplex == DUPLEX_HALF)
3042 setting = SUPPORTED_100baseT_Half;
3043 else
3044 return -EINVAL;
3045 break;
3046
3047 case SPEED_10:
3048 if (ecmd->duplex == DUPLEX_FULL)
3049 setting = SUPPORTED_10baseT_Full;
3050 else if (ecmd->duplex == DUPLEX_HALF)
3051 setting = SUPPORTED_10baseT_Half;
3052 else
3053 return -EINVAL;
3054 break;
3055 default:
3056 return -EINVAL;
3057 }
3058
3059 if ((setting & supported) == 0)
3060 return -EINVAL;
3061
3062 sky2->speed = ecmd->speed;
3063 sky2->duplex = ecmd->duplex;
3064 }
3065
3066 sky2->autoneg = ecmd->autoneg;
3067 sky2->advertising = ecmd->advertising;
3068
3069 if (netif_running(dev)) {
3070 sky2_phy_reinit(sky2);
3071 sky2_set_multicast(dev);
3072 }
3073
3074 return 0;
3075 }
3076
3077 static void sky2_get_drvinfo(struct net_device *dev,
3078 struct ethtool_drvinfo *info)
3079 {
3080 struct sky2_port *sky2 = netdev_priv(dev);
3081
3082 strcpy(info->driver, DRV_NAME);
3083 strcpy(info->version, DRV_VERSION);
3084 strcpy(info->fw_version, "N/A");
3085 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3086 }
3087
3088 static const struct sky2_stat {
3089 char name[ETH_GSTRING_LEN];
3090 u16 offset;
3091 } sky2_stats[] = {
3092 { "tx_bytes", GM_TXO_OK_HI },
3093 { "rx_bytes", GM_RXO_OK_HI },
3094 { "tx_broadcast", GM_TXF_BC_OK },
3095 { "rx_broadcast", GM_RXF_BC_OK },
3096 { "tx_multicast", GM_TXF_MC_OK },
3097 { "rx_multicast", GM_RXF_MC_OK },
3098 { "tx_unicast", GM_TXF_UC_OK },
3099 { "rx_unicast", GM_RXF_UC_OK },
3100 { "tx_mac_pause", GM_TXF_MPAUSE },
3101 { "rx_mac_pause", GM_RXF_MPAUSE },
3102 { "collisions", GM_TXF_COL },
3103 { "late_collision",GM_TXF_LAT_COL },
3104 { "aborted", GM_TXF_ABO_COL },
3105 { "single_collisions", GM_TXF_SNG_COL },
3106 { "multi_collisions", GM_TXF_MUL_COL },
3107
3108 { "rx_short", GM_RXF_SHT },
3109 { "rx_runt", GM_RXE_FRAG },
3110 { "rx_64_byte_packets", GM_RXF_64B },
3111 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3112 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3113 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3114 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3115 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3116 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3117 { "rx_too_long", GM_RXF_LNG_ERR },
3118 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3119 { "rx_jabber", GM_RXF_JAB_PKT },
3120 { "rx_fcs_error", GM_RXF_FCS_ERR },
3121
3122 { "tx_64_byte_packets", GM_TXF_64B },
3123 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3124 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3125 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3126 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3127 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3128 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3129 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3130 };
3131
3132 static u32 sky2_get_rx_csum(struct net_device *dev)
3133 {
3134 struct sky2_port *sky2 = netdev_priv(dev);
3135
3136 return sky2->rx_csum;
3137 }
3138
3139 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3140 {
3141 struct sky2_port *sky2 = netdev_priv(dev);
3142
3143 sky2->rx_csum = data;
3144
3145 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3146 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3147
3148 return 0;
3149 }
3150
3151 static u32 sky2_get_msglevel(struct net_device *netdev)
3152 {
3153 struct sky2_port *sky2 = netdev_priv(netdev);
3154 return sky2->msg_enable;
3155 }
3156
3157 static int sky2_nway_reset(struct net_device *dev)
3158 {
3159 struct sky2_port *sky2 = netdev_priv(dev);
3160
3161 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3162 return -EINVAL;
3163
3164 sky2_phy_reinit(sky2);
3165 sky2_set_multicast(dev);
3166
3167 return 0;
3168 }
3169
3170 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3171 {
3172 struct sky2_hw *hw = sky2->hw;
3173 unsigned port = sky2->port;
3174 int i;
3175
3176 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3177 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3178 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3179 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3180
3181 for (i = 2; i < count; i++)
3182 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3183 }
3184
3185 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3186 {
3187 struct sky2_port *sky2 = netdev_priv(netdev);
3188 sky2->msg_enable = value;
3189 }
3190
3191 static int sky2_get_sset_count(struct net_device *dev, int sset)
3192 {
3193 switch (sset) {
3194 case ETH_SS_STATS:
3195 return ARRAY_SIZE(sky2_stats);
3196 default:
3197 return -EOPNOTSUPP;
3198 }
3199 }
3200
3201 static void sky2_get_ethtool_stats(struct net_device *dev,
3202 struct ethtool_stats *stats, u64 * data)
3203 {
3204 struct sky2_port *sky2 = netdev_priv(dev);
3205
3206 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3207 }
3208
3209 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3210 {
3211 int i;
3212
3213 switch (stringset) {
3214 case ETH_SS_STATS:
3215 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3216 memcpy(data + i * ETH_GSTRING_LEN,
3217 sky2_stats[i].name, ETH_GSTRING_LEN);
3218 break;
3219 }
3220 }
3221
3222 static int sky2_set_mac_address(struct net_device *dev, void *p)
3223 {
3224 struct sky2_port *sky2 = netdev_priv(dev);
3225 struct sky2_hw *hw = sky2->hw;
3226 unsigned port = sky2->port;
3227 const struct sockaddr *addr = p;
3228
3229 if (!is_valid_ether_addr(addr->sa_data))
3230 return -EADDRNOTAVAIL;
3231
3232 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3233 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3234 dev->dev_addr, ETH_ALEN);
3235 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3236 dev->dev_addr, ETH_ALEN);
3237
3238 /* virtual address for data */
3239 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3240
3241 /* physical address: used for pause frames */
3242 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3243
3244 return 0;
3245 }
3246
3247 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3248 {
3249 u32 bit;
3250
3251 bit = ether_crc(ETH_ALEN, addr) & 63;
3252 filter[bit >> 3] |= 1 << (bit & 7);
3253 }
3254
3255 static void sky2_set_multicast(struct net_device *dev)
3256 {
3257 struct sky2_port *sky2 = netdev_priv(dev);
3258 struct sky2_hw *hw = sky2->hw;
3259 unsigned port = sky2->port;
3260 struct dev_mc_list *list = dev->mc_list;
3261 u16 reg;
3262 u8 filter[8];
3263 int rx_pause;
3264 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3265
3266 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3267 memset(filter, 0, sizeof(filter));
3268
3269 reg = gma_read16(hw, port, GM_RX_CTRL);
3270 reg |= GM_RXCR_UCF_ENA;
3271
3272 if (dev->flags & IFF_PROMISC) /* promiscuous */
3273 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3274 else if (dev->flags & IFF_ALLMULTI)
3275 memset(filter, 0xff, sizeof(filter));
3276 else if (dev->mc_count == 0 && !rx_pause)
3277 reg &= ~GM_RXCR_MCF_ENA;
3278 else {
3279 int i;
3280 reg |= GM_RXCR_MCF_ENA;
3281
3282 if (rx_pause)
3283 sky2_add_filter(filter, pause_mc_addr);
3284
3285 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3286 sky2_add_filter(filter, list->dmi_addr);
3287 }
3288
3289 gma_write16(hw, port, GM_MC_ADDR_H1,
3290 (u16) filter[0] | ((u16) filter[1] << 8));
3291 gma_write16(hw, port, GM_MC_ADDR_H2,
3292 (u16) filter[2] | ((u16) filter[3] << 8));
3293 gma_write16(hw, port, GM_MC_ADDR_H3,
3294 (u16) filter[4] | ((u16) filter[5] << 8));
3295 gma_write16(hw, port, GM_MC_ADDR_H4,
3296 (u16) filter[6] | ((u16) filter[7] << 8));
3297
3298 gma_write16(hw, port, GM_RX_CTRL, reg);
3299 }
3300
3301 /* Can have one global because blinking is controlled by
3302 * ethtool and that is always under RTNL mutex
3303 */
3304 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3305 {
3306 u16 pg;
3307
3308 switch (hw->chip_id) {
3309 case CHIP_ID_YUKON_XL:
3310 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3311 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3312 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3313 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3314 PHY_M_LEDC_INIT_CTRL(7) |
3315 PHY_M_LEDC_STA1_CTRL(7) |
3316 PHY_M_LEDC_STA0_CTRL(7))
3317 : 0);
3318
3319 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3320 break;
3321
3322 default:
3323 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3324 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3325 on ? PHY_M_LED_ALL : 0);
3326 }
3327 }
3328
3329 /* blink LED's for finding board */
3330 static int sky2_phys_id(struct net_device *dev, u32 data)
3331 {
3332 struct sky2_port *sky2 = netdev_priv(dev);
3333 struct sky2_hw *hw = sky2->hw;
3334 unsigned port = sky2->port;
3335 u16 ledctrl, ledover = 0;
3336 long ms;
3337 int interrupted;
3338 int onoff = 1;
3339
3340 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3341 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3342 else
3343 ms = data * 1000;
3344
3345 /* save initial values */
3346 spin_lock_bh(&sky2->phy_lock);
3347 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3348 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3349 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3350 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3351 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3352 } else {
3353 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3354 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3355 }
3356
3357 interrupted = 0;
3358 while (!interrupted && ms > 0) {
3359 sky2_led(hw, port, onoff);
3360 onoff = !onoff;
3361
3362 spin_unlock_bh(&sky2->phy_lock);
3363 interrupted = msleep_interruptible(250);
3364 spin_lock_bh(&sky2->phy_lock);
3365
3366 ms -= 250;
3367 }
3368
3369 /* resume regularly scheduled programming */
3370 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3371 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3372 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3373 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3374 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3375 } else {
3376 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3377 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3378 }
3379 spin_unlock_bh(&sky2->phy_lock);
3380
3381 return 0;
3382 }
3383
3384 static void sky2_get_pauseparam(struct net_device *dev,
3385 struct ethtool_pauseparam *ecmd)
3386 {
3387 struct sky2_port *sky2 = netdev_priv(dev);
3388
3389 switch (sky2->flow_mode) {
3390 case FC_NONE:
3391 ecmd->tx_pause = ecmd->rx_pause = 0;
3392 break;
3393 case FC_TX:
3394 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3395 break;
3396 case FC_RX:
3397 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3398 break;
3399 case FC_BOTH:
3400 ecmd->tx_pause = ecmd->rx_pause = 1;
3401 }
3402
3403 ecmd->autoneg = sky2->autoneg;
3404 }
3405
3406 static int sky2_set_pauseparam(struct net_device *dev,
3407 struct ethtool_pauseparam *ecmd)
3408 {
3409 struct sky2_port *sky2 = netdev_priv(dev);
3410
3411 sky2->autoneg = ecmd->autoneg;
3412 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3413
3414 if (netif_running(dev))
3415 sky2_phy_reinit(sky2);
3416
3417 return 0;
3418 }
3419
3420 static int sky2_get_coalesce(struct net_device *dev,
3421 struct ethtool_coalesce *ecmd)
3422 {
3423 struct sky2_port *sky2 = netdev_priv(dev);
3424 struct sky2_hw *hw = sky2->hw;
3425
3426 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3427 ecmd->tx_coalesce_usecs = 0;
3428 else {
3429 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3430 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3431 }
3432 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3433
3434 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3435 ecmd->rx_coalesce_usecs = 0;
3436 else {
3437 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3438 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3439 }
3440 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3441
3442 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3443 ecmd->rx_coalesce_usecs_irq = 0;
3444 else {
3445 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3446 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3447 }
3448
3449 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3450
3451 return 0;
3452 }
3453
3454 /* Note: this affect both ports */
3455 static int sky2_set_coalesce(struct net_device *dev,
3456 struct ethtool_coalesce *ecmd)
3457 {
3458 struct sky2_port *sky2 = netdev_priv(dev);
3459 struct sky2_hw *hw = sky2->hw;
3460 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3461
3462 if (ecmd->tx_coalesce_usecs > tmax ||
3463 ecmd->rx_coalesce_usecs > tmax ||
3464 ecmd->rx_coalesce_usecs_irq > tmax)
3465 return -EINVAL;
3466
3467 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3468 return -EINVAL;
3469 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3470 return -EINVAL;
3471 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3472 return -EINVAL;
3473
3474 if (ecmd->tx_coalesce_usecs == 0)
3475 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3476 else {
3477 sky2_write32(hw, STAT_TX_TIMER_INI,
3478 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3479 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3480 }
3481 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3482
3483 if (ecmd->rx_coalesce_usecs == 0)
3484 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3485 else {
3486 sky2_write32(hw, STAT_LEV_TIMER_INI,
3487 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3488 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3489 }
3490 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3491
3492 if (ecmd->rx_coalesce_usecs_irq == 0)
3493 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3494 else {
3495 sky2_write32(hw, STAT_ISR_TIMER_INI,
3496 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3497 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3498 }
3499 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3500 return 0;
3501 }
3502
3503 static void sky2_get_ringparam(struct net_device *dev,
3504 struct ethtool_ringparam *ering)
3505 {
3506 struct sky2_port *sky2 = netdev_priv(dev);
3507
3508 ering->rx_max_pending = RX_MAX_PENDING;
3509 ering->rx_mini_max_pending = 0;
3510 ering->rx_jumbo_max_pending = 0;
3511 ering->tx_max_pending = TX_RING_SIZE - 1;
3512
3513 ering->rx_pending = sky2->rx_pending;
3514 ering->rx_mini_pending = 0;
3515 ering->rx_jumbo_pending = 0;
3516 ering->tx_pending = sky2->tx_pending;
3517 }
3518
3519 static int sky2_set_ringparam(struct net_device *dev,
3520 struct ethtool_ringparam *ering)
3521 {
3522 struct sky2_port *sky2 = netdev_priv(dev);
3523 int err = 0;
3524
3525 if (ering->rx_pending > RX_MAX_PENDING ||
3526 ering->rx_pending < 8 ||
3527 ering->tx_pending < MAX_SKB_TX_LE ||
3528 ering->tx_pending > TX_RING_SIZE - 1)
3529 return -EINVAL;
3530
3531 if (netif_running(dev))
3532 sky2_down(dev);
3533
3534 sky2->rx_pending = ering->rx_pending;
3535 sky2->tx_pending = ering->tx_pending;
3536
3537 if (netif_running(dev)) {
3538 err = sky2_up(dev);
3539 if (err)
3540 dev_close(dev);
3541 else
3542 sky2_set_multicast(dev);
3543 }
3544
3545 return err;
3546 }
3547
3548 static int sky2_get_regs_len(struct net_device *dev)
3549 {
3550 return 0x4000;
3551 }
3552
3553 /*
3554 * Returns copy of control register region
3555 * Note: ethtool_get_regs always provides full size (16k) buffer
3556 */
3557 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3558 void *p)
3559 {
3560 const struct sky2_port *sky2 = netdev_priv(dev);
3561 const void __iomem *io = sky2->hw->regs;
3562 unsigned int b;
3563
3564 regs->version = 1;
3565
3566 for (b = 0; b < 128; b++) {
3567 /* This complicated switch statement is to make sure and
3568 * only access regions that are unreserved.
3569 * Some blocks are only valid on dual port cards.
3570 * and block 3 has some special diagnostic registers that
3571 * are poison.
3572 */
3573 switch (b) {
3574 case 3:
3575 /* skip diagnostic ram region */
3576 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3577 break;
3578
3579 /* dual port cards only */
3580 case 5: /* Tx Arbiter 2 */
3581 case 9: /* RX2 */
3582 case 14 ... 15: /* TX2 */
3583 case 17: case 19: /* Ram Buffer 2 */
3584 case 22 ... 23: /* Tx Ram Buffer 2 */
3585 case 25: /* Rx MAC Fifo 1 */
3586 case 27: /* Tx MAC Fifo 2 */
3587 case 31: /* GPHY 2 */
3588 case 40 ... 47: /* Pattern Ram 2 */
3589 case 52: case 54: /* TCP Segmentation 2 */
3590 case 112 ... 116: /* GMAC 2 */
3591 if (sky2->hw->ports == 1)
3592 goto reserved;
3593 /* fall through */
3594 case 0: /* Control */
3595 case 2: /* Mac address */
3596 case 4: /* Tx Arbiter 1 */
3597 case 7: /* PCI express reg */
3598 case 8: /* RX1 */
3599 case 12 ... 13: /* TX1 */
3600 case 16: case 18:/* Rx Ram Buffer 1 */
3601 case 20 ... 21: /* Tx Ram Buffer 1 */
3602 case 24: /* Rx MAC Fifo 1 */
3603 case 26: /* Tx MAC Fifo 1 */
3604 case 28 ... 29: /* Descriptor and status unit */
3605 case 30: /* GPHY 1*/
3606 case 32 ... 39: /* Pattern Ram 1 */
3607 case 48: case 50: /* TCP Segmentation 1 */
3608 case 56 ... 60: /* PCI space */
3609 case 80 ... 84: /* GMAC 1 */
3610 memcpy_fromio(p, io, 128);
3611 break;
3612 default:
3613 reserved:
3614 memset(p, 0, 128);
3615 }
3616
3617 p += 128;
3618 io += 128;
3619 }
3620 }
3621
3622 /* In order to do Jumbo packets on these chips, need to turn off the
3623 * transmit store/forward. Therefore checksum offload won't work.
3624 */
3625 static int no_tx_offload(struct net_device *dev)
3626 {
3627 const struct sky2_port *sky2 = netdev_priv(dev);
3628 const struct sky2_hw *hw = sky2->hw;
3629
3630 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3631 }
3632
3633 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3634 {
3635 if (data && no_tx_offload(dev))
3636 return -EINVAL;
3637
3638 return ethtool_op_set_tx_csum(dev, data);
3639 }
3640
3641
3642 static int sky2_set_tso(struct net_device *dev, u32 data)
3643 {
3644 if (data && no_tx_offload(dev))
3645 return -EINVAL;
3646
3647 return ethtool_op_set_tso(dev, data);
3648 }
3649
3650 static int sky2_get_eeprom_len(struct net_device *dev)
3651 {
3652 struct sky2_port *sky2 = netdev_priv(dev);
3653 u16 reg2;
3654
3655 pci_read_config_word(sky2->hw->pdev, PCI_DEV_REG2, &reg2);
3656 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3657 }
3658
3659 static u32 sky2_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
3660 {
3661 u32 val;
3662
3663 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
3664
3665 do {
3666 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
3667 } while (!(offset & PCI_VPD_ADDR_F));
3668
3669 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
3670 return val;
3671 }
3672
3673 static void sky2_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
3674 {
3675 pci_write_config_word(pdev, cap + PCI_VPD_DATA, val);
3676 pci_write_config_dword(pdev, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3677 do {
3678 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
3679 } while (offset & PCI_VPD_ADDR_F);
3680 }
3681
3682 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3683 u8 *data)
3684 {
3685 struct sky2_port *sky2 = netdev_priv(dev);
3686 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3687 int length = eeprom->len;
3688 u16 offset = eeprom->offset;
3689
3690 if (!cap)
3691 return -EINVAL;
3692
3693 eeprom->magic = SKY2_EEPROM_MAGIC;
3694
3695 while (length > 0) {
3696 u32 val = sky2_vpd_read(sky2->hw->pdev, cap, offset);
3697 int n = min_t(int, length, sizeof(val));
3698
3699 memcpy(data, &val, n);
3700 length -= n;
3701 data += n;
3702 offset += n;
3703 }
3704 return 0;
3705 }
3706
3707 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3708 u8 *data)
3709 {
3710 struct sky2_port *sky2 = netdev_priv(dev);
3711 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3712 int length = eeprom->len;
3713 u16 offset = eeprom->offset;
3714
3715 if (!cap)
3716 return -EINVAL;
3717
3718 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3719 return -EINVAL;
3720
3721 while (length > 0) {
3722 u32 val;
3723 int n = min_t(int, length, sizeof(val));
3724
3725 if (n < sizeof(val))
3726 val = sky2_vpd_read(sky2->hw->pdev, cap, offset);
3727 memcpy(&val, data, n);
3728
3729 sky2_vpd_write(sky2->hw->pdev, cap, offset, val);
3730
3731 length -= n;
3732 data += n;
3733 offset += n;
3734 }
3735 return 0;
3736 }
3737
3738
3739 static const struct ethtool_ops sky2_ethtool_ops = {
3740 .get_settings = sky2_get_settings,
3741 .set_settings = sky2_set_settings,
3742 .get_drvinfo = sky2_get_drvinfo,
3743 .get_wol = sky2_get_wol,
3744 .set_wol = sky2_set_wol,
3745 .get_msglevel = sky2_get_msglevel,
3746 .set_msglevel = sky2_set_msglevel,
3747 .nway_reset = sky2_nway_reset,
3748 .get_regs_len = sky2_get_regs_len,
3749 .get_regs = sky2_get_regs,
3750 .get_link = ethtool_op_get_link,
3751 .get_eeprom_len = sky2_get_eeprom_len,
3752 .get_eeprom = sky2_get_eeprom,
3753 .set_eeprom = sky2_set_eeprom,
3754 .set_sg = ethtool_op_set_sg,
3755 .set_tx_csum = sky2_set_tx_csum,
3756 .set_tso = sky2_set_tso,
3757 .get_rx_csum = sky2_get_rx_csum,
3758 .set_rx_csum = sky2_set_rx_csum,
3759 .get_strings = sky2_get_strings,
3760 .get_coalesce = sky2_get_coalesce,
3761 .set_coalesce = sky2_set_coalesce,
3762 .get_ringparam = sky2_get_ringparam,
3763 .set_ringparam = sky2_set_ringparam,
3764 .get_pauseparam = sky2_get_pauseparam,
3765 .set_pauseparam = sky2_set_pauseparam,
3766 .phys_id = sky2_phys_id,
3767 .get_sset_count = sky2_get_sset_count,
3768 .get_ethtool_stats = sky2_get_ethtool_stats,
3769 };
3770
3771 #ifdef CONFIG_SKY2_DEBUG
3772
3773 static struct dentry *sky2_debug;
3774
3775 static int sky2_debug_show(struct seq_file *seq, void *v)
3776 {
3777 struct net_device *dev = seq->private;
3778 const struct sky2_port *sky2 = netdev_priv(dev);
3779 struct sky2_hw *hw = sky2->hw;
3780 unsigned port = sky2->port;
3781 unsigned idx, last;
3782 int sop;
3783
3784 if (!netif_running(dev))
3785 return -ENETDOWN;
3786
3787 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3788 sky2_read32(hw, B0_ISRC),
3789 sky2_read32(hw, B0_IMSK),
3790 sky2_read32(hw, B0_Y2_SP_ICR));
3791
3792 napi_disable(&hw->napi);
3793 last = sky2_read16(hw, STAT_PUT_IDX);
3794
3795 if (hw->st_idx == last)
3796 seq_puts(seq, "Status ring (empty)\n");
3797 else {
3798 seq_puts(seq, "Status ring\n");
3799 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3800 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3801 const struct sky2_status_le *le = hw->st_le + idx;
3802 seq_printf(seq, "[%d] %#x %d %#x\n",
3803 idx, le->opcode, le->length, le->status);
3804 }
3805 seq_puts(seq, "\n");
3806 }
3807
3808 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3809 sky2->tx_cons, sky2->tx_prod,
3810 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3811 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3812
3813 /* Dump contents of tx ring */
3814 sop = 1;
3815 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3816 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3817 const struct sky2_tx_le *le = sky2->tx_le + idx;
3818 u32 a = le32_to_cpu(le->addr);
3819
3820 if (sop)
3821 seq_printf(seq, "%u:", idx);
3822 sop = 0;
3823
3824 switch(le->opcode & ~HW_OWNER) {
3825 case OP_ADDR64:
3826 seq_printf(seq, " %#x:", a);
3827 break;
3828 case OP_LRGLEN:
3829 seq_printf(seq, " mtu=%d", a);
3830 break;
3831 case OP_VLAN:
3832 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3833 break;
3834 case OP_TCPLISW:
3835 seq_printf(seq, " csum=%#x", a);
3836 break;
3837 case OP_LARGESEND:
3838 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3839 break;
3840 case OP_PACKET:
3841 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3842 break;
3843 case OP_BUFFER:
3844 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3845 break;
3846 default:
3847 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3848 a, le16_to_cpu(le->length));
3849 }
3850
3851 if (le->ctrl & EOP) {
3852 seq_putc(seq, '\n');
3853 sop = 1;
3854 }
3855 }
3856
3857 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3858 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3859 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3860 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3861
3862 napi_enable(&hw->napi);
3863 return 0;
3864 }
3865
3866 static int sky2_debug_open(struct inode *inode, struct file *file)
3867 {
3868 return single_open(file, sky2_debug_show, inode->i_private);
3869 }
3870
3871 static const struct file_operations sky2_debug_fops = {
3872 .owner = THIS_MODULE,
3873 .open = sky2_debug_open,
3874 .read = seq_read,
3875 .llseek = seq_lseek,
3876 .release = single_release,
3877 };
3878
3879 /*
3880 * Use network device events to create/remove/rename
3881 * debugfs file entries
3882 */
3883 static int sky2_device_event(struct notifier_block *unused,
3884 unsigned long event, void *ptr)
3885 {
3886 struct net_device *dev = ptr;
3887 struct sky2_port *sky2 = netdev_priv(dev);
3888
3889 if (dev->open != sky2_up || !sky2_debug)
3890 return NOTIFY_DONE;
3891
3892 switch(event) {
3893 case NETDEV_CHANGENAME:
3894 if (sky2->debugfs) {
3895 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3896 sky2_debug, dev->name);
3897 }
3898 break;
3899
3900 case NETDEV_GOING_DOWN:
3901 if (sky2->debugfs) {
3902 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3903 dev->name);
3904 debugfs_remove(sky2->debugfs);
3905 sky2->debugfs = NULL;
3906 }
3907 break;
3908
3909 case NETDEV_UP:
3910 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3911 sky2_debug, dev,
3912 &sky2_debug_fops);
3913 if (IS_ERR(sky2->debugfs))
3914 sky2->debugfs = NULL;
3915 }
3916
3917 return NOTIFY_DONE;
3918 }
3919
3920 static struct notifier_block sky2_notifier = {
3921 .notifier_call = sky2_device_event,
3922 };
3923
3924
3925 static __init void sky2_debug_init(void)
3926 {
3927 struct dentry *ent;
3928
3929 ent = debugfs_create_dir("sky2", NULL);
3930 if (!ent || IS_ERR(ent))
3931 return;
3932
3933 sky2_debug = ent;
3934 register_netdevice_notifier(&sky2_notifier);
3935 }
3936
3937 static __exit void sky2_debug_cleanup(void)
3938 {
3939 if (sky2_debug) {
3940 unregister_netdevice_notifier(&sky2_notifier);
3941 debugfs_remove(sky2_debug);
3942 sky2_debug = NULL;
3943 }
3944 }
3945
3946 #else
3947 #define sky2_debug_init()
3948 #define sky2_debug_cleanup()
3949 #endif
3950
3951
3952 /* Initialize network device */
3953 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3954 unsigned port,
3955 int highmem, int wol)
3956 {
3957 struct sky2_port *sky2;
3958 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3959
3960 if (!dev) {
3961 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3962 return NULL;
3963 }
3964
3965 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3966 dev->irq = hw->pdev->irq;
3967 dev->open = sky2_up;
3968 dev->stop = sky2_down;
3969 dev->do_ioctl = sky2_ioctl;
3970 dev->hard_start_xmit = sky2_xmit_frame;
3971 dev->set_multicast_list = sky2_set_multicast;
3972 dev->set_mac_address = sky2_set_mac_address;
3973 dev->change_mtu = sky2_change_mtu;
3974 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3975 dev->tx_timeout = sky2_tx_timeout;
3976 dev->watchdog_timeo = TX_WATCHDOG;
3977 #ifdef CONFIG_NET_POLL_CONTROLLER
3978 dev->poll_controller = sky2_netpoll;
3979 #endif
3980
3981 sky2 = netdev_priv(dev);
3982 sky2->netdev = dev;
3983 sky2->hw = hw;
3984 sky2->msg_enable = netif_msg_init(debug, default_msg);
3985
3986 /* Auto speed and flow control */
3987 sky2->autoneg = AUTONEG_ENABLE;
3988 sky2->flow_mode = FC_BOTH;
3989
3990 sky2->duplex = -1;
3991 sky2->speed = -1;
3992 sky2->advertising = sky2_supported_modes(hw);
3993 sky2->rx_csum = 1;
3994 sky2->wol = wol;
3995
3996 spin_lock_init(&sky2->phy_lock);
3997 sky2->tx_pending = TX_DEF_PENDING;
3998 sky2->rx_pending = RX_DEF_PENDING;
3999
4000 hw->dev[port] = dev;
4001
4002 sky2->port = port;
4003
4004 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4005 if (highmem)
4006 dev->features |= NETIF_F_HIGHDMA;
4007
4008 #ifdef SKY2_VLAN_TAG_USED
4009 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4010 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4011 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4012 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4013 dev->vlan_rx_register = sky2_vlan_rx_register;
4014 }
4015 #endif
4016
4017 /* read the mac address */
4018 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4019 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4020
4021 return dev;
4022 }
4023
4024 static void __devinit sky2_show_addr(struct net_device *dev)
4025 {
4026 const struct sky2_port *sky2 = netdev_priv(dev);
4027 DECLARE_MAC_BUF(mac);
4028
4029 if (netif_msg_probe(sky2))
4030 printk(KERN_INFO PFX "%s: addr %s\n",
4031 dev->name, print_mac(mac, dev->dev_addr));
4032 }
4033
4034 /* Handle software interrupt used during MSI test */
4035 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4036 {
4037 struct sky2_hw *hw = dev_id;
4038 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4039
4040 if (status == 0)
4041 return IRQ_NONE;
4042
4043 if (status & Y2_IS_IRQ_SW) {
4044 hw->flags |= SKY2_HW_USE_MSI;
4045 wake_up(&hw->msi_wait);
4046 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4047 }
4048 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4049
4050 return IRQ_HANDLED;
4051 }
4052
4053 /* Test interrupt path by forcing a a software IRQ */
4054 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4055 {
4056 struct pci_dev *pdev = hw->pdev;
4057 int err;
4058
4059 init_waitqueue_head (&hw->msi_wait);
4060
4061 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4062
4063 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4064 if (err) {
4065 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4066 return err;
4067 }
4068
4069 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4070 sky2_read8(hw, B0_CTST);
4071
4072 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4073
4074 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4075 /* MSI test failed, go back to INTx mode */
4076 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4077 "switching to INTx mode.\n");
4078
4079 err = -EOPNOTSUPP;
4080 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4081 }
4082
4083 sky2_write32(hw, B0_IMSK, 0);
4084 sky2_read32(hw, B0_IMSK);
4085
4086 free_irq(pdev->irq, hw);
4087
4088 return err;
4089 }
4090
4091 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4092 {
4093 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4094 u16 value;
4095
4096 if (!pm)
4097 return 0;
4098 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4099 return 0;
4100 return value & PCI_PM_CTRL_PME_ENABLE;
4101 }
4102
4103 static int __devinit sky2_probe(struct pci_dev *pdev,
4104 const struct pci_device_id *ent)
4105 {
4106 struct net_device *dev;
4107 struct sky2_hw *hw;
4108 int err, using_dac = 0, wol_default;
4109
4110 err = pci_enable_device(pdev);
4111 if (err) {
4112 dev_err(&pdev->dev, "cannot enable PCI device\n");
4113 goto err_out;
4114 }
4115
4116 err = pci_request_regions(pdev, DRV_NAME);
4117 if (err) {
4118 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4119 goto err_out_disable;
4120 }
4121
4122 pci_set_master(pdev);
4123
4124 if (sizeof(dma_addr_t) > sizeof(u32) &&
4125 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4126 using_dac = 1;
4127 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4128 if (err < 0) {
4129 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4130 "for consistent allocations\n");
4131 goto err_out_free_regions;
4132 }
4133 } else {
4134 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4135 if (err) {
4136 dev_err(&pdev->dev, "no usable DMA configuration\n");
4137 goto err_out_free_regions;
4138 }
4139 }
4140
4141 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4142
4143 err = -ENOMEM;
4144 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4145 if (!hw) {
4146 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4147 goto err_out_free_regions;
4148 }
4149
4150 hw->pdev = pdev;
4151
4152 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4153 if (!hw->regs) {
4154 dev_err(&pdev->dev, "cannot map device registers\n");
4155 goto err_out_free_hw;
4156 }
4157
4158 #ifdef __BIG_ENDIAN
4159 /* The sk98lin vendor driver uses hardware byte swapping but
4160 * this driver uses software swapping.
4161 */
4162 {
4163 u32 reg;
4164 pci_read_config_dword(pdev,PCI_DEV_REG2, &reg);
4165 reg &= ~PCI_REV_DESC;
4166 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4167 }
4168 #endif
4169
4170 /* ring for status responses */
4171 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4172 if (!hw->st_le)
4173 goto err_out_iounmap;
4174
4175 err = sky2_init(hw);
4176 if (err)
4177 goto err_out_iounmap;
4178
4179 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4180 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4181 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4182 hw->chip_id, hw->chip_rev);
4183
4184 sky2_reset(hw);
4185
4186 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4187 if (!dev) {
4188 err = -ENOMEM;
4189 goto err_out_free_pci;
4190 }
4191
4192 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4193 err = sky2_test_msi(hw);
4194 if (err == -EOPNOTSUPP)
4195 pci_disable_msi(pdev);
4196 else if (err)
4197 goto err_out_free_netdev;
4198 }
4199
4200 err = register_netdev(dev);
4201 if (err) {
4202 dev_err(&pdev->dev, "cannot register net device\n");
4203 goto err_out_free_netdev;
4204 }
4205
4206 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4207
4208 err = request_irq(pdev->irq, sky2_intr,
4209 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4210 dev->name, hw);
4211 if (err) {
4212 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4213 goto err_out_unregister;
4214 }
4215 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4216 napi_enable(&hw->napi);
4217
4218 sky2_show_addr(dev);
4219
4220 if (hw->ports > 1) {
4221 struct net_device *dev1;
4222
4223 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4224 if (!dev1)
4225 dev_warn(&pdev->dev, "allocation for second device failed\n");
4226 else if ((err = register_netdev(dev1))) {
4227 dev_warn(&pdev->dev,
4228 "register of second port failed (%d)\n", err);
4229 hw->dev[1] = NULL;
4230 free_netdev(dev1);
4231 } else
4232 sky2_show_addr(dev1);
4233 }
4234
4235 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4236 INIT_WORK(&hw->restart_work, sky2_restart);
4237
4238 pci_set_drvdata(pdev, hw);
4239
4240 return 0;
4241
4242 err_out_unregister:
4243 if (hw->flags & SKY2_HW_USE_MSI)
4244 pci_disable_msi(pdev);
4245 unregister_netdev(dev);
4246 err_out_free_netdev:
4247 free_netdev(dev);
4248 err_out_free_pci:
4249 sky2_write8(hw, B0_CTST, CS_RST_SET);
4250 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4251 err_out_iounmap:
4252 iounmap(hw->regs);
4253 err_out_free_hw:
4254 kfree(hw);
4255 err_out_free_regions:
4256 pci_release_regions(pdev);
4257 err_out_disable:
4258 pci_disable_device(pdev);
4259 err_out:
4260 pci_set_drvdata(pdev, NULL);
4261 return err;
4262 }
4263
4264 static void __devexit sky2_remove(struct pci_dev *pdev)
4265 {
4266 struct sky2_hw *hw = pci_get_drvdata(pdev);
4267 int i;
4268
4269 if (!hw)
4270 return;
4271
4272 del_timer_sync(&hw->watchdog_timer);
4273 cancel_work_sync(&hw->restart_work);
4274
4275 for (i = hw->ports-1; i >= 0; --i)
4276 unregister_netdev(hw->dev[i]);
4277
4278 sky2_write32(hw, B0_IMSK, 0);
4279
4280 sky2_power_aux(hw);
4281
4282 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4283 sky2_write8(hw, B0_CTST, CS_RST_SET);
4284 sky2_read8(hw, B0_CTST);
4285
4286 free_irq(pdev->irq, hw);
4287 if (hw->flags & SKY2_HW_USE_MSI)
4288 pci_disable_msi(pdev);
4289 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4290 pci_release_regions(pdev);
4291 pci_disable_device(pdev);
4292
4293 for (i = hw->ports-1; i >= 0; --i)
4294 free_netdev(hw->dev[i]);
4295
4296 iounmap(hw->regs);
4297 kfree(hw);
4298
4299 pci_set_drvdata(pdev, NULL);
4300 }
4301
4302 #ifdef CONFIG_PM
4303 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4304 {
4305 struct sky2_hw *hw = pci_get_drvdata(pdev);
4306 int i, wol = 0;
4307
4308 if (!hw)
4309 return 0;
4310
4311 for (i = 0; i < hw->ports; i++) {
4312 struct net_device *dev = hw->dev[i];
4313 struct sky2_port *sky2 = netdev_priv(dev);
4314
4315 if (netif_running(dev))
4316 sky2_down(dev);
4317
4318 if (sky2->wol)
4319 sky2_wol_init(sky2);
4320
4321 wol |= sky2->wol;
4322 }
4323
4324 sky2_write32(hw, B0_IMSK, 0);
4325 napi_disable(&hw->napi);
4326 sky2_power_aux(hw);
4327
4328 pci_save_state(pdev);
4329 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4330 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4331
4332 return 0;
4333 }
4334
4335 static int sky2_resume(struct pci_dev *pdev)
4336 {
4337 struct sky2_hw *hw = pci_get_drvdata(pdev);
4338 int i, err;
4339
4340 if (!hw)
4341 return 0;
4342
4343 err = pci_set_power_state(pdev, PCI_D0);
4344 if (err)
4345 goto out;
4346
4347 err = pci_restore_state(pdev);
4348 if (err)
4349 goto out;
4350
4351 pci_enable_wake(pdev, PCI_D0, 0);
4352
4353 /* Re-enable all clocks */
4354 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4355 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4356 hw->chip_id == CHIP_ID_YUKON_FE_P)
4357 pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4358
4359 sky2_reset(hw);
4360 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4361 napi_enable(&hw->napi);
4362
4363 for (i = 0; i < hw->ports; i++) {
4364 struct net_device *dev = hw->dev[i];
4365 if (netif_running(dev)) {
4366 err = sky2_up(dev);
4367 if (err) {
4368 printk(KERN_ERR PFX "%s: could not up: %d\n",
4369 dev->name, err);
4370 dev_close(dev);
4371 goto out;
4372 }
4373
4374 sky2_set_multicast(dev);
4375 }
4376 }
4377
4378 return 0;
4379 out:
4380 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4381 pci_disable_device(pdev);
4382 return err;
4383 }
4384 #endif
4385
4386 static void sky2_shutdown(struct pci_dev *pdev)
4387 {
4388 struct sky2_hw *hw = pci_get_drvdata(pdev);
4389 int i, wol = 0;
4390
4391 if (!hw)
4392 return;
4393
4394 del_timer_sync(&hw->watchdog_timer);
4395
4396 for (i = 0; i < hw->ports; i++) {
4397 struct net_device *dev = hw->dev[i];
4398 struct sky2_port *sky2 = netdev_priv(dev);
4399
4400 if (sky2->wol) {
4401 wol = 1;
4402 sky2_wol_init(sky2);
4403 }
4404 }
4405
4406 if (wol)
4407 sky2_power_aux(hw);
4408
4409 pci_enable_wake(pdev, PCI_D3hot, wol);
4410 pci_enable_wake(pdev, PCI_D3cold, wol);
4411
4412 pci_disable_device(pdev);
4413 pci_set_power_state(pdev, PCI_D3hot);
4414
4415 }
4416
4417 static struct pci_driver sky2_driver = {
4418 .name = DRV_NAME,
4419 .id_table = sky2_id_table,
4420 .probe = sky2_probe,
4421 .remove = __devexit_p(sky2_remove),
4422 #ifdef CONFIG_PM
4423 .suspend = sky2_suspend,
4424 .resume = sky2_resume,
4425 #endif
4426 .shutdown = sky2_shutdown,
4427 };
4428
4429 static int __init sky2_init_module(void)
4430 {
4431 sky2_debug_init();
4432 return pci_register_driver(&sky2_driver);
4433 }
4434
4435 static void __exit sky2_cleanup_module(void)
4436 {
4437 pci_unregister_driver(&sky2_driver);
4438 sky2_debug_cleanup();
4439 }
4440
4441 module_init(sky2_init_module);
4442 module_exit(sky2_cleanup_module);
4443
4444 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4445 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4446 MODULE_LICENSE("GPL");
4447 MODULE_VERSION(DRV_VERSION);
cpufreq for S3C2410