2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/config.h>
18 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/bootmem.h>
23 #include <linux/smp_lock.h>
24 #include <linux/interrupt.h>
25 #include <linux/mc146818rtc.h>
26 #include <linux/kernel_stat.h>
27 #include <linux/sysdev.h>
28 #include <linux/cpu.h>
29 #include <linux/module.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/arch_hooks.h>
38 #include <asm/i8253.h>
40 #include <mach_apic.h>
41 #include <mach_apicdef.h>
47 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
48 * IPIs in place of local APIC timers
50 static cpumask_t timer_bcast_ipi
;
53 * Knob to control our willingness to enable the local APIC.
55 int enable_local_apic __initdata
= 0; /* -1=force-disable, +1=force-enable */
63 static void apic_pm_activate(void);
66 * 'what should we do if we get a hw irq event on an illegal vector'.
67 * each architecture has to answer this themselves.
69 void ack_bad_irq(unsigned int irq
)
71 printk("unexpected IRQ trap at vector %02x\n", irq
);
73 * Currently unexpected vectors happen only on SMP and APIC.
74 * We _must_ ack these because every local APIC has only N
75 * irq slots per priority level, and a 'hanging, unacked' IRQ
76 * holds up an irq slot - in excessive cases (when multiple
77 * unexpected vectors occur) that might lock up the APIC
79 * But only ack when the APIC is enabled -AK
85 void __init
apic_intr_init(void)
90 /* self generated IPI for local APIC timer */
91 set_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
93 /* IPI vectors for APIC spurious and error interrupts */
94 set_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
95 set_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
97 /* thermal monitor LVT interrupt */
98 #ifdef CONFIG_X86_MCE_P4THERMAL
99 set_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
103 /* Using APIC to generate smp_local_timer_interrupt? */
104 int using_apic_timer
= 0;
106 static int enabled_via_apicbase
;
108 void enable_NMI_through_LVT0 (void * dummy
)
112 ver
= apic_read(APIC_LVR
);
113 ver
= GET_APIC_VERSION(ver
);
114 v
= APIC_DM_NMI
; /* unmask and set to NMI */
115 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
116 v
|= APIC_LVT_LEVEL_TRIGGER
;
117 apic_write_around(APIC_LVT0
, v
);
120 int get_physical_broadcast(void)
122 unsigned int lvr
, version
;
123 lvr
= apic_read(APIC_LVR
);
124 version
= GET_APIC_VERSION(lvr
);
125 if (!APIC_INTEGRATED(version
) || version
>= 0x14)
133 unsigned int v
, ver
, maxlvt
;
135 v
= apic_read(APIC_LVR
);
136 ver
= GET_APIC_VERSION(v
);
137 /* 82489DXs do not report # of LVT entries. */
138 maxlvt
= APIC_INTEGRATED(ver
) ? GET_APIC_MAXLVT(v
) : 2;
142 void clear_local_APIC(void)
147 maxlvt
= get_maxlvt();
150 * Masking an LVT entry on a P6 can trigger a local APIC error
151 * if the vector is zero. Mask LVTERR first to prevent this.
154 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
155 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
158 * Careful: we have to set masks only first to deassert
159 * any level-triggered sources.
161 v
= apic_read(APIC_LVTT
);
162 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
163 v
= apic_read(APIC_LVT0
);
164 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
165 v
= apic_read(APIC_LVT1
);
166 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
168 v
= apic_read(APIC_LVTPC
);
169 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
172 /* lets not touch this if we didn't frob it */
173 #ifdef CONFIG_X86_MCE_P4THERMAL
175 v
= apic_read(APIC_LVTTHMR
);
176 apic_write_around(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
180 * Clean APIC state for other OSs:
182 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
183 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
184 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
186 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
188 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
190 #ifdef CONFIG_X86_MCE_P4THERMAL
192 apic_write_around(APIC_LVTTHMR
, APIC_LVT_MASKED
);
194 v
= GET_APIC_VERSION(apic_read(APIC_LVR
));
195 if (APIC_INTEGRATED(v
)) { /* !82489DX */
196 if (maxlvt
> 3) /* Due to Pentium errata 3AP and 11AP. */
197 apic_write(APIC_ESR
, 0);
202 void __init
connect_bsp_APIC(void)
206 * Do not trust the local APIC being empty at bootup.
210 * PIC mode, enable APIC mode in the IMCR, i.e.
211 * connect BSP's local APIC to INT and NMI lines.
213 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
214 "enabling APIC mode.\n");
221 void disconnect_bsp_APIC(int virt_wire_setup
)
225 * Put the board back into PIC mode (has an effect
226 * only on certain older boards). Note that APIC
227 * interrupts, including IPIs, won't work beyond
228 * this point! The only exception are INIT IPIs.
230 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
231 "entering PIC mode.\n");
236 /* Go back to Virtual Wire compatibility mode */
239 /* For the spurious interrupt use vector F, and enable it */
240 value
= apic_read(APIC_SPIV
);
241 value
&= ~APIC_VECTOR_MASK
;
242 value
|= APIC_SPIV_APIC_ENABLED
;
244 apic_write_around(APIC_SPIV
, value
);
246 if (!virt_wire_setup
) {
247 /* For LVT0 make it edge triggered, active high, external and enabled */
248 value
= apic_read(APIC_LVT0
);
249 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
250 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
251 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
252 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
253 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
254 apic_write_around(APIC_LVT0
, value
);
258 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
261 /* For LVT1 make it edge triggered, active high, nmi and enabled */
262 value
= apic_read(APIC_LVT1
);
264 APIC_MODE_MASK
| APIC_SEND_PENDING
|
265 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
266 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
267 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
268 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
269 apic_write_around(APIC_LVT1
, value
);
273 void disable_local_APIC(void)
280 * Disable APIC (implies clearing of registers
283 value
= apic_read(APIC_SPIV
);
284 value
&= ~APIC_SPIV_APIC_ENABLED
;
285 apic_write_around(APIC_SPIV
, value
);
287 if (enabled_via_apicbase
) {
289 rdmsr(MSR_IA32_APICBASE
, l
, h
);
290 l
&= ~MSR_IA32_APICBASE_ENABLE
;
291 wrmsr(MSR_IA32_APICBASE
, l
, h
);
296 * This is to verify that we're looking at a real local APIC.
297 * Check these against your board if the CPUs aren't getting
298 * started for no apparent reason.
300 int __init
verify_local_APIC(void)
302 unsigned int reg0
, reg1
;
305 * The version register is read-only in a real APIC.
307 reg0
= apic_read(APIC_LVR
);
308 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
309 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
310 reg1
= apic_read(APIC_LVR
);
311 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
314 * The two version reads above should print the same
315 * numbers. If the second one is different, then we
316 * poke at a non-APIC.
322 * Check if the version looks reasonably.
324 reg1
= GET_APIC_VERSION(reg0
);
325 if (reg1
== 0x00 || reg1
== 0xff)
328 if (reg1
< 0x02 || reg1
== 0xff)
332 * The ID register is read/write in a real APIC.
334 reg0
= apic_read(APIC_ID
);
335 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
338 * The next two are just to see if we have sane values.
339 * They're only really relevant if we're in Virtual Wire
340 * compatibility mode, but most boxes are anymore.
342 reg0
= apic_read(APIC_LVT0
);
343 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
344 reg1
= apic_read(APIC_LVT1
);
345 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
350 void __init
sync_Arb_IDs(void)
352 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
353 unsigned int ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
354 if (ver
>= 0x14) /* P4 or higher */
359 apic_wait_icr_idle();
361 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
362 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
366 extern void __error_in_apic_c (void);
369 * An initial setup of the virtual wire mode.
371 void __init
init_bsp_APIC(void)
373 unsigned long value
, ver
;
376 * Don't do the setup now if we have a SMP BIOS as the
377 * through-I/O-APIC virtual wire mode might be active.
379 if (smp_found_config
|| !cpu_has_apic
)
382 value
= apic_read(APIC_LVR
);
383 ver
= GET_APIC_VERSION(value
);
386 * Do not trust the local APIC being empty at bootup.
393 value
= apic_read(APIC_SPIV
);
394 value
&= ~APIC_VECTOR_MASK
;
395 value
|= APIC_SPIV_APIC_ENABLED
;
397 /* This bit is reserved on P4/Xeon and should be cleared */
398 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 15))
399 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
401 value
|= APIC_SPIV_FOCUS_DISABLED
;
402 value
|= SPURIOUS_APIC_VECTOR
;
403 apic_write_around(APIC_SPIV
, value
);
406 * Set up the virtual wire mode.
408 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
410 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
411 value
|= APIC_LVT_LEVEL_TRIGGER
;
412 apic_write_around(APIC_LVT1
, value
);
415 void __devinit
setup_local_APIC(void)
417 unsigned long oldvalue
, value
, ver
, maxlvt
;
419 /* Pound the ESR really hard over the head with a big hammer - mbligh */
421 apic_write(APIC_ESR
, 0);
422 apic_write(APIC_ESR
, 0);
423 apic_write(APIC_ESR
, 0);
424 apic_write(APIC_ESR
, 0);
427 value
= apic_read(APIC_LVR
);
428 ver
= GET_APIC_VERSION(value
);
430 if ((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f)
434 * Double-check whether this APIC is really registered.
436 if (!apic_id_registered())
440 * Intel recommends to set DFR, LDR and TPR before enabling
441 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
442 * document number 292116). So here it goes...
447 * Set Task Priority to 'accept all'. We never change this
450 value
= apic_read(APIC_TASKPRI
);
451 value
&= ~APIC_TPRI_MASK
;
452 apic_write_around(APIC_TASKPRI
, value
);
455 * Now that we are all set up, enable the APIC
457 value
= apic_read(APIC_SPIV
);
458 value
&= ~APIC_VECTOR_MASK
;
462 value
|= APIC_SPIV_APIC_ENABLED
;
465 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
466 * certain networking cards. If high frequency interrupts are
467 * happening on a particular IOAPIC pin, plus the IOAPIC routing
468 * entry is masked/unmasked at a high rate as well then sooner or
469 * later IOAPIC line gets 'stuck', no more interrupts are received
470 * from the device. If focus CPU is disabled then the hang goes
473 * [ This bug can be reproduced easily with a level-triggered
474 * PCI Ne2000 networking cards and PII/PIII processors, dual
478 * Actually disabling the focus CPU check just makes the hang less
479 * frequent as it makes the interrupt distributon model be more
480 * like LRU than MRU (the short-term load is more even across CPUs).
481 * See also the comment in end_level_ioapic_irq(). --macro
484 /* Enable focus processor (bit==0) */
485 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
487 /* Disable focus processor (bit==1) */
488 value
|= APIC_SPIV_FOCUS_DISABLED
;
491 * Set spurious IRQ vector
493 value
|= SPURIOUS_APIC_VECTOR
;
494 apic_write_around(APIC_SPIV
, value
);
499 * set up through-local-APIC on the BP's LINT0. This is not
500 * strictly necessery in pure symmetric-IO mode, but sometimes
501 * we delegate interrupts to the 8259A.
504 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
506 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
507 if (!smp_processor_id() && (pic_mode
|| !value
)) {
508 value
= APIC_DM_EXTINT
;
509 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
512 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
513 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
516 apic_write_around(APIC_LVT0
, value
);
519 * only the BP should see the LINT1 NMI signal, obviously.
521 if (!smp_processor_id())
524 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
525 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
526 value
|= APIC_LVT_LEVEL_TRIGGER
;
527 apic_write_around(APIC_LVT1
, value
);
529 if (APIC_INTEGRATED(ver
) && !esr_disable
) { /* !82489DX */
530 maxlvt
= get_maxlvt();
531 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
532 apic_write(APIC_ESR
, 0);
533 oldvalue
= apic_read(APIC_ESR
);
535 value
= ERROR_APIC_VECTOR
; // enables sending errors
536 apic_write_around(APIC_LVTERR
, value
);
538 * spec says clear errors after enabling vector.
541 apic_write(APIC_ESR
, 0);
542 value
= apic_read(APIC_ESR
);
543 if (value
!= oldvalue
)
544 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
545 "vector: 0x%08lx after: 0x%08lx\n",
550 * Something untraceble is creating bad interrupts on
551 * secondary quads ... for the moment, just leave the
552 * ESR disabled - we can't do anything useful with the
553 * errors anyway - mbligh
555 printk("Leaving ESR disabled.\n");
557 printk("No ESR for 82489DX.\n");
560 if (nmi_watchdog
== NMI_LOCAL_APIC
)
561 setup_apic_nmi_watchdog();
566 * If Linux enabled the LAPIC against the BIOS default
567 * disable it down before re-entering the BIOS on shutdown.
568 * Otherwise the BIOS may get confused and not power-off.
569 * Additionally clear all LVT entries before disable_local_APIC
570 * for the case where Linux didn't enable the LAPIC.
572 void lapic_shutdown(void)
579 local_irq_save(flags
);
582 if (enabled_via_apicbase
)
583 disable_local_APIC();
585 local_irq_restore(flags
);
592 /* r/w apic fields */
593 unsigned int apic_id
;
594 unsigned int apic_taskpri
;
595 unsigned int apic_ldr
;
596 unsigned int apic_dfr
;
597 unsigned int apic_spiv
;
598 unsigned int apic_lvtt
;
599 unsigned int apic_lvtpc
;
600 unsigned int apic_lvt0
;
601 unsigned int apic_lvt1
;
602 unsigned int apic_lvterr
;
603 unsigned int apic_tmict
;
604 unsigned int apic_tdcr
;
605 unsigned int apic_thmr
;
608 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
612 if (!apic_pm_state
.active
)
615 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
616 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
617 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
618 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
619 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
620 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
621 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
622 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
623 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
624 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
625 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
626 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
627 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
629 local_irq_save(flags
);
630 disable_local_APIC();
631 local_irq_restore(flags
);
635 static int lapic_resume(struct sys_device
*dev
)
640 if (!apic_pm_state
.active
)
643 local_irq_save(flags
);
646 * Make sure the APICBASE points to the right address
648 * FIXME! This will be wrong if we ever support suspend on
649 * SMP! We'll need to do this as part of the CPU restore!
651 rdmsr(MSR_IA32_APICBASE
, l
, h
);
652 l
&= ~MSR_IA32_APICBASE_BASE
;
653 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
654 wrmsr(MSR_IA32_APICBASE
, l
, h
);
656 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
657 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
658 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
659 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
660 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
661 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
662 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
663 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
664 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
665 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
666 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
667 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
668 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
669 apic_write(APIC_ESR
, 0);
671 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
672 apic_write(APIC_ESR
, 0);
674 local_irq_restore(flags
);
679 * This device has no shutdown method - fully functioning local APICs
680 * are needed on every CPU up until machine_halt/restart/poweroff.
683 static struct sysdev_class lapic_sysclass
= {
684 set_kset_name("lapic"),
685 .resume
= lapic_resume
,
686 .suspend
= lapic_suspend
,
689 static struct sys_device device_lapic
= {
691 .cls
= &lapic_sysclass
,
694 static void __devinit
apic_pm_activate(void)
696 apic_pm_state
.active
= 1;
699 static int __init
init_lapic_sysfs(void)
705 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
707 error
= sysdev_class_register(&lapic_sysclass
);
709 error
= sysdev_register(&device_lapic
);
712 device_initcall(init_lapic_sysfs
);
714 #else /* CONFIG_PM */
716 static void apic_pm_activate(void) { }
718 #endif /* CONFIG_PM */
721 * Detect and enable local APICs on non-SMP boards.
722 * Original code written by Keir Fraser.
725 static int __init
apic_set_verbosity(char *str
)
727 if (strcmp("debug", str
) == 0)
728 apic_verbosity
= APIC_DEBUG
;
729 else if (strcmp("verbose", str
) == 0)
730 apic_verbosity
= APIC_VERBOSE
;
732 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
733 " use apic=verbose or apic=debug\n", str
);
738 __setup("apic=", apic_set_verbosity
);
740 static int __init
detect_init_APIC (void)
744 /* Disabled by kernel option? */
745 if (enable_local_apic
< 0)
748 switch (boot_cpu_data
.x86_vendor
) {
750 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
751 (boot_cpu_data
.x86
== 15))
754 case X86_VENDOR_INTEL
:
755 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
756 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
765 * Over-ride BIOS and try to enable the local
766 * APIC only if "lapic" specified.
768 if (enable_local_apic
<= 0) {
769 printk("Local APIC disabled by BIOS -- "
770 "you can enable it with \"lapic\"\n");
774 * Some BIOSes disable the local APIC in the
775 * APIC_BASE MSR. This can only be done in
776 * software for Intel P6 or later and AMD K7
777 * (Model > 1) or later.
779 rdmsr(MSR_IA32_APICBASE
, l
, h
);
780 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
781 printk("Local APIC disabled by BIOS -- reenabling.\n");
782 l
&= ~MSR_IA32_APICBASE_BASE
;
783 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
784 wrmsr(MSR_IA32_APICBASE
, l
, h
);
785 enabled_via_apicbase
= 1;
789 * The APIC feature bit should now be enabled
792 features
= cpuid_edx(1);
793 if (!(features
& (1 << X86_FEATURE_APIC
))) {
794 printk("Could not enable APIC!\n");
797 set_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
798 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
800 /* The BIOS may have set up the APIC at some other address */
801 rdmsr(MSR_IA32_APICBASE
, l
, h
);
802 if (l
& MSR_IA32_APICBASE_ENABLE
)
803 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
805 if (nmi_watchdog
!= NMI_NONE
)
806 nmi_watchdog
= NMI_LOCAL_APIC
;
808 printk("Found and enabled local APIC!\n");
815 printk("No local APIC present or hardware disabled\n");
819 void __init
init_apic_mappings(void)
821 unsigned long apic_phys
;
824 * If no local APIC can be found then set up a fake all
825 * zeroes page to simulate the local APIC and another
826 * one for the IO-APIC.
828 if (!smp_found_config
&& detect_init_APIC()) {
829 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
830 apic_phys
= __pa(apic_phys
);
832 apic_phys
= mp_lapic_addr
;
834 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
835 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
839 * Fetch the APIC ID of the BSP in case we have a
840 * default configuration (or the MP table is broken).
842 if (boot_cpu_physical_apicid
== -1U)
843 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
845 #ifdef CONFIG_X86_IO_APIC
847 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
850 for (i
= 0; i
< nr_ioapics
; i
++) {
851 if (smp_found_config
) {
852 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
855 "WARNING: bogus zero IO-APIC "
856 "address found in MPTABLE, "
857 "disabling IO/APIC support!\n");
858 smp_found_config
= 0;
859 skip_ioapic_setup
= 1;
860 goto fake_ioapic_page
;
864 ioapic_phys
= (unsigned long)
865 alloc_bootmem_pages(PAGE_SIZE
);
866 ioapic_phys
= __pa(ioapic_phys
);
868 set_fixmap_nocache(idx
, ioapic_phys
);
869 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
870 __fix_to_virt(idx
), ioapic_phys
);
878 * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
879 * per second. We assume that the caller has already set up the local
882 * The APIC timer is not exactly sync with the external timer chip, it
883 * closely follows bus clocks.
887 * The timer chip is already set up at HZ interrupts per second here,
888 * but we do not accept timer interrupts yet. We only allow the BP
891 static unsigned int __devinit
get_8254_timer_count(void)
897 spin_lock_irqsave(&i8253_lock
, flags
);
899 outb_p(0x00, PIT_MODE
);
900 count
= inb_p(PIT_CH0
);
901 count
|= inb_p(PIT_CH0
) << 8;
903 spin_unlock_irqrestore(&i8253_lock
, flags
);
908 /* next tick in 8254 can be caught by catching timer wraparound */
909 static void __devinit
wait_8254_wraparound(void)
911 unsigned int curr_count
, prev_count
;
913 curr_count
= get_8254_timer_count();
915 prev_count
= curr_count
;
916 curr_count
= get_8254_timer_count();
918 /* workaround for broken Mercury/Neptune */
919 if (prev_count
>= curr_count
+ 0x100)
920 curr_count
= get_8254_timer_count();
922 } while (prev_count
>= curr_count
);
926 * Default initialization for 8254 timers. If we use other timers like HPET,
927 * we override this later
929 void (*wait_timer_tick
)(void) __devinitdata
= wait_8254_wraparound
;
932 * This function sets up the local APIC timer, with a timeout of
933 * 'clocks' APIC bus clock. During calibration we actually call
934 * this function twice on the boot CPU, once with a bogus timeout
935 * value, second time for real. The other (noncalibrating) CPUs
936 * call this function only once, with the real, calibrated value.
938 * We do reads before writes even if unnecessary, to get around the
939 * P5 APIC double write bug.
942 #define APIC_DIVISOR 16
944 static void __setup_APIC_LVTT(unsigned int clocks
)
946 unsigned int lvtt_value
, tmp_value
, ver
;
947 int cpu
= smp_processor_id();
949 ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
950 lvtt_value
= APIC_LVT_TIMER_PERIODIC
| LOCAL_TIMER_VECTOR
;
951 if (!APIC_INTEGRATED(ver
))
952 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
954 if (cpu_isset(cpu
, timer_bcast_ipi
))
955 lvtt_value
|= APIC_LVT_MASKED
;
957 apic_write_around(APIC_LVTT
, lvtt_value
);
962 tmp_value
= apic_read(APIC_TDCR
);
963 apic_write_around(APIC_TDCR
, (tmp_value
964 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
967 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
970 static void __devinit
setup_APIC_timer(unsigned int clocks
)
974 local_irq_save(flags
);
977 * Wait for IRQ0's slice:
981 __setup_APIC_LVTT(clocks
);
983 local_irq_restore(flags
);
987 * In this function we calibrate APIC bus clocks to the external
988 * timer. Unfortunately we cannot use jiffies and the timer irq
989 * to calibrate, since some later bootup code depends on getting
990 * the first irq? Ugh.
992 * We want to do the calibration only once since we
993 * want to have local timer irqs syncron. CPUs connected
994 * by the same APIC bus have the very same bus frequency.
995 * And we want to have irqs off anyways, no accidental
999 static int __init
calibrate_APIC_clock(void)
1001 unsigned long long t1
= 0, t2
= 0;
1005 const int LOOPS
= HZ
/10;
1007 apic_printk(APIC_VERBOSE
, "calibrating APIC timer ...\n");
1010 * Put whatever arbitrary (but long enough) timeout
1011 * value into the APIC clock, we just want to get the
1012 * counter running for calibration.
1014 __setup_APIC_LVTT(1000000000);
1017 * The timer chip counts down to zero. Let's wait
1018 * for a wraparound to start exact measurement:
1019 * (the current tick might have been already half done)
1025 * We wrapped around just now. Let's start:
1029 tt1
= apic_read(APIC_TMCCT
);
1032 * Let's wait LOOPS wraprounds:
1034 for (i
= 0; i
< LOOPS
; i
++)
1037 tt2
= apic_read(APIC_TMCCT
);
1042 * The APIC bus clock counter is 32 bits only, it
1043 * might have overflown, but note that we use signed
1044 * longs, thus no extra care needed.
1046 * underflown to be exact, as the timer counts down ;)
1049 result
= (tt1
-tt2
)*APIC_DIVISOR
/LOOPS
;
1052 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
1054 ((long)(t2
-t1
)/LOOPS
)/(1000000/HZ
),
1055 ((long)(t2
-t1
)/LOOPS
)%(1000000/HZ
));
1057 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
1059 result
/(1000000/HZ
),
1060 result
%(1000000/HZ
));
1065 static unsigned int calibration_result
;
1067 void __init
setup_boot_APIC_clock(void)
1069 unsigned long flags
;
1070 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n");
1071 using_apic_timer
= 1;
1073 local_irq_save(flags
);
1075 calibration_result
= calibrate_APIC_clock();
1077 * Now set up the timer for real.
1079 setup_APIC_timer(calibration_result
);
1081 local_irq_restore(flags
);
1084 void __devinit
setup_secondary_APIC_clock(void)
1086 setup_APIC_timer(calibration_result
);
1089 void disable_APIC_timer(void)
1091 if (using_apic_timer
) {
1094 v
= apic_read(APIC_LVTT
);
1095 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
1099 void enable_APIC_timer(void)
1101 int cpu
= smp_processor_id();
1103 if (using_apic_timer
&&
1104 !cpu_isset(cpu
, timer_bcast_ipi
)) {
1107 v
= apic_read(APIC_LVTT
);
1108 apic_write_around(APIC_LVTT
, v
& ~APIC_LVT_MASKED
);
1112 void switch_APIC_timer_to_ipi(void *cpumask
)
1114 cpumask_t mask
= *(cpumask_t
*)cpumask
;
1115 int cpu
= smp_processor_id();
1117 if (cpu_isset(cpu
, mask
) &&
1118 !cpu_isset(cpu
, timer_bcast_ipi
)) {
1119 disable_APIC_timer();
1120 cpu_set(cpu
, timer_bcast_ipi
);
1123 EXPORT_SYMBOL(switch_APIC_timer_to_ipi
);
1125 void switch_ipi_to_APIC_timer(void *cpumask
)
1127 cpumask_t mask
= *(cpumask_t
*)cpumask
;
1128 int cpu
= smp_processor_id();
1130 if (cpu_isset(cpu
, mask
) &&
1131 cpu_isset(cpu
, timer_bcast_ipi
)) {
1132 cpu_clear(cpu
, timer_bcast_ipi
);
1133 enable_APIC_timer();
1136 EXPORT_SYMBOL(switch_ipi_to_APIC_timer
);
1141 * Local timer interrupt handler. It does both profiling and
1142 * process statistics/rescheduling.
1144 * We do profiling in every local tick, statistics/rescheduling
1145 * happen only every 'profiling multiplier' ticks. The default
1146 * multiplier is 1 and it can be changed by writing the new multiplier
1147 * value into /proc/profile.
1150 inline void smp_local_timer_interrupt(struct pt_regs
* regs
)
1152 profile_tick(CPU_PROFILING
, regs
);
1154 update_process_times(user_mode_vm(regs
));
1158 * We take the 'long' return path, and there every subsystem
1159 * grabs the apropriate locks (kernel lock/ irq lock).
1161 * we might want to decouple profiling from the 'long path',
1162 * and do the profiling totally in assembly.
1164 * Currently this isn't too much of an issue (performance wise),
1165 * we can take more than 100K local irqs per second on a 100 MHz P5.
1170 * Local APIC timer interrupt. This is the most natural way for doing
1171 * local interrupts, but local timer interrupts can be emulated by
1172 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1174 * [ if a single-CPU system runs an SMP kernel then we call the local
1175 * interrupt as well. Thus we cannot inline the local irq ... ]
1178 fastcall
void smp_apic_timer_interrupt(struct pt_regs
*regs
)
1180 int cpu
= smp_processor_id();
1183 * the NMI deadlock-detector uses this.
1185 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
1188 * NOTE! We'd better ACK the irq immediately,
1189 * because timer handling can be slow.
1193 * update_process_times() expects us to have done irq_enter().
1194 * Besides, if we don't timer interrupts ignore the global
1195 * interrupt lock, which is the WrongThing (tm) to do.
1198 smp_local_timer_interrupt(regs
);
1203 static void up_apic_timer_interrupt_call(struct pt_regs
*regs
)
1205 int cpu
= smp_processor_id();
1208 * the NMI deadlock-detector uses this.
1210 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
1212 smp_local_timer_interrupt(regs
);
1216 void smp_send_timer_broadcast_ipi(struct pt_regs
*regs
)
1220 cpus_and(mask
, cpu_online_map
, timer_bcast_ipi
);
1221 if (!cpus_empty(mask
)) {
1223 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
1226 * We can directly call the apic timer interrupt handler
1227 * in UP case. Minus all irq related functions
1229 up_apic_timer_interrupt_call(regs
);
1234 int setup_profiling_timer(unsigned int multiplier
)
1240 * This interrupt should _never_ happen with our APIC/SMP architecture
1242 fastcall
void smp_spurious_interrupt(struct pt_regs
*regs
)
1248 * Check if this really is a spurious interrupt and ACK it
1249 * if it is a vectored one. Just in case...
1250 * Spurious interrupts should not be ACKed.
1252 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1253 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1256 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1257 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, should never happen.\n",
1258 smp_processor_id());
1263 * This interrupt should never happen with our APIC/SMP architecture
1266 fastcall
void smp_error_interrupt(struct pt_regs
*regs
)
1268 unsigned long v
, v1
;
1271 /* First tickle the hardware, only then report what went on. -- REW */
1272 v
= apic_read(APIC_ESR
);
1273 apic_write(APIC_ESR
, 0);
1274 v1
= apic_read(APIC_ESR
);
1276 atomic_inc(&irq_err_count
);
1278 /* Here is what the APIC error bits mean:
1281 2: Send accept error
1282 3: Receive accept error
1284 5: Send illegal vector
1285 6: Received illegal vector
1286 7: Illegal register address
1288 printk (KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1289 smp_processor_id(), v
, v1
);
1294 * This initializes the IO-APIC and APIC hardware if this is
1297 int __init
APIC_init_uniprocessor (void)
1299 if (enable_local_apic
< 0)
1300 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1302 if (!smp_found_config
&& !cpu_has_apic
)
1306 * Complain if the BIOS pretends there is one.
1308 if (!cpu_has_apic
&& APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1309 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1310 boot_cpu_physical_apicid
);
1311 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1315 verify_local_APIC();
1319 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
1323 #ifdef CONFIG_X86_IO_APIC
1324 if (smp_found_config
)
1325 if (!skip_ioapic_setup
&& nr_ioapics
)
1328 setup_boot_APIC_clock();