include/asm-powerpc/system.h

   1 /*
   2  * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
   3  */
   4 #ifndef _ASM_POWERPC_SYSTEM_H
   5 #define _ASM_POWERPC_SYSTEM_H
   6
   7 #include <linux/kernel.h>
   8
   9 #include <asm/hw_irq.h>
  10
  11 /*
  12  * Memory barrier.
  13  * The sync instruction guarantees that all memory accesses initiated
  14  * by this processor have been performed (with respect to all other
  15  * mechanisms that access memory).  The eieio instruction is a barrier
  16  * providing an ordering (separately) for (a) cacheable stores and (b)
  17  * loads and stores to non-cacheable memory (e.g. I/O devices).
  18  *
  19  * mb() prevents loads and stores being reordered across this point.
  20  * rmb() prevents loads being reordered across this point.
  21  * wmb() prevents stores being reordered across this point.
  22  * read_barrier_depends() prevents data-dependent loads being reordered
  23  *      across this point (nop on PPC).
  24  *
  25  * We have to use the sync instructions for mb(), since lwsync doesn't
  26  * order loads with respect to previous stores.  Lwsync is fine for
  27  * rmb(), though. Note that rmb() actually uses a sync on 32-bit
  28  * architectures.
  29  *
  30  * For wmb(), we use sync since wmb is used in drivers to order
  31  * stores to system memory with respect to writes to the device.
  32  * However, smp_wmb() can be a lighter-weight eieio barrier on
  33  * SMP since it is only used to order updates to system memory.
  34  */
  35 #define mb()   __asm__ __volatile__ ("sync" : : : "memory")
  36 #define rmb()  __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory")
  37 #define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
  38 #define read_barrier_depends()  do { } while(0)
  39
  40 #define set_mb(var, value)      do { var = value; mb(); } while (0)
  41
  42 #ifdef __KERNEL__
  43 #ifdef CONFIG_SMP
  44 #define smp_mb()        mb()
  45 #define smp_rmb()       rmb()
  46 #define smp_wmb()       __asm__ __volatile__ ("eieio" : : : "memory")
  47 #define smp_read_barrier_depends()      read_barrier_depends()
  48 #else
  49 #define smp_mb()        barrier()
  50 #define smp_rmb()       barrier()
  51 #define smp_wmb()       barrier()
  52 #define smp_read_barrier_depends()      do { } while(0)
  53 #endif /* CONFIG_SMP */
  54
  55 /*
  56  * This is a barrier which prevents following instructions from being
  57  * started until the value of the argument x is known.  For example, if
  58  * x is a variable loaded from memory, this prevents following
  59  * instructions from being executed until the load has been performed.
  60  */
  61 #define data_barrier(x) \
  62         asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
  63
  64 struct task_struct;
  65 struct pt_regs;
  66
  67 #ifdef CONFIG_DEBUGGER
  68
  69 extern int (*__debugger)(struct pt_regs *regs);
  70 extern int (*__debugger_ipi)(struct pt_regs *regs);
  71 extern int (*__debugger_bpt)(struct pt_regs *regs);
  72 extern int (*__debugger_sstep)(struct pt_regs *regs);
  73 extern int (*__debugger_iabr_match)(struct pt_regs *regs);
  74 extern int (*__debugger_dabr_match)(struct pt_regs *regs);
  75 extern int (*__debugger_fault_handler)(struct pt_regs *regs);
  76
  77 #define DEBUGGER_BOILERPLATE(__NAME) \
  78 static inline int __NAME(struct pt_regs *regs) \
  79 { \
  80         if (unlikely(__ ## __NAME)) \
  81                 return __ ## __NAME(regs); \
  82         return 0; \
  83 }
  84
  85 DEBUGGER_BOILERPLATE(debugger)
  86 DEBUGGER_BOILERPLATE(debugger_ipi)
  87 DEBUGGER_BOILERPLATE(debugger_bpt)
  88 DEBUGGER_BOILERPLATE(debugger_sstep)
  89 DEBUGGER_BOILERPLATE(debugger_iabr_match)
  90 DEBUGGER_BOILERPLATE(debugger_dabr_match)
  91 DEBUGGER_BOILERPLATE(debugger_fault_handler)
  92
  93 #else
  94 static inline int debugger(struct pt_regs *regs) { return 0; }
  95 static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
  96 static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
  97 static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
  98 static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
  99 static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
 100 static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
 101 #endif
 102
 103 extern int set_dabr(unsigned long dabr);
 104 extern void print_backtrace(unsigned long *);
 105 extern void show_regs(struct pt_regs * regs);
 106 extern void flush_instruction_cache(void);
 107 extern void hard_reset_now(void);
 108 extern void poweroff_now(void);
 109
 110 #ifdef CONFIG_6xx
 111 extern long _get_L2CR(void);
 112 extern long _get_L3CR(void);
 113 extern void _set_L2CR(unsigned long);
 114 extern void _set_L3CR(unsigned long);
 115 #else
 116 #define _get_L2CR()     0L
 117 #define _get_L3CR()     0L
 118 #define _set_L2CR(val)  do { } while(0)
 119 #define _set_L3CR(val)  do { } while(0)
 120 #endif
 121
 122 extern void via_cuda_init(void);
 123 extern void read_rtc_time(void);
 124 extern void pmac_find_display(void);
 125 extern void giveup_fpu(struct task_struct *);
 126 extern void disable_kernel_fp(void);
 127 extern void enable_kernel_fp(void);
 128 extern void flush_fp_to_thread(struct task_struct *);
 129 extern void enable_kernel_altivec(void);
 130 extern void giveup_altivec(struct task_struct *);
 131 extern void load_up_altivec(struct task_struct *);
 132 extern int emulate_altivec(struct pt_regs *);
 133 extern void enable_kernel_spe(void);
 134 extern void giveup_spe(struct task_struct *);
 135 extern void load_up_spe(struct task_struct *);
 136 extern int fix_alignment(struct pt_regs *);
 137 extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
 138 extern void cvt_df(double *from, float *to, struct thread_struct *thread);
 139
 140 #ifndef CONFIG_SMP
 141 extern void discard_lazy_cpu_state(void);
 142 #else
 143 static inline void discard_lazy_cpu_state(void)
 144 {
 145 }
 146 #endif
 147
 148 #ifdef CONFIG_ALTIVEC
 149 extern void flush_altivec_to_thread(struct task_struct *);
 150 #else
 151 static inline void flush_altivec_to_thread(struct task_struct *t)
 152 {
 153 }
 154 #endif
 155
 156 #ifdef CONFIG_SPE
 157 extern void flush_spe_to_thread(struct task_struct *);
 158 #else
 159 static inline void flush_spe_to_thread(struct task_struct *t)
 160 {
 161 }
 162 #endif
 163
 164 extern int call_rtas(const char *, int, int, unsigned long *, ...);
 165 extern void cacheable_memzero(void *p, unsigned int nb);
 166 extern void *cacheable_memcpy(void *, const void *, unsigned int);
 167 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
 168 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
 169 extern int die(const char *, struct pt_regs *, long);
 170 extern void _exception(int, struct pt_regs *, int, unsigned long);
 171 #ifdef CONFIG_BOOKE_WDT
 172 extern u32 booke_wdt_enabled;
 173 extern u32 booke_wdt_period;
 174 #endif /* CONFIG_BOOKE_WDT */
 175
 176 struct device_node;
 177 extern void note_scsi_host(struct device_node *, void *);
 178
 179 extern struct task_struct *__switch_to(struct task_struct *,
 180         struct task_struct *);
 181 #define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
 182
 183 struct thread_struct;
 184 extern struct task_struct *_switch(struct thread_struct *prev,
 185                                    struct thread_struct *next);
 186
 187 /*
 188  * On SMP systems, when the scheduler does migration-cost autodetection,
 189  * it needs a way to flush as much of the CPU's caches as possible.
 190  *
 191  * TODO: fill this in!
 192  */
 193 static inline void sched_cacheflush(void)
 194 {
 195 }
 196
 197 extern unsigned int rtas_data;
 198 extern int mem_init_done;       /* set on boot once kmalloc can be called */
 199 extern unsigned long memory_limit;
 200 extern unsigned long klimit;
 201
 202 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 203
 204 /*
 205  * Atomic exchange
 206  *
 207  * Changes the memory location '*ptr' to be val and returns
 208  * the previous value stored there.
 209  */
 210 static __inline__ unsigned long
 211 __xchg_u32(volatile void *p, unsigned long val)
 212 {
 213         unsigned long prev;
 214
 215         __asm__ __volatile__(
 216         LWSYNC_ON_SMP
 217 "1:     lwarx   %0,0,%2 \n"
 218         PPC405_ERR77(0,%2)
 219 "       stwcx.  %3,0,%2 \n\
 220         bne-    1b"
 221         ISYNC_ON_SMP
 222         : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
 223         : "r" (p), "r" (val)
 224         : "cc", "memory");
 225
 226         return prev;
 227 }
 228
 229 /*
 230  * Atomic exchange
 231  *
 232  * Changes the memory location '*ptr' to be val and returns
 233  * the previous value stored there.
 234  */
 235 static __inline__ unsigned long
 236 __xchg_u32_local(volatile void *p, unsigned long val)
 237 {
 238         unsigned long prev;
 239
 240         __asm__ __volatile__(
 241 "1:     lwarx   %0,0,%2 \n"
 242         PPC405_ERR77(0,%2)
 243 "       stwcx.  %3,0,%2 \n\
 244         bne-    1b"
 245         : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
 246         : "r" (p), "r" (val)
 247         : "cc", "memory");
 248
 249         return prev;
 250 }
 251
 252 #ifdef CONFIG_PPC64
 253 static __inline__ unsigned long
 254 __xchg_u64(volatile void *p, unsigned long val)
 255 {
 256         unsigned long prev;
 257
 258         __asm__ __volatile__(
 259         LWSYNC_ON_SMP
 260 "1:     ldarx   %0,0,%2 \n"
 261         PPC405_ERR77(0,%2)
 262 "       stdcx.  %3,0,%2 \n\
 263         bne-    1b"
 264         ISYNC_ON_SMP
 265         : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
 266         : "r" (p), "r" (val)
 267         : "cc", "memory");
 268
 269         return prev;
 270 }
 271
 272 static __inline__ unsigned long
 273 __xchg_u64_local(volatile void *p, unsigned long val)
 274 {
 275         unsigned long prev;
 276
 277         __asm__ __volatile__(
 278 "1:     ldarx   %0,0,%2 \n"
 279         PPC405_ERR77(0,%2)
 280 "       stdcx.  %3,0,%2 \n\
 281         bne-    1b"
 282         : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
 283         : "r" (p), "r" (val)
 284         : "cc", "memory");
 285
 286         return prev;
 287 }
 288 #endif
 289
 290 /*
 291  * This function doesn't exist, so you'll get a linker error
 292  * if something tries to do an invalid xchg().
 293  */
 294 extern void __xchg_called_with_bad_pointer(void);
 295
 296 static __inline__ unsigned long
 297 __xchg(volatile void *ptr, unsigned long x, unsigned int size)
 298 {
 299         switch (size) {
 300         case 4:
 301                 return __xchg_u32(ptr, x);
 302 #ifdef CONFIG_PPC64
 303         case 8:
 304                 return __xchg_u64(ptr, x);
 305 #endif
 306         }
 307         __xchg_called_with_bad_pointer();
 308         return x;
 309 }
 310
 311 static __inline__ unsigned long
 312 __xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
 313 {
 314         switch (size) {
 315         case 4:
 316                 return __xchg_u32_local(ptr, x);
 317 #ifdef CONFIG_PPC64
 318         case 8:
 319                 return __xchg_u64_local(ptr, x);
 320 #endif
 321         }
 322         __xchg_called_with_bad_pointer();
 323         return x;
 324 }
 325 #define xchg(ptr,x)                                                          \
 326   ({                                                                         \
 327      __typeof__(*(ptr)) _x_ = (x);                                           \
 328      (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
 329   })
 330
 331 #define xchg_local(ptr,x)                                                    \
 332   ({                                                                         \
 333      __typeof__(*(ptr)) _x_ = (x);                                           \
 334      (__typeof__(*(ptr))) __xchg_local((ptr),                                \
 335                 (unsigned long)_x_, sizeof(*(ptr)));                         \
 336   })
 337
 338 #define tas(ptr) (xchg((ptr),1))
 339
 340 /*
 341  * Compare and exchange - if *p == old, set it to new,
 342  * and return the old value of *p.
 343  */
 344 #define __HAVE_ARCH_CMPXCHG     1
 345
 346 static __inline__ unsigned long
 347 __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
 348 {
 349         unsigned int prev;
 350
 351         __asm__ __volatile__ (
 352         LWSYNC_ON_SMP
 353 "1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
 354         cmpw    0,%0,%3\n\
 355         bne-    2f\n"
 356         PPC405_ERR77(0,%2)
 357 "       stwcx.  %4,0,%2\n\
 358         bne-    1b"
 359         ISYNC_ON_SMP
 360         "\n\
 361 2:"
 362         : "=&r" (prev), "+m" (*p)
 363         : "r" (p), "r" (old), "r" (new)
 364         : "cc", "memory");
 365
 366         return prev;
 367 }
 368
 369 static __inline__ unsigned long
 370 __cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
 371                         unsigned long new)
 372 {
 373         unsigned int prev;
 374
 375         __asm__ __volatile__ (
 376 "1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
 377         cmpw    0,%0,%3\n\
 378         bne-    2f\n"
 379         PPC405_ERR77(0,%2)
 380 "       stwcx.  %4,0,%2\n\
 381         bne-    1b"
 382         "\n\
 383 2:"
 384         : "=&r" (prev), "+m" (*p)
 385         : "r" (p), "r" (old), "r" (new)
 386         : "cc", "memory");
 387
 388         return prev;
 389 }
 390
 391 #ifdef CONFIG_PPC64
 392 static __inline__ unsigned long
 393 __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
 394 {
 395         unsigned long prev;
 396
 397         __asm__ __volatile__ (
 398         LWSYNC_ON_SMP
 399 "1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
 400         cmpd    0,%0,%3\n\
 401         bne-    2f\n\
 402         stdcx.  %4,0,%2\n\
 403         bne-    1b"
 404         ISYNC_ON_SMP
 405         "\n\
 406 2:"
 407         : "=&r" (prev), "+m" (*p)
 408         : "r" (p), "r" (old), "r" (new)
 409         : "cc", "memory");
 410
 411         return prev;
 412 }
 413
 414 static __inline__ unsigned long
 415 __cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
 416                         unsigned long new)
 417 {
 418         unsigned long prev;
 419
 420         __asm__ __volatile__ (
 421 "1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
 422         cmpd    0,%0,%3\n\
 423         bne-    2f\n\
 424         stdcx.  %4,0,%2\n\
 425         bne-    1b"
 426         "\n\
 427 2:"
 428         : "=&r" (prev), "+m" (*p)
 429         : "r" (p), "r" (old), "r" (new)
 430         : "cc", "memory");
 431
 432         return prev;
 433 }
 434 #endif
 435
 436 /* This function doesn't exist, so you'll get a linker error
 437    if something tries to do an invalid cmpxchg().  */
 438 extern void __cmpxchg_called_with_bad_pointer(void);
 439
 440 static __inline__ unsigned long
 441 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
 442           unsigned int size)
 443 {
 444         switch (size) {
 445         case 4:
 446                 return __cmpxchg_u32(ptr, old, new);
 447 #ifdef CONFIG_PPC64
 448         case 8:
 449                 return __cmpxchg_u64(ptr, old, new);
 450 #endif
 451         }
 452         __cmpxchg_called_with_bad_pointer();
 453         return old;
 454 }
 455
 456 static __inline__ unsigned long
 457 __cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
 458           unsigned int size)
 459 {
 460         switch (size) {
 461         case 4:
 462                 return __cmpxchg_u32_local(ptr, old, new);
 463 #ifdef CONFIG_PPC64
 464         case 8:
 465                 return __cmpxchg_u64_local(ptr, old, new);
 466 #endif
 467         }
 468         __cmpxchg_called_with_bad_pointer();
 469         return old;
 470 }
 471
 472 #define cmpxchg(ptr,o,n)                                                 \
 473   ({                                                                     \
 474      __typeof__(*(ptr)) _o_ = (o);                                       \
 475      __typeof__(*(ptr)) _n_ = (n);                                       \
 476      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 477                                     (unsigned long)_n_, sizeof(*(ptr))); \
 478   })
 479
 480
 481 #define cmpxchg_local(ptr,o,n)                                           \
 482   ({                                                                     \
 483      __typeof__(*(ptr)) _o_ = (o);                                       \
 484      __typeof__(*(ptr)) _n_ = (n);                                       \
 485      (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_,     \
 486                                     (unsigned long)_n_, sizeof(*(ptr))); \
 487   })
 488
 489 #ifdef CONFIG_PPC64
 490 /*
 491  * We handle most unaligned accesses in hardware. On the other hand
 492  * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 493  * powers of 2 writes until it reaches sufficient alignment).
 494  *
 495  * Based on this we disable the IP header alignment in network drivers.
 496  * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
 497  * cacheline alignment of buffers.
 498  */
 499 #define NET_IP_ALIGN    0
 500 #define NET_SKB_PAD     L1_CACHE_BYTES
 501 #endif
 502
 503 #define arch_align_stack(x) (x)
 504
 505 /* Used in very early kernel initialization. */
 506 extern unsigned long reloc_offset(void);
 507 extern unsigned long add_reloc_offset(unsigned long);
 508 extern void reloc_got2(unsigned long);
 509
 510 #define PTRRELOC(x)     ((typeof(x)) add_reloc_offset((unsigned long)(x)))
 511
 512 static inline void create_instruction(unsigned long addr, unsigned int instr)
 513 {
 514         unsigned int *p;
 515         p  = (unsigned int *)addr;
 516         *p = instr;
 517         asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p));
 518 }
 519
 520 /* Flags for create_branch:
 521  * "b"   == create_branch(addr, target, 0);
 522  * "ba"  == create_branch(addr, target, BRANCH_ABSOLUTE);
 523  * "bl"  == create_branch(addr, target, BRANCH_SET_LINK);
 524  * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
 525  */
 526 #define BRANCH_SET_LINK 0x1
 527 #define BRANCH_ABSOLUTE 0x2
 528
 529 static inline void create_branch(unsigned long addr,
 530                 unsigned long target, int flags)
 531 {
 532         unsigned int instruction;
 533
 534         if (! (flags & BRANCH_ABSOLUTE))
 535                 target = target - addr;
 536
 537         /* Mask out the flags and target, so they don't step on each other. */
 538         instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC);
 539
 540         create_instruction(addr, instruction);
 541 }
 542
 543 static inline void create_function_call(unsigned long addr, void * func)
 544 {
 545         unsigned long func_addr;
 546
 547 #ifdef CONFIG_PPC64
 548         /*
 549          * On PPC64 the function pointer actually points to the function's
 550          * descriptor. The first entry in the descriptor is the address
 551          * of the function text.
 552          */
 553         func_addr = *(unsigned long *)func;
 554 #else
 555         func_addr = (unsigned long)func;
 556 #endif
 557         create_branch(addr, func_addr, BRANCH_SET_LINK);
 558 }
 559
 560 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
 561 extern void account_system_vtime(struct task_struct *);
 562 #endif
 563
 564 #endif /* __KERNEL__ */
 565 #endif /* _ASM_POWERPC_SYSTEM_H */