include/asm-powerpc/ppc_asm.h

   1 /*
   2  * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
   3  */
   4 #ifndef _ASM_POWERPC_PPC_ASM_H
   5 #define _ASM_POWERPC_PPC_ASM_H
   6
   7 #include <linux/stringify.h>
   8 #include <asm/asm-compat.h>
   9
  10 #ifndef __ASSEMBLY__
  11 #error __FILE__ should only be used in assembler files
  12 #else
  13
  14 #define SZL                     (BITS_PER_LONG/8)
  15
  16 /*
  17  * Stuff for accurate CPU time accounting.
  18  * These macros handle transitions between user and system state
  19  * in exception entry and exit and accumulate time to the
  20  * user_time and system_time fields in the paca.
  21  */
  22
  23 #ifndef CONFIG_VIRT_CPU_ACCOUNTING
  24 #define ACCOUNT_CPU_USER_ENTRY(ra, rb)
  25 #define ACCOUNT_CPU_USER_EXIT(ra, rb)
  26 #else
  27 #define ACCOUNT_CPU_USER_ENTRY(ra, rb)                                  \
  28         beq     2f;                     /* if from kernel mode */       \
  29 BEGIN_FTR_SECTION;                                                      \
  30         mfspr   ra,SPRN_PURR;           /* get processor util. reg */   \
  31 END_FTR_SECTION_IFSET(CPU_FTR_PURR);                                    \
  32 BEGIN_FTR_SECTION;                                                      \
  33         MFTB(ra);                       /* or get TB if no PURR */      \
  34 END_FTR_SECTION_IFCLR(CPU_FTR_PURR);                                    \
  35         ld      rb,PACA_STARTPURR(r13);                                 \
  36         std     ra,PACA_STARTPURR(r13);                                 \
  37         subf    rb,rb,ra;               /* subtract start value */      \
  38         ld      ra,PACA_USER_TIME(r13);                                 \
  39         add     ra,ra,rb;               /* add on to user time */       \
  40         std     ra,PACA_USER_TIME(r13);                                 \
  41 2:
  42
  43 #define ACCOUNT_CPU_USER_EXIT(ra, rb)                                   \
  44 BEGIN_FTR_SECTION;                                                      \
  45         mfspr   ra,SPRN_PURR;           /* get processor util. reg */   \
  46 END_FTR_SECTION_IFSET(CPU_FTR_PURR);                                    \
  47 BEGIN_FTR_SECTION;                                                      \
  48         MFTB(ra);                       /* or get TB if no PURR */      \
  49 END_FTR_SECTION_IFCLR(CPU_FTR_PURR);                                    \
  50         ld      rb,PACA_STARTPURR(r13);                                 \
  51         std     ra,PACA_STARTPURR(r13);                                 \
  52         subf    rb,rb,ra;               /* subtract start value */      \
  53         ld      ra,PACA_SYSTEM_TIME(r13);                               \
  54         add     ra,ra,rb;               /* add on to user time */       \
  55         std     ra,PACA_SYSTEM_TIME(r13);
  56 #endif
  57
  58 /*
  59  * Macros for storing registers into and loading registers from
  60  * exception frames.
  61  */
  62 #ifdef __powerpc64__
  63 #define SAVE_GPR(n, base)       std     n,GPR0+8*(n)(base)
  64 #define REST_GPR(n, base)       ld      n,GPR0+8*(n)(base)
  65 #define SAVE_NVGPRS(base)       SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
  66 #define REST_NVGPRS(base)       REST_8GPRS(14, base); REST_10GPRS(22, base)
  67 #else
  68 #define SAVE_GPR(n, base)       stw     n,GPR0+4*(n)(base)
  69 #define REST_GPR(n, base)       lwz     n,GPR0+4*(n)(base)
  70 #define SAVE_NVGPRS(base)       SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
  71                                 SAVE_10GPRS(22, base)
  72 #define REST_NVGPRS(base)       REST_GPR(13, base); REST_8GPRS(14, base); \
  73                                 REST_10GPRS(22, base)
  74 #endif
  75
  76
  77 #define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
  78 #define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
  79 #define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
  80 #define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
  81 #define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
  82 #define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
  83 #define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
  84 #define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
  85
  86 #define SAVE_FPR(n, base)       stfd    n,THREAD_FPR0+8*(n)(base)
  87 #define SAVE_2FPRS(n, base)     SAVE_FPR(n, base); SAVE_FPR(n+1, base)
  88 #define SAVE_4FPRS(n, base)     SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
  89 #define SAVE_8FPRS(n, base)     SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
  90 #define SAVE_16FPRS(n, base)    SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
  91 #define SAVE_32FPRS(n, base)    SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
  92 #define REST_FPR(n, base)       lfd     n,THREAD_FPR0+8*(n)(base)
  93 #define REST_2FPRS(n, base)     REST_FPR(n, base); REST_FPR(n+1, base)
  94 #define REST_4FPRS(n, base)     REST_2FPRS(n, base); REST_2FPRS(n+2, base)
  95 #define REST_8FPRS(n, base)     REST_4FPRS(n, base); REST_4FPRS(n+4, base)
  96 #define REST_16FPRS(n, base)    REST_8FPRS(n, base); REST_8FPRS(n+8, base)
  97 #define REST_32FPRS(n, base)    REST_16FPRS(n, base); REST_16FPRS(n+16, base)
  98
  99 #define SAVE_VR(n,b,base)       li b,THREAD_VR0+(16*(n));  stvx n,b,base
 100 #define SAVE_2VRS(n,b,base)     SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
 101 #define SAVE_4VRS(n,b,base)     SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
 102 #define SAVE_8VRS(n,b,base)     SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
 103 #define SAVE_16VRS(n,b,base)    SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
 104 #define SAVE_32VRS(n,b,base)    SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
 105 #define REST_VR(n,b,base)       li b,THREAD_VR0+(16*(n)); lvx n,b,base
 106 #define REST_2VRS(n,b,base)     REST_VR(n,b,base); REST_VR(n+1,b,base)
 107 #define REST_4VRS(n,b,base)     REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
 108 #define REST_8VRS(n,b,base)     REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
 109 #define REST_16VRS(n,b,base)    REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
 110 #define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
 111
 112 #define SAVE_EVR(n,s,base)      evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
 113 #define SAVE_2EVRS(n,s,base)    SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
 114 #define SAVE_4EVRS(n,s,base)    SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
 115 #define SAVE_8EVRS(n,s,base)    SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
 116 #define SAVE_16EVRS(n,s,base)   SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
 117 #define SAVE_32EVRS(n,s,base)   SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
 118 #define REST_EVR(n,s,base)      lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
 119 #define REST_2EVRS(n,s,base)    REST_EVR(n,s,base); REST_EVR(n+1,s,base)
 120 #define REST_4EVRS(n,s,base)    REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
 121 #define REST_8EVRS(n,s,base)    REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
 122 #define REST_16EVRS(n,s,base)   REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
 123 #define REST_32EVRS(n,s,base)   REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
 124
 125 /* Macros to adjust thread priority for hardware multithreading */
 126 #define HMT_VERY_LOW    or      31,31,31        # very low priority
 127 #define HMT_LOW         or      1,1,1
 128 #define HMT_MEDIUM_LOW  or      6,6,6           # medium low priority
 129 #define HMT_MEDIUM      or      2,2,2
 130 #define HMT_MEDIUM_HIGH or      5,5,5           # medium high priority
 131 #define HMT_HIGH        or      3,3,3
 132
 133 /* handle instructions that older assemblers may not know */
 134 #define RFCI            .long 0x4c000066        /* rfci instruction */
 135 #define RFDI            .long 0x4c00004e        /* rfdi instruction */
 136 #define RFMCI           .long 0x4c00004c        /* rfmci instruction */
 137
 138 #ifdef __KERNEL__
 139 #ifdef CONFIG_PPC64
 140
 141 #define XGLUE(a,b) a##b
 142 #define GLUE(a,b) XGLUE(a,b)
 143
 144 #define _GLOBAL(name) \
 145         .section ".text"; \
 146         .align 2 ; \
 147         .globl name; \
 148         .globl GLUE(.,name); \
 149         .section ".opd","aw"; \
 150 name: \
 151         .quad GLUE(.,name); \
 152         .quad .TOC.@tocbase; \
 153         .quad 0; \
 154         .previous; \
 155         .type GLUE(.,name),@function; \
 156 GLUE(.,name):
 157
 158 #define _KPROBE(name) \
 159         .section ".kprobes.text","a"; \
 160         .align 2 ; \
 161         .globl name; \
 162         .globl GLUE(.,name); \
 163         .section ".opd","aw"; \
 164 name: \
 165         .quad GLUE(.,name); \
 166         .quad .TOC.@tocbase; \
 167         .quad 0; \
 168         .previous; \
 169         .type GLUE(.,name),@function; \
 170 GLUE(.,name):
 171
 172 #define _STATIC(name) \
 173         .section ".text"; \
 174         .align 2 ; \
 175         .section ".opd","aw"; \
 176 name: \
 177         .quad GLUE(.,name); \
 178         .quad .TOC.@tocbase; \
 179         .quad 0; \
 180         .previous; \
 181         .type GLUE(.,name),@function; \
 182 GLUE(.,name):
 183
 184 #else /* 32-bit */
 185
 186 #define _GLOBAL(n)      \
 187         .text;          \
 188         .stabs __stringify(n:F-1),N_FUN,0,0,n;\
 189         .globl n;       \
 190 n:
 191
 192 #define _KPROBE(n)      \
 193         .section ".kprobes.text","a";   \
 194         .globl  n;      \
 195 n:
 196
 197 #endif
 198
 199 /*
 200  * LOAD_REG_IMMEDIATE(rn, expr)
 201  *   Loads the value of the constant expression 'expr' into register 'rn'
 202  *   using immediate instructions only.  Use this when it's important not
 203  *   to reference other data (i.e. on ppc64 when the TOC pointer is not
 204  *   valid).
 205  *
 206  * LOAD_REG_ADDR(rn, name)
 207  *   Loads the address of label 'name' into register 'rn'.  Use this when
 208  *   you don't particularly need immediate instructions only, but you need
 209  *   the whole address in one register (e.g. it's a structure address and
 210  *   you want to access various offsets within it).  On ppc32 this is
 211  *   identical to LOAD_REG_IMMEDIATE.
 212  *
 213  * LOAD_REG_ADDRBASE(rn, name)
 214  * ADDROFF(name)
 215  *   LOAD_REG_ADDRBASE loads part of the address of label 'name' into
 216  *   register 'rn'.  ADDROFF(name) returns the remainder of the address as
 217  *   a constant expression.  ADDROFF(name) is a signed expression < 16 bits
 218  *   in size, so is suitable for use directly as an offset in load and store
 219  *   instructions.  Use this when loading/storing a single word or less as:
 220  *      LOAD_REG_ADDRBASE(rX, name)
 221  *      ld      rY,ADDROFF(name)(rX)
 222  */
 223 #ifdef __powerpc64__
 224 #define LOAD_REG_IMMEDIATE(reg,expr)            \
 225         lis     (reg),(expr)@highest;           \
 226         ori     (reg),(reg),(expr)@higher;      \
 227         rldicr  (reg),(reg),32,31;              \
 228         oris    (reg),(reg),(expr)@h;           \
 229         ori     (reg),(reg),(expr)@l;
 230
 231 #define LOAD_REG_ADDR(reg,name)                 \
 232         ld      (reg),name@got(r2)
 233
 234 #define LOAD_REG_ADDRBASE(reg,name)     LOAD_REG_ADDR(reg,name)
 235 #define ADDROFF(name)                   0
 236
 237 /* offsets for stack frame layout */
 238 #define LRSAVE  16
 239
 240 #else /* 32-bit */
 241
 242 #define LOAD_REG_IMMEDIATE(reg,expr)            \
 243         lis     (reg),(expr)@ha;                \
 244         addi    (reg),(reg),(expr)@l;
 245
 246 #define LOAD_REG_ADDR(reg,name)         LOAD_REG_IMMEDIATE(reg, name)
 247
 248 #define LOAD_REG_ADDRBASE(reg, name)    lis     (reg),name@ha
 249 #define ADDROFF(name)                   name@l
 250
 251 /* offsets for stack frame layout */
 252 #define LRSAVE  4
 253
 254 #endif
 255
 256 /* various errata or part fixups */
 257 #ifdef CONFIG_PPC601_SYNC_FIX
 258 #define SYNC                            \
 259 BEGIN_FTR_SECTION                       \
 260         sync;                           \
 261         isync;                          \
 262 END_FTR_SECTION_IFSET(CPU_FTR_601)
 263 #define SYNC_601                        \
 264 BEGIN_FTR_SECTION                       \
 265         sync;                           \
 266 END_FTR_SECTION_IFSET(CPU_FTR_601)
 267 #define ISYNC_601                       \
 268 BEGIN_FTR_SECTION                       \
 269         isync;                          \
 270 END_FTR_SECTION_IFSET(CPU_FTR_601)
 271 #else
 272 #define SYNC
 273 #define SYNC_601
 274 #define ISYNC_601
 275 #endif
 276
 277 #ifdef CONFIG_PPC_CELL
 278 #define MFTB(dest)                      \
 279 90:     mftb  dest;                     \
 280 BEGIN_FTR_SECTION_NESTED(96);           \
 281         cmpwi dest,0;                   \
 282         beq-  90b;                      \
 283 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
 284 #else
 285 #define MFTB(dest)                      mftb dest
 286 #endif
 287
 288 #ifndef CONFIG_SMP
 289 #define TLBSYNC
 290 #else /* CONFIG_SMP */
 291 /* tlbsync is not implemented on 601 */
 292 #define TLBSYNC                         \
 293 BEGIN_FTR_SECTION                       \
 294         tlbsync;                        \
 295         sync;                           \
 296 END_FTR_SECTION_IFCLR(CPU_FTR_601)
 297 #endif
 298
 299
 300 /*
 301  * This instruction is not implemented on the PPC 603 or 601; however, on
 302  * the 403GCX and 405GP tlbia IS defined and tlbie is not.
 303  * All of these instructions exist in the 8xx, they have magical powers,
 304  * and they must be used.
 305  */
 306
 307 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
 308 #define tlbia                                   \
 309         li      r4,1024;                        \
 310         mtctr   r4;                             \
 311         lis     r4,KERNELBASE@h;                \
 312 0:      tlbie   r4;                             \
 313         addi    r4,r4,0x1000;                   \
 314         bdnz    0b
 315 #endif
 316
 317
 318 #ifdef CONFIG_IBM440EP_ERR42
 319 #define PPC440EP_ERR42 isync
 320 #else
 321 #define PPC440EP_ERR42
 322 #endif
 323
 324
 325 #if defined(CONFIG_BOOKE)
 326 #define toreal(rd)
 327 #define fromreal(rd)
 328
 329 #define tophys(rd,rs)                           \
 330         addis   rd,rs,0
 331
 332 #define tovirt(rd,rs)                           \
 333         addis   rd,rs,0
 334
 335 #elif defined(CONFIG_PPC64)
 336 #define toreal(rd)              /* we can access c000... in real mode */
 337 #define fromreal(rd)
 338
 339 #define tophys(rd,rs)                           \
 340         clrldi  rd,rs,2
 341
 342 #define tovirt(rd,rs)                           \
 343         rotldi  rd,rs,16;                       \
 344         ori     rd,rd,((KERNELBASE>>48)&0xFFFF);\
 345         rotldi  rd,rd,48
 346 #else
 347 /*
 348  * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
 349  * physical base address of RAM at compile time.
 350  */
 351 #define toreal(rd)      tophys(rd,rd)
 352 #define fromreal(rd)    tovirt(rd,rd)
 353
 354 #define tophys(rd,rs)                           \
 355 0:      addis   rd,rs,-KERNELBASE@h;            \
 356         .section ".vtop_fixup","aw";            \
 357         .align  1;                              \
 358         .long   0b;                             \
 359         .previous
 360
 361 #define tovirt(rd,rs)                           \
 362 0:      addis   rd,rs,KERNELBASE@h;             \
 363         .section ".ptov_fixup","aw";            \
 364         .align  1;                              \
 365         .long   0b;                             \
 366         .previous
 367 #endif
 368
 369 #ifdef CONFIG_PPC64
 370 #define RFI             rfid
 371 #define MTMSRD(r)       mtmsrd  r
 372
 373 #else
 374 #define FIX_SRR1(ra, rb)
 375 #ifndef CONFIG_40x
 376 #define RFI             rfi
 377 #else
 378 #define RFI             rfi; b .        /* Prevent prefetch past rfi */
 379 #endif
 380 #define MTMSRD(r)       mtmsr   r
 381 #define CLR_TOP32(r)
 382 #endif
 383
 384 #endif /* __KERNEL__ */
 385
 386 /* The boring bits... */
 387
 388 /* Condition Register Bit Fields */
 389
 390 #define cr0     0
 391 #define cr1     1
 392 #define cr2     2
 393 #define cr3     3
 394 #define cr4     4
 395 #define cr5     5
 396 #define cr6     6
 397 #define cr7     7
 398
 399
 400 /* General Purpose Registers (GPRs) */
 401
 402 #define r0      0
 403 #define r1      1
 404 #define r2      2
 405 #define r3      3
 406 #define r4      4
 407 #define r5      5
 408 #define r6      6
 409 #define r7      7
 410 #define r8      8
 411 #define r9      9
 412 #define r10     10
 413 #define r11     11
 414 #define r12     12
 415 #define r13     13
 416 #define r14     14
 417 #define r15     15
 418 #define r16     16
 419 #define r17     17
 420 #define r18     18
 421 #define r19     19
 422 #define r20     20
 423 #define r21     21
 424 #define r22     22
 425 #define r23     23
 426 #define r24     24
 427 #define r25     25
 428 #define r26     26
 429 #define r27     27
 430 #define r28     28
 431 #define r29     29
 432 #define r30     30
 433 #define r31     31
 434
 435
 436 /* Floating Point Registers (FPRs) */
 437
 438 #define fr0     0
 439 #define fr1     1
 440 #define fr2     2
 441 #define fr3     3
 442 #define fr4     4
 443 #define fr5     5
 444 #define fr6     6
 445 #define fr7     7
 446 #define fr8     8
 447 #define fr9     9
 448 #define fr10    10
 449 #define fr11    11
 450 #define fr12    12
 451 #define fr13    13
 452 #define fr14    14
 453 #define fr15    15
 454 #define fr16    16
 455 #define fr17    17
 456 #define fr18    18
 457 #define fr19    19
 458 #define fr20    20
 459 #define fr21    21
 460 #define fr22    22
 461 #define fr23    23
 462 #define fr24    24
 463 #define fr25    25
 464 #define fr26    26
 465 #define fr27    27
 466 #define fr28    28
 467 #define fr29    29
 468 #define fr30    30
 469 #define fr31    31
 470
 471 /* AltiVec Registers (VPRs) */
 472
 473 #define vr0     0
 474 #define vr1     1
 475 #define vr2     2
 476 #define vr3     3
 477 #define vr4     4
 478 #define vr5     5
 479 #define vr6     6
 480 #define vr7     7
 481 #define vr8     8
 482 #define vr9     9
 483 #define vr10    10
 484 #define vr11    11
 485 #define vr12    12
 486 #define vr13    13
 487 #define vr14    14
 488 #define vr15    15
 489 #define vr16    16
 490 #define vr17    17
 491 #define vr18    18
 492 #define vr19    19
 493 #define vr20    20
 494 #define vr21    21
 495 #define vr22    22
 496 #define vr23    23
 497 #define vr24    24
 498 #define vr25    25
 499 #define vr26    26
 500 #define vr27    27
 501 #define vr28    28
 502 #define vr29    29
 503 #define vr30    30
 504 #define vr31    31
 505
 506 /* SPE Registers (EVPRs) */
 507
 508 #define evr0    0
 509 #define evr1    1
 510 #define evr2    2
 511 #define evr3    3
 512 #define evr4    4
 513 #define evr5    5
 514 #define evr6    6
 515 #define evr7    7
 516 #define evr8    8
 517 #define evr9    9
 518 #define evr10   10
 519 #define evr11   11
 520 #define evr12   12
 521 #define evr13   13
 522 #define evr14   14
 523 #define evr15   15
 524 #define evr16   16
 525 #define evr17   17
 526 #define evr18   18
 527 #define evr19   19
 528 #define evr20   20
 529 #define evr21   21
 530 #define evr22   22
 531 #define evr23   23
 532 #define evr24   24
 533 #define evr25   25
 534 #define evr26   26
 535 #define evr27   27
 536 #define evr28   28
 537 #define evr29   29
 538 #define evr30   30
 539 #define evr31   31
 540
 541 /* some stab codes */
 542 #define N_FUN   36
 543 #define N_RSYM  64
 544 #define N_SLINE 68
 545 #define N_SO    100
 546
 547 #endif /*  __ASSEMBLY__ */
 548
 549 #endif /* _ASM_POWERPC_PPC_ASM_H */