drivers/pci/hotplug/ibmphp_hpc.c

   1 /*
   2  * IBM Hot Plug Controller Driver
   3  *
   4  * Written By: Jyoti Shah, IBM Corporation
   5  *
   6  * Copyright (C) 2001-2003 IBM Corp.
   7  *
   8  * All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or (at
  13  * your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  18  * NON INFRINGEMENT.  See the GNU General Public License for more
  19  * details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  *
  25  * Send feedback to <gregkh@us.ibm.com>
  26  *                  <jshah@us.ibm.com>
  27  *
  28  */
  29
  30 #include <linux/wait.h>
  31 #include <linux/time.h>
  32 #include <linux/delay.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/init.h>
  36 #include <linux/mutex.h>
  37
  38 #include "ibmphp.h"
  39
  40 static int to_debug = 0;
  41 #define debug_polling(fmt, arg...)      do { if (to_debug) debug (fmt, arg); } while (0)
  42
  43 //----------------------------------------------------------------------------
  44 // timeout values
  45 //----------------------------------------------------------------------------
  46 #define CMD_COMPLETE_TOUT_SEC   60      // give HPC 60 sec to finish cmd
  47 #define HPC_CTLR_WORKING_TOUT   60      // give HPC 60 sec to finish cmd
  48 #define HPC_GETACCESS_TIMEOUT   60      // seconds
  49 #define POLL_INTERVAL_SEC       2       // poll HPC every 2 seconds
  50 #define POLL_LATCH_CNT          5       // poll latch 5 times, then poll slots
  51
  52 //----------------------------------------------------------------------------
  53 // Winnipeg Architected Register Offsets
  54 //----------------------------------------------------------------------------
  55 #define WPG_I2CMBUFL_OFFSET     0x08    // I2C Message Buffer Low
  56 #define WPG_I2CMOSUP_OFFSET     0x10    // I2C Master Operation Setup Reg
  57 #define WPG_I2CMCNTL_OFFSET     0x20    // I2C Master Control Register
  58 #define WPG_I2CPARM_OFFSET      0x40    // I2C Parameter Register
  59 #define WPG_I2CSTAT_OFFSET      0x70    // I2C Status Register
  60
  61 //----------------------------------------------------------------------------
  62 // Winnipeg Store Type commands (Add this commands to the register offset)
  63 //----------------------------------------------------------------------------
  64 #define WPG_I2C_AND             0x1000  // I2C AND operation
  65 #define WPG_I2C_OR              0x2000  // I2C OR operation
  66
  67 //----------------------------------------------------------------------------
  68 // Command set for I2C Master Operation Setup Register
  69 //----------------------------------------------------------------------------
  70 #define WPG_READATADDR_MASK     0x00010000      // read,bytes,I2C shifted,index
  71 #define WPG_WRITEATADDR_MASK    0x40010000      // write,bytes,I2C shifted,index
  72 #define WPG_READDIRECT_MASK     0x10010000
  73 #define WPG_WRITEDIRECT_MASK    0x60010000
  74
  75
  76 //----------------------------------------------------------------------------
  77 // bit masks for I2C Master Control Register
  78 //----------------------------------------------------------------------------
  79 #define WPG_I2CMCNTL_STARTOP_MASK       0x00000002      // Start the Operation
  80
  81 //----------------------------------------------------------------------------
  82 //
  83 //----------------------------------------------------------------------------
  84 #define WPG_I2C_IOREMAP_SIZE    0x2044  // size of linear address interval
  85
  86 //----------------------------------------------------------------------------
  87 // command index
  88 //----------------------------------------------------------------------------
  89 #define WPG_1ST_SLOT_INDEX      0x01    // index - 1st slot for ctlr
  90 #define WPG_CTLR_INDEX          0x0F    // index - ctlr
  91 #define WPG_1ST_EXTSLOT_INDEX   0x10    // index - 1st ext slot for ctlr
  92 #define WPG_1ST_BUS_INDEX       0x1F    // index - 1st bus for ctlr
  93
  94 //----------------------------------------------------------------------------
  95 // macro utilities
  96 //----------------------------------------------------------------------------
  97 // if bits 20,22,25,26,27,29,30 are OFF return 1
  98 #define HPC_I2CSTATUS_CHECK(s)  ((u8)((s & 0x00000A76) ? 0 : 1))
  99
 100 //----------------------------------------------------------------------------
 101 // global variables
 102 //----------------------------------------------------------------------------
 103 static int ibmphp_shutdown;
 104 static int tid_poll;
 105 static struct mutex sem_hpcaccess;      // lock access to HPC
 106 static struct semaphore semOperations;  // lock all operations and
 107                                         // access to data structures
 108 static struct semaphore sem_exit;       // make sure polling thread goes away
 109 //----------------------------------------------------------------------------
 110 // local function prototypes
 111 //----------------------------------------------------------------------------
 112 static u8 i2c_ctrl_read (struct controller *, void __iomem *, u8);
 113 static u8 i2c_ctrl_write (struct controller *, void __iomem *, u8, u8);
 114 static u8 hpc_writecmdtoindex (u8, u8);
 115 static u8 hpc_readcmdtoindex (u8, u8);
 116 static void get_hpc_access (void);
 117 static void free_hpc_access (void);
 118 static void poll_hpc (void);
 119 static int process_changeinstatus (struct slot *, struct slot *);
 120 static int process_changeinlatch (u8, u8, struct controller *);
 121 static int hpc_poll_thread (void *);
 122 static int hpc_wait_ctlr_notworking (int, struct controller *, void __iomem *, u8 *);
 123 //----------------------------------------------------------------------------
 124
 125
 126 /*----------------------------------------------------------------------
 127 * Name:    ibmphp_hpc_initvars
 128 *
 129 * Action:  initialize semaphores and variables
 130 *---------------------------------------------------------------------*/
 131 void __init ibmphp_hpc_initvars (void)
 132 {
 133         debug ("%s - Entry\n", __FUNCTION__);
 134
 135         mutex_init(&sem_hpcaccess);
 136         init_MUTEX (&semOperations);
 137         init_MUTEX_LOCKED (&sem_exit);
 138         to_debug = 0;
 139         ibmphp_shutdown = 0;
 140         tid_poll = 0;
 141
 142         debug ("%s - Exit\n", __FUNCTION__);
 143 }
 144
 145 /*----------------------------------------------------------------------
 146 * Name:    i2c_ctrl_read
 147 *
 148 * Action:  read from HPC over I2C
 149 *
 150 *---------------------------------------------------------------------*/
 151 static u8 i2c_ctrl_read (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index)
 152 {
 153         u8 status;
 154         int i;
 155         void __iomem *wpg_addr; // base addr + offset
 156         unsigned long wpg_data; // data to/from WPG LOHI format
 157         unsigned long ultemp;
 158         unsigned long data;     // actual data HILO format
 159
 160         debug_polling ("%s - Entry WPGBbar[%p] index[%x] \n", __FUNCTION__, WPGBbar, index);
 161
 162         //--------------------------------------------------------------------
 163         // READ - step 1
 164         // read at address, byte length, I2C address (shifted), index
 165         // or read direct, byte length, index
 166         if (ctlr_ptr->ctlr_type == 0x02) {
 167                 data = WPG_READATADDR_MASK;
 168                 // fill in I2C address
 169                 ultemp = (unsigned long)ctlr_ptr->u.wpeg_ctlr.i2c_addr;
 170                 ultemp = ultemp >> 1;
 171                 data |= (ultemp << 8);
 172
 173                 // fill in index
 174                 data |= (unsigned long)index;
 175         } else if (ctlr_ptr->ctlr_type == 0x04) {
 176                 data = WPG_READDIRECT_MASK;
 177
 178                 // fill in index
 179                 ultemp = (unsigned long)index;
 180                 ultemp = ultemp << 8;
 181                 data |= ultemp;
 182         } else {
 183                 err ("this controller type is not supported \n");
 184                 return HPC_ERROR;
 185         }
 186
 187         wpg_data = swab32 (data);       // swap data before writing
 188         wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET;
 189         writel (wpg_data, wpg_addr);
 190
 191         //--------------------------------------------------------------------
 192         // READ - step 2 : clear the message buffer
 193         data = 0x00000000;
 194         wpg_data = swab32 (data);
 195         wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET;
 196         writel (wpg_data, wpg_addr);
 197
 198         //--------------------------------------------------------------------
 199         // READ - step 3 : issue start operation, I2C master control bit 30:ON
 200         //                 2020 : [20] OR operation at [20] offset 0x20
 201         data = WPG_I2CMCNTL_STARTOP_MASK;
 202         wpg_data = swab32 (data);
 203         wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR;
 204         writel (wpg_data, wpg_addr);
 205
 206         //--------------------------------------------------------------------
 207         // READ - step 4 : wait until start operation bit clears
 208         i = CMD_COMPLETE_TOUT_SEC;
 209         while (i) {
 210                 msleep(10);
 211                 wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET;
 212                 wpg_data = readl (wpg_addr);
 213                 data = swab32 (wpg_data);
 214                 if (!(data & WPG_I2CMCNTL_STARTOP_MASK))
 215                         break;
 216                 i--;
 217         }
 218         if (i == 0) {
 219                 debug ("%s - Error : WPG timeout\n", __FUNCTION__);
 220                 return HPC_ERROR;
 221         }
 222         //--------------------------------------------------------------------
 223         // READ - step 5 : read I2C status register
 224         i = CMD_COMPLETE_TOUT_SEC;
 225         while (i) {
 226                 msleep(10);
 227                 wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET;
 228                 wpg_data = readl (wpg_addr);
 229                 data = swab32 (wpg_data);
 230                 if (HPC_I2CSTATUS_CHECK (data))
 231                         break;
 232                 i--;
 233         }
 234         if (i == 0) {
 235                 debug ("ctrl_read - Exit Error:I2C timeout\n");
 236                 return HPC_ERROR;
 237         }
 238
 239         //--------------------------------------------------------------------
 240         // READ - step 6 : get DATA
 241         wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET;
 242         wpg_data = readl (wpg_addr);
 243         data = swab32 (wpg_data);
 244
 245         status = (u8) data;
 246
 247         debug_polling ("%s - Exit index[%x] status[%x]\n", __FUNCTION__, index, status);
 248
 249         return (status);
 250 }
 251
 252 /*----------------------------------------------------------------------
 253 * Name:    i2c_ctrl_write
 254 *
 255 * Action:  write to HPC over I2C
 256 *
 257 * Return   0 or error codes
 258 *---------------------------------------------------------------------*/
 259 static u8 i2c_ctrl_write (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index, u8 cmd)
 260 {
 261         u8 rc;
 262         void __iomem *wpg_addr; // base addr + offset
 263         unsigned long wpg_data; // data to/from WPG LOHI format
 264         unsigned long ultemp;
 265         unsigned long data;     // actual data HILO format
 266         int i;
 267
 268         debug_polling ("%s - Entry WPGBbar[%p] index[%x] cmd[%x]\n", __FUNCTION__, WPGBbar, index, cmd);
 269
 270         rc = 0;
 271         //--------------------------------------------------------------------
 272         // WRITE - step 1
 273         // write at address, byte length, I2C address (shifted), index
 274         // or write direct, byte length, index
 275         data = 0x00000000;
 276
 277         if (ctlr_ptr->ctlr_type == 0x02) {
 278                 data = WPG_WRITEATADDR_MASK;
 279                 // fill in I2C address
 280                 ultemp = (unsigned long)ctlr_ptr->u.wpeg_ctlr.i2c_addr;
 281                 ultemp = ultemp >> 1;
 282                 data |= (ultemp << 8);
 283
 284                 // fill in index
 285                 data |= (unsigned long)index;
 286         } else if (ctlr_ptr->ctlr_type == 0x04) {
 287                 data = WPG_WRITEDIRECT_MASK;
 288
 289                 // fill in index
 290                 ultemp = (unsigned long)index;
 291                 ultemp = ultemp << 8;
 292                 data |= ultemp;
 293         } else {
 294                 err ("this controller type is not supported \n");
 295                 return HPC_ERROR;
 296         }
 297
 298         wpg_data = swab32 (data);       // swap data before writing
 299         wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET;
 300         writel (wpg_data, wpg_addr);
 301
 302         //--------------------------------------------------------------------
 303         // WRITE - step 2 : clear the message buffer
 304         data = 0x00000000 | (unsigned long)cmd;
 305         wpg_data = swab32 (data);
 306         wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET;
 307         writel (wpg_data, wpg_addr);
 308
 309         //--------------------------------------------------------------------
 310         // WRITE - step 3 : issue start operation,I2C master control bit 30:ON
 311         //                 2020 : [20] OR operation at [20] offset 0x20
 312         data = WPG_I2CMCNTL_STARTOP_MASK;
 313         wpg_data = swab32 (data);
 314         wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR;
 315         writel (wpg_data, wpg_addr);
 316
 317         //--------------------------------------------------------------------
 318         // WRITE - step 4 : wait until start operation bit clears
 319         i = CMD_COMPLETE_TOUT_SEC;
 320         while (i) {
 321                 msleep(10);
 322                 wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET;
 323                 wpg_data = readl (wpg_addr);
 324                 data = swab32 (wpg_data);
 325                 if (!(data & WPG_I2CMCNTL_STARTOP_MASK))
 326                         break;
 327                 i--;
 328         }
 329         if (i == 0) {
 330                 debug ("%s - Exit Error:WPG timeout\n", __FUNCTION__);
 331                 rc = HPC_ERROR;
 332         }
 333
 334         //--------------------------------------------------------------------
 335         // WRITE - step 5 : read I2C status register
 336         i = CMD_COMPLETE_TOUT_SEC;
 337         while (i) {
 338                 msleep(10);
 339                 wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET;
 340                 wpg_data = readl (wpg_addr);
 341                 data = swab32 (wpg_data);
 342                 if (HPC_I2CSTATUS_CHECK (data))
 343                         break;
 344                 i--;
 345         }
 346         if (i == 0) {
 347                 debug ("ctrl_read - Error : I2C timeout\n");
 348                 rc = HPC_ERROR;
 349         }
 350
 351         debug_polling ("%s Exit rc[%x]\n", __FUNCTION__, rc);
 352         return (rc);
 353 }
 354
 355 //------------------------------------------------------------
 356 //  Read from ISA type HPC
 357 //------------------------------------------------------------
 358 static u8 isa_ctrl_read (struct controller *ctlr_ptr, u8 offset)
 359 {
 360         u16 start_address;
 361         u16 end_address;
 362         u8 data;
 363
 364         start_address = ctlr_ptr->u.isa_ctlr.io_start;
 365         end_address = ctlr_ptr->u.isa_ctlr.io_end;
 366         data = inb (start_address + offset);
 367         return data;
 368 }
 369
 370 //--------------------------------------------------------------
 371 // Write to ISA type HPC
 372 //--------------------------------------------------------------
 373 static void isa_ctrl_write (struct controller *ctlr_ptr, u8 offset, u8 data)
 374 {
 375         u16 start_address;
 376         u16 port_address;
 377
 378         start_address = ctlr_ptr->u.isa_ctlr.io_start;
 379         port_address = start_address + (u16) offset;
 380         outb (data, port_address);
 381 }
 382
 383 static u8 pci_ctrl_read (struct controller *ctrl, u8 offset)
 384 {
 385         u8 data = 0x00;
 386         debug ("inside pci_ctrl_read\n");
 387         if (ctrl->ctrl_dev)
 388                 pci_read_config_byte (ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, &data);
 389         return data;
 390 }
 391
 392 static u8 pci_ctrl_write (struct controller *ctrl, u8 offset, u8 data)
 393 {
 394         u8 rc = -ENODEV;
 395         debug ("inside pci_ctrl_write\n");
 396         if (ctrl->ctrl_dev) {
 397                 pci_write_config_byte (ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, data);
 398                 rc = 0;
 399         }
 400         return rc;
 401 }
 402
 403 static u8 ctrl_read (struct controller *ctlr, void __iomem *base, u8 offset)
 404 {
 405         u8 rc;
 406         switch (ctlr->ctlr_type) {
 407         case 0:
 408                 rc = isa_ctrl_read (ctlr, offset);
 409                 break;
 410         case 1:
 411                 rc = pci_ctrl_read (ctlr, offset);
 412                 break;
 413         case 2:
 414         case 4:
 415                 rc = i2c_ctrl_read (ctlr, base, offset);
 416                 break;
 417         default:
 418                 return -ENODEV;
 419         }
 420         return rc;
 421 }
 422
 423 static u8 ctrl_write (struct controller *ctlr, void __iomem *base, u8 offset, u8 data)
 424 {
 425         u8 rc = 0;
 426         switch (ctlr->ctlr_type) {
 427         case 0:
 428                 isa_ctrl_write(ctlr, offset, data);
 429                 break;
 430         case 1:
 431                 rc = pci_ctrl_write (ctlr, offset, data);
 432                 break;
 433         case 2:
 434         case 4:
 435                 rc = i2c_ctrl_write(ctlr, base, offset, data);
 436                 break;
 437         default:
 438                 return -ENODEV;
 439         }
 440         return rc;
 441 }
 442 /*----------------------------------------------------------------------
 443 * Name:    hpc_writecmdtoindex()
 444 *
 445 * Action:  convert a write command to proper index within a controller
 446 *
 447 * Return   index, HPC_ERROR
 448 *---------------------------------------------------------------------*/
 449 static u8 hpc_writecmdtoindex (u8 cmd, u8 index)
 450 {
 451         u8 rc;
 452
 453         switch (cmd) {
 454         case HPC_CTLR_ENABLEIRQ:        // 0x00.N.15
 455         case HPC_CTLR_CLEARIRQ: // 0x06.N.15
 456         case HPC_CTLR_RESET:    // 0x07.N.15
 457         case HPC_CTLR_IRQSTEER: // 0x08.N.15
 458         case HPC_CTLR_DISABLEIRQ:       // 0x01.N.15
 459         case HPC_ALLSLOT_ON:    // 0x11.N.15
 460         case HPC_ALLSLOT_OFF:   // 0x12.N.15
 461                 rc = 0x0F;
 462                 break;
 463
 464         case HPC_SLOT_OFF:      // 0x02.Y.0-14
 465         case HPC_SLOT_ON:       // 0x03.Y.0-14
 466         case HPC_SLOT_ATTNOFF:  // 0x04.N.0-14
 467         case HPC_SLOT_ATTNON:   // 0x05.N.0-14
 468         case HPC_SLOT_BLINKLED: // 0x13.N.0-14
 469                 rc = index;
 470                 break;
 471
 472         case HPC_BUS_33CONVMODE:
 473         case HPC_BUS_66CONVMODE:
 474         case HPC_BUS_66PCIXMODE:
 475         case HPC_BUS_100PCIXMODE:
 476         case HPC_BUS_133PCIXMODE:
 477                 rc = index + WPG_1ST_BUS_INDEX - 1;
 478                 break;
 479
 480         default:
 481                 err ("hpc_writecmdtoindex - Error invalid cmd[%x]\n", cmd);
 482                 rc = HPC_ERROR;
 483         }
 484
 485         return rc;
 486 }
 487
 488 /*----------------------------------------------------------------------
 489 * Name:    hpc_readcmdtoindex()
 490 *
 491 * Action:  convert a read command to proper index within a controller
 492 *
 493 * Return   index, HPC_ERROR
 494 *---------------------------------------------------------------------*/
 495 static u8 hpc_readcmdtoindex (u8 cmd, u8 index)
 496 {
 497         u8 rc;
 498
 499         switch (cmd) {
 500         case READ_CTLRSTATUS:
 501                 rc = 0x0F;
 502                 break;
 503         case READ_SLOTSTATUS:
 504         case READ_ALLSTAT:
 505                 rc = index;
 506                 break;
 507         case READ_EXTSLOTSTATUS:
 508                 rc = index + WPG_1ST_EXTSLOT_INDEX;
 509                 break;
 510         case READ_BUSSTATUS:
 511                 rc = index + WPG_1ST_BUS_INDEX - 1;
 512                 break;
 513         case READ_SLOTLATCHLOWREG:
 514                 rc = 0x28;
 515                 break;
 516         case READ_REVLEVEL:
 517                 rc = 0x25;
 518                 break;
 519         case READ_HPCOPTIONS:
 520                 rc = 0x27;
 521                 break;
 522         default:
 523                 rc = HPC_ERROR;
 524         }
 525         return rc;
 526 }
 527
 528 /*----------------------------------------------------------------------
 529 * Name:    HPCreadslot()
 530 *
 531 * Action:  issue a READ command to HPC
 532 *
 533 * Input:   pslot   - cannot be NULL for READ_ALLSTAT
 534 *          pstatus - can be NULL for READ_ALLSTAT
 535 *
 536 * Return   0 or error codes
 537 *---------------------------------------------------------------------*/
 538 int ibmphp_hpc_readslot (struct slot * pslot, u8 cmd, u8 * pstatus)
 539 {
 540         void __iomem *wpg_bbar = NULL;
 541         struct controller *ctlr_ptr;
 542         struct list_head *pslotlist;
 543         u8 index, status;
 544         int rc = 0;
 545         int busindex;
 546
 547         debug_polling ("%s - Entry pslot[%p] cmd[%x] pstatus[%p]\n", __FUNCTION__, pslot, cmd, pstatus);
 548
 549         if ((pslot == NULL)
 550             || ((pstatus == NULL) && (cmd != READ_ALLSTAT) && (cmd != READ_BUSSTATUS))) {
 551                 rc = -EINVAL;
 552                 err ("%s - Error invalid pointer, rc[%d]\n", __FUNCTION__, rc);
 553                 return rc;
 554         }
 555
 556         if (cmd == READ_BUSSTATUS) {
 557                 busindex = ibmphp_get_bus_index (pslot->bus);
 558                 if (busindex < 0) {
 559                         rc = -EINVAL;
 560                         err ("%s - Exit Error:invalid bus, rc[%d]\n", __FUNCTION__, rc);
 561                         return rc;
 562                 } else
 563                         index = (u8) busindex;
 564         } else
 565                 index = pslot->ctlr_index;
 566
 567         index = hpc_readcmdtoindex (cmd, index);
 568
 569         if (index == HPC_ERROR) {
 570                 rc = -EINVAL;
 571                 err ("%s - Exit Error:invalid index, rc[%d]\n", __FUNCTION__, rc);
 572                 return rc;
 573         }
 574
 575         ctlr_ptr = pslot->ctrl;
 576
 577         get_hpc_access ();
 578
 579         //--------------------------------------------------------------------
 580         // map physical address to logical address
 581         //--------------------------------------------------------------------
 582         if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4))
 583                 wpg_bbar = ioremap (ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE);
 584
 585         //--------------------------------------------------------------------
 586         // check controller status before reading
 587         //--------------------------------------------------------------------
 588         rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status);
 589         if (!rc) {
 590                 switch (cmd) {
 591                 case READ_ALLSTAT:
 592                         // update the slot structure
 593                         pslot->ctrl->status = status;
 594                         pslot->status = ctrl_read (ctlr_ptr, wpg_bbar, index);
 595                         rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar,
 596                                                        &status);
 597                         if (!rc)
 598                                 pslot->ext_status = ctrl_read (ctlr_ptr, wpg_bbar, index + WPG_1ST_EXTSLOT_INDEX);
 599
 600                         break;
 601
 602                 case READ_SLOTSTATUS:
 603                         // DO NOT update the slot structure
 604                         *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
 605                         break;
 606
 607                 case READ_EXTSLOTSTATUS:
 608                         // DO NOT update the slot structure
 609                         *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
 610                         break;
 611
 612                 case READ_CTLRSTATUS:
 613                         // DO NOT update the slot structure
 614                         *pstatus = status;
 615                         break;
 616
 617                 case READ_BUSSTATUS:
 618                         pslot->busstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
 619                         break;
 620                 case READ_REVLEVEL:
 621                         *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
 622                         break;
 623                 case READ_HPCOPTIONS:
 624                         *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
 625                         break;
 626                 case READ_SLOTLATCHLOWREG:
 627                         // DO NOT update the slot structure
 628                         *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
 629                         break;
 630
 631                         // Not used
 632                 case READ_ALLSLOT:
 633                         list_for_each (pslotlist, &ibmphp_slot_head) {
 634                                 pslot = list_entry (pslotlist, struct slot, ibm_slot_list);
 635                                 index = pslot->ctlr_index;
 636                                 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr,
 637                                                                 wpg_bbar, &status);
 638                                 if (!rc) {
 639                                         pslot->status = ctrl_read (ctlr_ptr, wpg_bbar, index);
 640                                         rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT,
 641                                                                         ctlr_ptr, wpg_bbar, &status);
 642                                         if (!rc)
 643                                                 pslot->ext_status =
 644                                                     ctrl_read (ctlr_ptr, wpg_bbar,
 645                                                                 index + WPG_1ST_EXTSLOT_INDEX);
 646                                 } else {
 647                                         err ("%s - Error ctrl_read failed\n", __FUNCTION__);
 648                                         rc = -EINVAL;
 649                                         break;
 650                                 }
 651                         }
 652                         break;
 653                 default:
 654                         rc = -EINVAL;
 655                         break;
 656                 }
 657         }
 658         //--------------------------------------------------------------------
 659         // cleanup
 660         //--------------------------------------------------------------------
 661
 662         // remove physical to logical address mapping
 663         if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4))
 664                 iounmap (wpg_bbar);
 665
 666         free_hpc_access ();
 667
 668         debug_polling ("%s - Exit rc[%d]\n", __FUNCTION__, rc);
 669         return rc;
 670 }
 671
 672 /*----------------------------------------------------------------------
 673 * Name:    ibmphp_hpc_writeslot()
 674 *
 675 * Action: issue a WRITE command to HPC
 676 *---------------------------------------------------------------------*/
 677 int ibmphp_hpc_writeslot (struct slot * pslot, u8 cmd)
 678 {
 679         void __iomem *wpg_bbar = NULL;
 680         struct controller *ctlr_ptr;
 681         u8 index, status;
 682         int busindex;
 683         u8 done;
 684         int rc = 0;
 685         int timeout;
 686
 687         debug_polling ("%s - Entry pslot[%p] cmd[%x]\n", __FUNCTION__, pslot, cmd);
 688         if (pslot == NULL) {
 689                 rc = -EINVAL;
 690                 err ("%s - Error Exit rc[%d]\n", __FUNCTION__, rc);
 691                 return rc;
 692         }
 693
 694         if ((cmd == HPC_BUS_33CONVMODE) || (cmd == HPC_BUS_66CONVMODE) ||
 695                 (cmd == HPC_BUS_66PCIXMODE) || (cmd == HPC_BUS_100PCIXMODE) ||
 696                 (cmd == HPC_BUS_133PCIXMODE)) {
 697                 busindex = ibmphp_get_bus_index (pslot->bus);
 698                 if (busindex < 0) {
 699                         rc = -EINVAL;
 700                         err ("%s - Exit Error:invalid bus, rc[%d]\n", __FUNCTION__, rc);
 701                         return rc;
 702                 } else
 703                         index = (u8) busindex;
 704         } else
 705                 index = pslot->ctlr_index;
 706
 707         index = hpc_writecmdtoindex (cmd, index);
 708
 709         if (index == HPC_ERROR) {
 710                 rc = -EINVAL;
 711                 err ("%s - Error Exit rc[%d]\n", __FUNCTION__, rc);
 712                 return rc;
 713         }
 714
 715         ctlr_ptr = pslot->ctrl;
 716
 717         get_hpc_access ();
 718
 719         //--------------------------------------------------------------------
 720         // map physical address to logical address
 721         //--------------------------------------------------------------------
 722         if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) {
 723                 wpg_bbar = ioremap (ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE);
 724
 725                 debug ("%s - ctlr id[%x] physical[%lx] logical[%lx] i2c[%x]\n", __FUNCTION__,
 726                 ctlr_ptr->ctlr_id, (ulong) (ctlr_ptr->u.wpeg_ctlr.wpegbbar), (ulong) wpg_bbar,
 727                 ctlr_ptr->u.wpeg_ctlr.i2c_addr);
 728         }
 729         //--------------------------------------------------------------------
 730         // check controller status before writing
 731         //--------------------------------------------------------------------
 732         rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status);
 733         if (!rc) {
 734
 735                 ctrl_write (ctlr_ptr, wpg_bbar, index, cmd);
 736
 737                 //--------------------------------------------------------------------
 738                 // check controller is still not working on the command
 739                 //--------------------------------------------------------------------
 740                 timeout = CMD_COMPLETE_TOUT_SEC;
 741                 done = 0;
 742                 while (!done) {
 743                         rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar,
 744                                                         &status);
 745                         if (!rc) {
 746                                 if (NEEDTOCHECK_CMDSTATUS (cmd)) {
 747                                         if (CTLR_FINISHED (status) == HPC_CTLR_FINISHED_YES)
 748                                                 done = 1;
 749                                 } else
 750                                         done = 1;
 751                         }
 752                         if (!done) {
 753                                 msleep(1000);
 754                                 if (timeout < 1) {
 755                                         done = 1;
 756                                         err ("%s - Error command complete timeout\n", __FUNCTION__);
 757                                         rc = -EFAULT;
 758                                 } else
 759                                         timeout--;
 760                         }
 761                 }
 762                 ctlr_ptr->status = status;
 763         }
 764         // cleanup
 765
 766         // remove physical to logical address mapping
 767         if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4))
 768                 iounmap (wpg_bbar);
 769         free_hpc_access ();
 770
 771         debug_polling ("%s - Exit rc[%d]\n", __FUNCTION__, rc);
 772         return rc;
 773 }
 774
 775 /*----------------------------------------------------------------------
 776 * Name:    get_hpc_access()
 777 *
 778 * Action: make sure only one process can access HPC at one time
 779 *---------------------------------------------------------------------*/
 780 static void get_hpc_access (void)
 781 {
 782         mutex_lock(&sem_hpcaccess);
 783 }
 784
 785 /*----------------------------------------------------------------------
 786 * Name:    free_hpc_access()
 787 *---------------------------------------------------------------------*/
 788 void free_hpc_access (void)
 789 {
 790         mutex_unlock(&sem_hpcaccess);
 791 }
 792
 793 /*----------------------------------------------------------------------
 794 * Name:    ibmphp_lock_operations()
 795 *
 796 * Action: make sure only one process can change the data structure
 797 *---------------------------------------------------------------------*/
 798 void ibmphp_lock_operations (void)
 799 {
 800         down (&semOperations);
 801         to_debug = 1;
 802 }
 803
 804 /*----------------------------------------------------------------------
 805 * Name:    ibmphp_unlock_operations()
 806 *---------------------------------------------------------------------*/
 807 void ibmphp_unlock_operations (void)
 808 {
 809         debug ("%s - Entry\n", __FUNCTION__);
 810         up (&semOperations);
 811         to_debug = 0;
 812         debug ("%s - Exit\n", __FUNCTION__);
 813 }
 814
 815 /*----------------------------------------------------------------------
 816 * Name:    poll_hpc()
 817 *---------------------------------------------------------------------*/
 818 #define POLL_LATCH_REGISTER     0
 819 #define POLL_SLOTS              1
 820 #define POLL_SLEEP              2
 821 static void poll_hpc (void)
 822 {
 823         struct slot myslot;
 824         struct slot *pslot = NULL;
 825         struct list_head *pslotlist;
 826         int rc;
 827         int poll_state = POLL_LATCH_REGISTER;
 828         u8 oldlatchlow = 0x00;
 829         u8 curlatchlow = 0x00;
 830         int poll_count = 0;
 831         u8 ctrl_count = 0x00;
 832
 833         debug ("%s - Entry\n", __FUNCTION__);
 834
 835         while (!ibmphp_shutdown) {
 836                 if (ibmphp_shutdown)
 837                         break;
 838
 839                 /* try to get the lock to do some kind of hardware access */
 840                 down (&semOperations);
 841
 842                 switch (poll_state) {
 843                 case POLL_LATCH_REGISTER:
 844                         oldlatchlow = curlatchlow;
 845                         ctrl_count = 0x00;
 846                         list_for_each (pslotlist, &ibmphp_slot_head) {
 847                                 if (ctrl_count >= ibmphp_get_total_controllers())
 848                                         break;
 849                                 pslot = list_entry (pslotlist, struct slot, ibm_slot_list);
 850                                 if (pslot->ctrl->ctlr_relative_id == ctrl_count) {
 851                                         ctrl_count++;
 852                                         if (READ_SLOT_LATCH (pslot->ctrl)) {
 853                                                 rc = ibmphp_hpc_readslot (pslot,
 854                                                                           READ_SLOTLATCHLOWREG,
 855                                                                           &curlatchlow);
 856                                                 if (oldlatchlow != curlatchlow)
 857                                                         process_changeinlatch (oldlatchlow,
 858                                                                                curlatchlow,
 859                                                                                pslot->ctrl);
 860                                         }
 861                                 }
 862                         }
 863                         ++poll_count;
 864                         poll_state = POLL_SLEEP;
 865                         break;
 866                 case POLL_SLOTS:
 867                         list_for_each (pslotlist, &ibmphp_slot_head) {
 868                                 pslot = list_entry (pslotlist, struct slot, ibm_slot_list);
 869                                 // make a copy of the old status
 870                                 memcpy ((void *) &myslot, (void *) pslot,
 871                                         sizeof (struct slot));
 872                                 rc = ibmphp_hpc_readslot (pslot, READ_ALLSTAT, NULL);
 873                                 if ((myslot.status != pslot->status)
 874                                     || (myslot.ext_status != pslot->ext_status))
 875                                         process_changeinstatus (pslot, &myslot);
 876                         }
 877                         ctrl_count = 0x00;
 878                         list_for_each (pslotlist, &ibmphp_slot_head) {
 879                                 if (ctrl_count >= ibmphp_get_total_controllers())
 880                                         break;
 881                                 pslot = list_entry (pslotlist, struct slot, ibm_slot_list);
 882                                 if (pslot->ctrl->ctlr_relative_id == ctrl_count) {
 883                                         ctrl_count++;
 884                                         if (READ_SLOT_LATCH (pslot->ctrl))
 885                                                 rc = ibmphp_hpc_readslot (pslot,
 886                                                                           READ_SLOTLATCHLOWREG,
 887                                                                           &curlatchlow);
 888                                 }
 889                         }
 890                         ++poll_count;
 891                         poll_state = POLL_SLEEP;
 892                         break;
 893                 case POLL_SLEEP:
 894                         /* don't sleep with a lock on the hardware */
 895                         up (&semOperations);
 896                         msleep(POLL_INTERVAL_SEC * 1000);
 897
 898                         if (ibmphp_shutdown)
 899                                 break;
 900
 901                         down (&semOperations);
 902
 903                         if (poll_count >= POLL_LATCH_CNT) {
 904                                 poll_count = 0;
 905                                 poll_state = POLL_SLOTS;
 906                         } else
 907                                 poll_state = POLL_LATCH_REGISTER;
 908                         break;
 909                 }
 910                 /* give up the hardware semaphore */
 911                 up (&semOperations);
 912                 /* sleep for a short time just for good measure */
 913                 msleep(100);
 914         }
 915         up (&sem_exit);
 916         debug ("%s - Exit\n", __FUNCTION__);
 917 }
 918
 919
 920 /*----------------------------------------------------------------------
 921 * Name:    process_changeinstatus
 922 *
 923 * Action:  compare old and new slot status, process the change in status
 924 *
 925 * Input:   pointer to slot struct, old slot struct
 926 *
 927 * Return   0 or error codes
 928 * Value:
 929 *
 930 * Side
 931 * Effects: None.
 932 *
 933 * Notes:
 934 *---------------------------------------------------------------------*/
 935 static int process_changeinstatus (struct slot *pslot, struct slot *poldslot)
 936 {
 937         u8 status;
 938         int rc = 0;
 939         u8 disable = 0;
 940         u8 update = 0;
 941
 942         debug ("process_changeinstatus - Entry pslot[%p], poldslot[%p]\n", pslot, poldslot);
 943
 944         // bit 0 - HPC_SLOT_POWER
 945         if ((pslot->status & 0x01) != (poldslot->status & 0x01))
 946                 update = 1;
 947
 948         // bit 1 - HPC_SLOT_CONNECT
 949         // ignore
 950
 951         // bit 2 - HPC_SLOT_ATTN
 952         if ((pslot->status & 0x04) != (poldslot->status & 0x04))
 953                 update = 1;
 954
 955         // bit 3 - HPC_SLOT_PRSNT2
 956         // bit 4 - HPC_SLOT_PRSNT1
 957         if (((pslot->status & 0x08) != (poldslot->status & 0x08))
 958                 || ((pslot->status & 0x10) != (poldslot->status & 0x10)))
 959                 update = 1;
 960
 961         // bit 5 - HPC_SLOT_PWRGD
 962         if ((pslot->status & 0x20) != (poldslot->status & 0x20))
 963                 // OFF -> ON: ignore, ON -> OFF: disable slot
 964                 if ((poldslot->status & 0x20) && (SLOT_CONNECT (poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT (poldslot->status)))
 965                         disable = 1;
 966
 967         // bit 6 - HPC_SLOT_BUS_SPEED
 968         // ignore
 969
 970         // bit 7 - HPC_SLOT_LATCH
 971         if ((pslot->status & 0x80) != (poldslot->status & 0x80)) {
 972                 update = 1;
 973                 // OPEN -> CLOSE
 974                 if (pslot->status & 0x80) {
 975                         if (SLOT_PWRGD (pslot->status)) {
 976                                 // power goes on and off after closing latch
 977                                 // check again to make sure power is still ON
 978                                 msleep(1000);
 979                                 rc = ibmphp_hpc_readslot (pslot, READ_SLOTSTATUS, &status);
 980                                 if (SLOT_PWRGD (status))
 981                                         update = 1;
 982                                 else    // overwrite power in pslot to OFF
 983                                         pslot->status &= ~HPC_SLOT_POWER;
 984                         }
 985                 }
 986                 // CLOSE -> OPEN
 987                 else if ((SLOT_PWRGD (poldslot->status) == HPC_SLOT_PWRGD_GOOD)
 988                         && (SLOT_CONNECT (poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT (poldslot->status))) {
 989                         disable = 1;
 990                 }
 991                 // else - ignore
 992         }
 993         // bit 4 - HPC_SLOT_BLINK_ATTN
 994         if ((pslot->ext_status & 0x08) != (poldslot->ext_status & 0x08))
 995                 update = 1;
 996
 997         if (disable) {
 998                 debug ("process_changeinstatus - disable slot\n");
 999                 pslot->flag = 0;
1000                 rc = ibmphp_do_disable_slot (pslot);
1001         }
1002
1003         if (update || disable) {
1004                 ibmphp_update_slot_info (pslot);
1005         }
1006
1007         debug ("%s - Exit rc[%d] disable[%x] update[%x]\n", __FUNCTION__, rc, disable, update);
1008
1009         return rc;
1010 }
1011
1012 /*----------------------------------------------------------------------
1013 * Name:    process_changeinlatch
1014 *
1015 * Action:  compare old and new latch reg status, process the change
1016 *
1017 * Input:   old and current latch register status
1018 *
1019 * Return   0 or error codes
1020 * Value:
1021 *---------------------------------------------------------------------*/
1022 static int process_changeinlatch (u8 old, u8 new, struct controller *ctrl)
1023 {
1024         struct slot myslot, *pslot;
1025         u8 i;
1026         u8 mask;
1027         int rc = 0;
1028
1029         debug ("%s - Entry old[%x], new[%x]\n", __FUNCTION__, old, new);
1030         // bit 0 reserved, 0 is LSB, check bit 1-6 for 6 slots
1031
1032         for (i = ctrl->starting_slot_num; i <= ctrl->ending_slot_num; i++) {
1033                 mask = 0x01 << i;
1034                 if ((mask & old) != (mask & new)) {
1035                         pslot = ibmphp_get_slot_from_physical_num (i);
1036                         if (pslot) {
1037                                 memcpy ((void *) &myslot, (void *) pslot, sizeof (struct slot));
1038                                 rc = ibmphp_hpc_readslot (pslot, READ_ALLSTAT, NULL);
1039                                 debug ("%s - call process_changeinstatus for slot[%d]\n", __FUNCTION__, i);
1040                                 process_changeinstatus (pslot, &myslot);
1041                         } else {
1042                                 rc = -EINVAL;
1043                                 err ("%s - Error bad pointer for slot[%d]\n", __FUNCTION__, i);
1044                         }
1045                 }
1046         }
1047         debug ("%s - Exit rc[%d]\n", __FUNCTION__, rc);
1048         return rc;
1049 }
1050
1051 /*----------------------------------------------------------------------
1052 * Name:    hpc_poll_thread
1053 *
1054 * Action:  polling
1055 *
1056 * Return   0
1057 * Value:
1058 *---------------------------------------------------------------------*/
1059 static int hpc_poll_thread (void *data)
1060 {
1061         debug ("%s - Entry\n", __FUNCTION__);
1062
1063         daemonize("hpc_poll");
1064         allow_signal(SIGKILL);
1065
1066         poll_hpc ();
1067
1068         tid_poll = 0;
1069         debug ("%s - Exit\n", __FUNCTION__);
1070         return 0;
1071 }
1072
1073
1074 /*----------------------------------------------------------------------
1075 * Name:    ibmphp_hpc_start_poll_thread
1076 *
1077 * Action:  start polling thread
1078 *---------------------------------------------------------------------*/
1079 int __init ibmphp_hpc_start_poll_thread (void)
1080 {
1081         int rc = 0;
1082
1083         debug ("%s - Entry\n", __FUNCTION__);
1084
1085         tid_poll = kernel_thread (hpc_poll_thread, NULL, 0);
1086         if (tid_poll < 0) {
1087                 err ("%s - Error, thread not started\n", __FUNCTION__);
1088                 rc = -1;
1089         }
1090
1091         debug ("%s - Exit tid_poll[%d] rc[%d]\n", __FUNCTION__, tid_poll, rc);
1092         return rc;
1093 }
1094
1095 /*----------------------------------------------------------------------
1096 * Name:    ibmphp_hpc_stop_poll_thread
1097 *
1098 * Action:  stop polling thread and cleanup
1099 *---------------------------------------------------------------------*/
1100 void __exit ibmphp_hpc_stop_poll_thread (void)
1101 {
1102         debug ("%s - Entry\n", __FUNCTION__);
1103
1104         ibmphp_shutdown = 1;
1105         debug ("before locking operations \n");
1106         ibmphp_lock_operations ();
1107         debug ("after locking operations \n");
1108
1109         // wait for poll thread to exit
1110         debug ("before sem_exit down \n");
1111         down (&sem_exit);
1112         debug ("after sem_exit down \n");
1113
1114         // cleanup
1115         debug ("before free_hpc_access \n");
1116         free_hpc_access ();
1117         debug ("after free_hpc_access \n");
1118         ibmphp_unlock_operations ();
1119         debug ("after unlock operations \n");
1120         up (&sem_exit);
1121         debug ("after sem exit up\n");
1122
1123         debug ("%s - Exit\n", __FUNCTION__);
1124 }
1125
1126 /*----------------------------------------------------------------------
1127 * Name:    hpc_wait_ctlr_notworking
1128 *
1129 * Action:  wait until the controller is in a not working state
1130 *
1131 * Return   0, HPC_ERROR
1132 * Value:
1133 *---------------------------------------------------------------------*/
1134 static int hpc_wait_ctlr_notworking (int timeout, struct controller *ctlr_ptr, void __iomem *wpg_bbar,
1135                                     u8 * pstatus)
1136 {
1137         int rc = 0;
1138         u8 done = 0;
1139
1140         debug_polling ("hpc_wait_ctlr_notworking - Entry timeout[%d]\n", timeout);
1141
1142         while (!done) {
1143                 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, WPG_CTLR_INDEX);
1144                 if (*pstatus == HPC_ERROR) {
1145                         rc = HPC_ERROR;
1146                         done = 1;
1147                 }
1148                 if (CTLR_WORKING (*pstatus) == HPC_CTLR_WORKING_NO)
1149                         done = 1;
1150                 if (!done) {
1151                         msleep(1000);
1152                         if (timeout < 1) {
1153                                 done = 1;
1154                                 err ("HPCreadslot - Error ctlr timeout\n");
1155                                 rc = HPC_ERROR;
1156                         } else
1157                                 timeout--;
1158                 }
1159         }
1160         debug_polling ("hpc_wait_ctlr_notworking - Exit rc[%x] status[%x]\n", rc, *pstatus);
1161         return rc;
1162 }