drivers/misc/hpilo.h

   1 /*
   2  * linux/drivers/char/hpilo.h
   3  *
   4  * Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
   5  *      David Altobelli <david.altobelli@hp.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #ifndef __HPILO_H
  12 #define __HPILO_H
  13
  14 #define ILO_NAME "hpilo"
  15
  16 /* max number of open channel control blocks per device, hw limited to 32 */
  17 #define MAX_CCB         8
  18 /* max number of supported devices */
  19 #define MAX_ILO_DEV     1
  20 /* max number of files */
  21 #define MAX_OPEN        (MAX_CCB * MAX_ILO_DEV)
  22
  23 /*
  24  * Per device, used to track global memory allocations.
  25  */
  26 struct ilo_hwinfo {
  27         /* mmio registers on device */
  28         char __iomem *mmio_vaddr;
  29
  30         /* doorbell registers on device */
  31         char __iomem *db_vaddr;
  32
  33         /* shared memory on device used for channel control blocks */
  34         char __iomem *ram_vaddr;
  35
  36         /* files corresponding to this device */
  37         struct ccb_data *ccb_alloc[MAX_CCB];
  38
  39         struct pci_dev *ilo_dev;
  40
  41         spinlock_t alloc_lock;
  42         spinlock_t fifo_lock;
  43
  44         struct cdev cdev;
  45 };
  46
  47 /* offset from mmio_vaddr */
  48 #define DB_OUT          0xD4
  49 /* DB_OUT reset bit */
  50 #define DB_RESET        26
  51
  52 /*
  53  * Channel control block. Used to manage hardware queues.
  54  * The format must match hw's version.  The hw ccb is 128 bytes,
  55  * but the context area shouldn't be touched by the driver.
  56  */
  57 #define ILOSW_CCB_SZ    64
  58 #define ILOHW_CCB_SZ    128
  59 struct ccb {
  60         union {
  61                 char *send_fifobar;
  62                 u64 padding1;
  63         } ccb_u1;
  64         union {
  65                 char *send_desc;
  66                 u64 padding2;
  67         } ccb_u2;
  68         u64 send_ctrl;
  69
  70         union {
  71                 char *recv_fifobar;
  72                 u64 padding3;
  73         } ccb_u3;
  74         union {
  75                 char *recv_desc;
  76                 u64 padding4;
  77         } ccb_u4;
  78         u64 recv_ctrl;
  79
  80         union {
  81                 char __iomem *db_base;
  82                 u64 padding5;
  83         } ccb_u5;
  84
  85         u64 channel;
  86
  87         /* unused context area (64 bytes) */
  88 };
  89
  90 /* ccb queue parameters */
  91 #define SENDQ           1
  92 #define RECVQ           2
  93 #define NR_QENTRY       4
  94 #define L2_QENTRY_SZ    12
  95
  96 /* ccb ctrl bitfields */
  97 #define CTRL_BITPOS_L2SZ             0
  98 #define CTRL_BITPOS_FIFOINDEXMASK    4
  99 #define CTRL_BITPOS_DESCLIMIT        18
 100 #define CTRL_BITPOS_A                30
 101 #define CTRL_BITPOS_G                31
 102
 103 /* ccb doorbell macros */
 104 #define L2_DB_SIZE              14
 105 #define ONE_DB_SIZE             (1 << L2_DB_SIZE)
 106
 107 /*
 108  * Per fd structure used to track the ccb allocated to that dev file.
 109  */
 110 struct ccb_data {
 111         /* software version of ccb, using virtual addrs */
 112         struct ccb  driver_ccb;
 113
 114         /* hardware version of ccb, using physical addrs */
 115         struct ccb  ilo_ccb;
 116
 117         /* hardware ccb is written to this shared mapped device memory */
 118         struct ccb __iomem *mapped_ccb;
 119
 120         /* dma'able memory used for send/recv queues */
 121         void       *dma_va;
 122         dma_addr_t  dma_pa;
 123         size_t      dma_size;
 124
 125         /* pointer to hardware device info */
 126         struct ilo_hwinfo *ilo_hw;
 127
 128         /* usage count, to allow for shared ccb's */
 129         int         ccb_cnt;
 130
 131         /* open wanted exclusive access to this ccb */
 132         int         ccb_excl;
 133 };
 134
 135 /*
 136  * FIFO queue structure, shared with hw.
 137  */
 138 #define ILO_START_ALIGN 4096
 139 #define ILO_CACHE_SZ     128
 140 struct fifo {
 141     u64 nrents; /* user requested number of fifo entries */
 142     u64 imask;  /* mask to extract valid fifo index */
 143     u64 merge;  /*  O/C bits to merge in during enqueue operation */
 144     u64 reset;  /* set to non-zero when the target device resets */
 145     u8  pad_0[ILO_CACHE_SZ - (sizeof(u64) * 4)];
 146
 147     u64 head;
 148     u8  pad_1[ILO_CACHE_SZ - (sizeof(u64))];
 149
 150     u64 tail;
 151     u8  pad_2[ILO_CACHE_SZ - (sizeof(u64))];
 152
 153     u64 fifobar[1];
 154 };
 155
 156 /* convert between struct fifo, and the fifobar, which is saved in the ccb */
 157 #define FIFOHANDLESIZE (sizeof(struct fifo) - sizeof(u64))
 158 #define FIFOBARTOHANDLE(_fifo) \
 159         ((struct fifo *)(((char *)(_fifo)) - FIFOHANDLESIZE))
 160
 161 /* the number of qwords to consume from the entry descriptor */
 162 #define ENTRY_BITPOS_QWORDS      0
 163 /* descriptor index number (within a specified queue) */
 164 #define ENTRY_BITPOS_DESCRIPTOR  10
 165 /* state bit, fifo entry consumed by consumer */
 166 #define ENTRY_BITPOS_C           22
 167 /* state bit, fifo entry is occupied */
 168 #define ENTRY_BITPOS_O           23
 169
 170 #define ENTRY_BITS_QWORDS        10
 171 #define ENTRY_BITS_DESCRIPTOR    12
 172 #define ENTRY_BITS_C             1
 173 #define ENTRY_BITS_O             1
 174 #define ENTRY_BITS_TOTAL        \
 175         (ENTRY_BITS_C + ENTRY_BITS_O + \
 176          ENTRY_BITS_QWORDS + ENTRY_BITS_DESCRIPTOR)
 177
 178 /* extract various entry fields */
 179 #define ENTRY_MASK ((1 << ENTRY_BITS_TOTAL) - 1)
 180 #define ENTRY_MASK_C (((1 << ENTRY_BITS_C) - 1) << ENTRY_BITPOS_C)
 181 #define ENTRY_MASK_O (((1 << ENTRY_BITS_O) - 1) << ENTRY_BITPOS_O)
 182 #define ENTRY_MASK_QWORDS \
 183         (((1 << ENTRY_BITS_QWORDS) - 1) << ENTRY_BITPOS_QWORDS)
 184 #define ENTRY_MASK_DESCRIPTOR \
 185         (((1 << ENTRY_BITS_DESCRIPTOR) - 1) << ENTRY_BITPOS_DESCRIPTOR)
 186
 187 #define ENTRY_MASK_NOSTATE (ENTRY_MASK >> (ENTRY_BITS_C + ENTRY_BITS_O))
 188
 189 #endif /* __HPILO_H */