2 * linux/drivers/mmc/host/imxmmc.c - Motorola i.MX MMCI driver
4 * Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de>
5 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
7 * derived from pxamci.c by Russell King
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
14 * Changed to conform redesigned i.MX scatter gather DMA interface
16 * 2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz>
17 * Updated for 2.6.14 kernel
19 * 2005-12-13 Jay Monkman <jtm@smoothsmoothie.com>
20 * Found and corrected problems in the write path
22 * 2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz>
23 * The event handling rewritten right way in softirq.
24 * Added many ugly hacks and delays to overcome SDHC
29 #include <linux/module.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/platform_device.h>
33 #include <linux/interrupt.h>
34 #include <linux/blkdev.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/mmc/host.h>
37 #include <linux/mmc/card.h>
38 #include <linux/delay.h>
39 #include <linux/clk.h>
44 #include <asm/sizes.h>
45 #include <asm/arch/mmc.h>
46 #include <asm/arch/imx-dma.h>
50 #define DRIVER_NAME "imx-mmc"
52 #define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
53 INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
54 INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
64 volatile unsigned int imask
;
65 unsigned int power_mode
;
67 struct imxmmc_platform_data
*pdata
;
69 struct mmc_request
*req
;
70 struct mmc_command
*cmd
;
71 struct mmc_data
*data
;
73 struct timer_list timer
;
74 struct tasklet_struct tasklet
;
75 unsigned int status_reg
;
76 unsigned long pending_events
;
77 /* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */
79 unsigned int data_cnt
;
80 atomic_t stuck_timeout
;
82 unsigned int dma_nents
;
83 unsigned int dma_size
;
87 unsigned char actual_bus_width
;
94 #define IMXMCI_PEND_IRQ_b 0
95 #define IMXMCI_PEND_DMA_END_b 1
96 #define IMXMCI_PEND_DMA_ERR_b 2
97 #define IMXMCI_PEND_WAIT_RESP_b 3
98 #define IMXMCI_PEND_DMA_DATA_b 4
99 #define IMXMCI_PEND_CPU_DATA_b 5
100 #define IMXMCI_PEND_CARD_XCHG_b 6
101 #define IMXMCI_PEND_SET_INIT_b 7
102 #define IMXMCI_PEND_STARTED_b 8
104 #define IMXMCI_PEND_IRQ_m (1 << IMXMCI_PEND_IRQ_b)
105 #define IMXMCI_PEND_DMA_END_m (1 << IMXMCI_PEND_DMA_END_b)
106 #define IMXMCI_PEND_DMA_ERR_m (1 << IMXMCI_PEND_DMA_ERR_b)
107 #define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b)
108 #define IMXMCI_PEND_DMA_DATA_m (1 << IMXMCI_PEND_DMA_DATA_b)
109 #define IMXMCI_PEND_CPU_DATA_m (1 << IMXMCI_PEND_CPU_DATA_b)
110 #define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b)
111 #define IMXMCI_PEND_SET_INIT_m (1 << IMXMCI_PEND_SET_INIT_b)
112 #define IMXMCI_PEND_STARTED_m (1 << IMXMCI_PEND_STARTED_b)
114 static void imxmci_stop_clock(struct imxmci_host
*host
)
117 MMC_STR_STP_CLK
&= ~STR_STP_CLK_START_CLK
;
120 MMC_STR_STP_CLK
|= STR_STP_CLK_STOP_CLK
;
122 if(!(MMC_STATUS
& STATUS_CARD_BUS_CLK_RUN
)) {
123 /* Check twice before cut */
124 if(!(MMC_STATUS
& STATUS_CARD_BUS_CLK_RUN
))
130 dev_dbg(mmc_dev(host
->mmc
), "imxmci_stop_clock blocked, no luck\n");
133 static int imxmci_start_clock(struct imxmci_host
*host
)
135 unsigned int trials
= 0;
136 unsigned int delay_limit
= 128;
139 MMC_STR_STP_CLK
&= ~STR_STP_CLK_STOP_CLK
;
141 clear_bit(IMXMCI_PEND_STARTED_b
, &host
->pending_events
);
144 * Command start of the clock, this usually succeeds in less
145 * then 6 delay loops, but during card detection (low clockrate)
146 * it takes up to 5000 delay loops and sometimes fails for the first time
148 MMC_STR_STP_CLK
|= STR_STP_CLK_START_CLK
;
151 unsigned int delay
= delay_limit
;
154 if(MMC_STATUS
& STATUS_CARD_BUS_CLK_RUN
)
155 /* Check twice before cut */
156 if(MMC_STATUS
& STATUS_CARD_BUS_CLK_RUN
)
159 if(test_bit(IMXMCI_PEND_STARTED_b
, &host
->pending_events
))
163 local_irq_save(flags
);
165 * Ensure, that request is not doubled under all possible circumstances.
166 * It is possible, that cock running state is missed, because some other
167 * IRQ or schedule delays this function execution and the clocks has
168 * been already stopped by other means (response processing, SDHC HW)
170 if(!test_bit(IMXMCI_PEND_STARTED_b
, &host
->pending_events
))
171 MMC_STR_STP_CLK
|= STR_STP_CLK_START_CLK
;
172 local_irq_restore(flags
);
174 } while(++trials
<256);
176 dev_err(mmc_dev(host
->mmc
), "imxmci_start_clock blocked, no luck\n");
181 static void imxmci_softreset(void)
184 MMC_STR_STP_CLK
= 0x8;
185 MMC_STR_STP_CLK
= 0xD;
186 MMC_STR_STP_CLK
= 0x5;
187 MMC_STR_STP_CLK
= 0x5;
188 MMC_STR_STP_CLK
= 0x5;
189 MMC_STR_STP_CLK
= 0x5;
190 MMC_STR_STP_CLK
= 0x5;
191 MMC_STR_STP_CLK
= 0x5;
192 MMC_STR_STP_CLK
= 0x5;
193 MMC_STR_STP_CLK
= 0x5;
200 static int imxmci_busy_wait_for_status(struct imxmci_host
*host
,
201 unsigned int *pstat
, unsigned int stat_mask
,
202 int timeout
, const char *where
)
205 while(!(*pstat
& stat_mask
)) {
207 if(loops
>= timeout
) {
208 dev_dbg(mmc_dev(host
->mmc
), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
209 where
, *pstat
, stat_mask
);
213 *pstat
|= MMC_STATUS
;
218 /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
219 if(!(stat_mask
& STATUS_END_CMD_RESP
) || (host
->mmc
->ios
.clock
>=8000000))
220 dev_info(mmc_dev(host
->mmc
), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
221 loops
, where
, *pstat
, stat_mask
);
225 static void imxmci_setup_data(struct imxmci_host
*host
, struct mmc_data
*data
)
227 unsigned int nob
= data
->blocks
;
228 unsigned int blksz
= data
->blksz
;
229 unsigned int datasz
= nob
* blksz
;
232 if (data
->flags
& MMC_DATA_STREAM
)
236 data
->bytes_xfered
= 0;
242 * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
243 * We are in big troubles for non-512 byte transfers according to note in the paragraph
244 * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least.
245 * The situation is even more complex in reality. The SDHC in not able to handle wll
246 * partial FIFO fills and reads. The length has to be rounded up to burst size multiple.
247 * This is required for SCR read at least.
250 host
->dma_size
= datasz
;
251 if (data
->flags
& MMC_DATA_READ
) {
252 host
->dma_dir
= DMA_FROM_DEVICE
;
254 /* Hack to enable read SCR */
258 host
->dma_dir
= DMA_TO_DEVICE
;
261 /* Convert back to virtual address */
262 host
->data_ptr
= (u16
*)sg_virt(data
->sg
);
265 clear_bit(IMXMCI_PEND_DMA_DATA_b
, &host
->pending_events
);
266 set_bit(IMXMCI_PEND_CPU_DATA_b
, &host
->pending_events
);
271 if (data
->flags
& MMC_DATA_READ
) {
272 host
->dma_dir
= DMA_FROM_DEVICE
;
273 host
->dma_nents
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
,
274 data
->sg_len
, host
->dma_dir
);
276 imx_dma_setup_sg(host
->dma
, data
->sg
, data
->sg_len
, datasz
,
277 host
->res
->start
+ MMC_BUFFER_ACCESS_OFS
, DMA_MODE_READ
);
279 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
280 CCR(host
->dma
) = CCR_DMOD_LINEAR
| CCR_DSIZ_32
| CCR_SMOD_FIFO
| CCR_SSIZ_16
| CCR_REN
;
282 host
->dma_dir
= DMA_TO_DEVICE
;
284 host
->dma_nents
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
,
285 data
->sg_len
, host
->dma_dir
);
287 imx_dma_setup_sg(host
->dma
, data
->sg
, data
->sg_len
, datasz
,
288 host
->res
->start
+ MMC_BUFFER_ACCESS_OFS
, DMA_MODE_WRITE
);
290 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
291 CCR(host
->dma
) = CCR_SMOD_LINEAR
| CCR_SSIZ_32
| CCR_DMOD_FIFO
| CCR_DSIZ_16
| CCR_REN
;
294 #if 1 /* This code is there only for consistency checking and can be disabled in future */
296 for(i
=0; i
<host
->dma_nents
; i
++)
297 host
->dma_size
+=data
->sg
[i
].length
;
299 if (datasz
> host
->dma_size
) {
300 dev_err(mmc_dev(host
->mmc
), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
301 datasz
, host
->dma_size
);
305 host
->dma_size
= datasz
;
309 if(host
->actual_bus_width
== MMC_BUS_WIDTH_4
)
310 BLR(host
->dma
) = 0; /* burst 64 byte read / 64 bytes write */
312 BLR(host
->dma
) = 16; /* burst 16 byte read / 16 bytes write */
314 RSSR(host
->dma
) = DMA_REQ_SDHC
;
316 set_bit(IMXMCI_PEND_DMA_DATA_b
, &host
->pending_events
);
317 clear_bit(IMXMCI_PEND_CPU_DATA_b
, &host
->pending_events
);
319 /* start DMA engine for read, write is delayed after initial response */
320 if (host
->dma_dir
== DMA_FROM_DEVICE
) {
321 imx_dma_enable(host
->dma
);
325 static void imxmci_start_cmd(struct imxmci_host
*host
, struct mmc_command
*cmd
, unsigned int cmdat
)
330 WARN_ON(host
->cmd
!= NULL
);
333 /* Ensure, that clock are stopped else command programming and start fails */
334 imxmci_stop_clock(host
);
336 if (cmd
->flags
& MMC_RSP_BUSY
)
337 cmdat
|= CMD_DAT_CONT_BUSY
;
339 switch (mmc_resp_type(cmd
)) {
340 case MMC_RSP_R1
: /* short CRC, OPCODE */
341 case MMC_RSP_R1B
:/* short CRC, OPCODE, BUSY */
342 cmdat
|= CMD_DAT_CONT_RESPONSE_FORMAT_R1
;
344 case MMC_RSP_R2
: /* long 136 bit + CRC */
345 cmdat
|= CMD_DAT_CONT_RESPONSE_FORMAT_R2
;
347 case MMC_RSP_R3
: /* short */
348 cmdat
|= CMD_DAT_CONT_RESPONSE_FORMAT_R3
;
354 if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b
, &host
->pending_events
) )
355 cmdat
|= CMD_DAT_CONT_INIT
; /* This command needs init */
357 if ( host
->actual_bus_width
== MMC_BUS_WIDTH_4
)
358 cmdat
|= CMD_DAT_CONT_BUS_WIDTH_4
;
360 MMC_CMD
= cmd
->opcode
;
361 MMC_ARGH
= cmd
->arg
>> 16;
362 MMC_ARGL
= cmd
->arg
& 0xffff;
363 MMC_CMD_DAT_CONT
= cmdat
;
365 atomic_set(&host
->stuck_timeout
, 0);
366 set_bit(IMXMCI_PEND_WAIT_RESP_b
, &host
->pending_events
);
369 imask
= IMXMCI_INT_MASK_DEFAULT
;
370 imask
&= ~INT_MASK_END_CMD_RES
;
371 if ( cmdat
& CMD_DAT_CONT_DATA_ENABLE
) {
372 /*imask &= ~INT_MASK_BUF_READY;*/
373 imask
&= ~INT_MASK_DATA_TRAN
;
374 if ( cmdat
& CMD_DAT_CONT_WRITE
)
375 imask
&= ~INT_MASK_WRITE_OP_DONE
;
376 if(test_bit(IMXMCI_PEND_CPU_DATA_b
, &host
->pending_events
))
377 imask
&= ~INT_MASK_BUF_READY
;
380 spin_lock_irqsave(&host
->lock
, flags
);
382 MMC_INT_MASK
= host
->imask
;
383 spin_unlock_irqrestore(&host
->lock
, flags
);
385 dev_dbg(mmc_dev(host
->mmc
), "CMD%02d (0x%02x) mask set to 0x%04x\n",
386 cmd
->opcode
, cmd
->opcode
, imask
);
388 imxmci_start_clock(host
);
391 static void imxmci_finish_request(struct imxmci_host
*host
, struct mmc_request
*req
)
395 spin_lock_irqsave(&host
->lock
, flags
);
397 host
->pending_events
&= ~(IMXMCI_PEND_WAIT_RESP_m
| IMXMCI_PEND_DMA_END_m
|
398 IMXMCI_PEND_DMA_DATA_m
| IMXMCI_PEND_CPU_DATA_m
);
400 host
->imask
= IMXMCI_INT_MASK_DEFAULT
;
401 MMC_INT_MASK
= host
->imask
;
403 spin_unlock_irqrestore(&host
->lock
, flags
);
406 host
->prev_cmd_code
= req
->cmd
->opcode
;
411 mmc_request_done(host
->mmc
, req
);
414 static int imxmci_finish_data(struct imxmci_host
*host
, unsigned int stat
)
416 struct mmc_data
*data
= host
->data
;
419 if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b
, &host
->pending_events
)){
420 imx_dma_disable(host
->dma
);
421 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, host
->dma_nents
,
425 if ( stat
& STATUS_ERR_MASK
) {
426 dev_dbg(mmc_dev(host
->mmc
), "request failed. status: 0x%08x\n",stat
);
427 if(stat
& (STATUS_CRC_READ_ERR
| STATUS_CRC_WRITE_ERR
))
428 data
->error
= -EILSEQ
;
429 else if(stat
& STATUS_TIME_OUT_READ
)
430 data
->error
= -ETIMEDOUT
;
434 data
->bytes_xfered
= host
->dma_size
;
437 data_error
= data
->error
;
444 static int imxmci_cmd_done(struct imxmci_host
*host
, unsigned int stat
)
446 struct mmc_command
*cmd
= host
->cmd
;
449 struct mmc_data
*data
= host
->data
;
456 if (stat
& STATUS_TIME_OUT_RESP
) {
457 dev_dbg(mmc_dev(host
->mmc
), "CMD TIMEOUT\n");
458 cmd
->error
= -ETIMEDOUT
;
459 } else if (stat
& STATUS_RESP_CRC_ERR
&& cmd
->flags
& MMC_RSP_CRC
) {
460 dev_dbg(mmc_dev(host
->mmc
), "cmd crc error\n");
461 cmd
->error
= -EILSEQ
;
464 if(cmd
->flags
& MMC_RSP_PRESENT
) {
465 if(cmd
->flags
& MMC_RSP_136
) {
466 for (i
= 0; i
< 4; i
++) {
467 u32 a
= MMC_RES_FIFO
& 0xffff;
468 u32 b
= MMC_RES_FIFO
& 0xffff;
469 cmd
->resp
[i
] = a
<<16 | b
;
472 a
= MMC_RES_FIFO
& 0xffff;
473 b
= MMC_RES_FIFO
& 0xffff;
474 c
= MMC_RES_FIFO
& 0xffff;
475 cmd
->resp
[0] = a
<<24 | b
<<8 | c
>>8;
479 dev_dbg(mmc_dev(host
->mmc
), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n",
480 cmd
->resp
[0], cmd
->resp
[1], cmd
->resp
[2], cmd
->resp
[3], cmd
->error
);
482 if (data
&& !cmd
->error
&& !(stat
& STATUS_ERR_MASK
)) {
483 if (host
->req
->data
->flags
& MMC_DATA_WRITE
) {
485 /* Wait for FIFO to be empty before starting DMA write */
488 if(imxmci_busy_wait_for_status(host
, &stat
,
490 40, "imxmci_cmd_done DMA WR") < 0) {
492 imxmci_finish_data(host
, stat
);
494 imxmci_finish_request(host
, host
->req
);
495 dev_warn(mmc_dev(host
->mmc
), "STATUS = 0x%04x\n",
500 if(test_bit(IMXMCI_PEND_DMA_DATA_b
, &host
->pending_events
)) {
501 imx_dma_enable(host
->dma
);
505 struct mmc_request
*req
;
506 imxmci_stop_clock(host
);
510 imxmci_finish_data(host
, stat
);
513 imxmci_finish_request(host
, req
);
515 dev_warn(mmc_dev(host
->mmc
), "imxmci_cmd_done: no request to finish\n");
522 static int imxmci_data_done(struct imxmci_host
*host
, unsigned int stat
)
524 struct mmc_data
*data
= host
->data
;
530 data_error
= imxmci_finish_data(host
, stat
);
532 if (host
->req
->stop
) {
533 imxmci_stop_clock(host
);
534 imxmci_start_cmd(host
, host
->req
->stop
, 0);
536 struct mmc_request
*req
;
539 imxmci_finish_request(host
, req
);
541 dev_warn(mmc_dev(host
->mmc
), "imxmci_data_done: no request to finish\n");
548 static int imxmci_cpu_driven_data(struct imxmci_host
*host
, unsigned int *pstat
)
553 unsigned int stat
= *pstat
;
555 if(host
->actual_bus_width
!= MMC_BUS_WIDTH_4
)
560 /* This is unfortunately required */
561 dev_dbg(mmc_dev(host
->mmc
), "imxmci_cpu_driven_data running STATUS = 0x%x\n",
564 udelay(20); /* required for clocks < 8MHz*/
566 if(host
->dma_dir
== DMA_FROM_DEVICE
) {
567 imxmci_busy_wait_for_status(host
, &stat
,
568 STATUS_APPL_BUFF_FF
| STATUS_DATA_TRANS_DONE
|
569 STATUS_TIME_OUT_READ
,
570 50, "imxmci_cpu_driven_data read");
572 while((stat
& (STATUS_APPL_BUFF_FF
| STATUS_DATA_TRANS_DONE
)) &&
573 !(stat
& STATUS_TIME_OUT_READ
) &&
574 (host
->data_cnt
< 512)) {
576 udelay(20); /* required for clocks < 8MHz*/
578 for(i
= burst_len
; i
>=2 ; i
-=2) {
580 data
= MMC_BUFFER_ACCESS
;
581 udelay(10); /* required for clocks < 8MHz*/
582 if(host
->data_cnt
+2 <= host
->dma_size
) {
583 *(host
->data_ptr
++) = data
;
585 if(host
->data_cnt
< host
->dma_size
)
586 *(u8
*)(host
->data_ptr
) = data
;
593 dev_dbg(mmc_dev(host
->mmc
), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
594 host
->data_cnt
, burst_len
, stat
);
597 if((stat
& STATUS_DATA_TRANS_DONE
) && (host
->data_cnt
>= 512))
600 if(host
->dma_size
& 0x1ff)
601 stat
&= ~STATUS_CRC_READ_ERR
;
603 if(stat
& STATUS_TIME_OUT_READ
) {
604 dev_dbg(mmc_dev(host
->mmc
), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
610 imxmci_busy_wait_for_status(host
, &stat
,
612 20, "imxmci_cpu_driven_data write");
614 while((stat
& STATUS_APPL_BUFF_FE
) &&
615 (host
->data_cnt
< host
->dma_size
)) {
616 if(burst_len
>= host
->dma_size
- host
->data_cnt
) {
617 burst_len
= host
->dma_size
- host
->data_cnt
;
618 host
->data_cnt
= host
->dma_size
;
621 host
->data_cnt
+= burst_len
;
624 for(i
= burst_len
; i
>0 ; i
-=2)
625 MMC_BUFFER_ACCESS
= *(host
->data_ptr
++);
629 dev_dbg(mmc_dev(host
->mmc
), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
639 static void imxmci_dma_irq(int dma
, void *devid
)
641 struct imxmci_host
*host
= devid
;
642 uint32_t stat
= MMC_STATUS
;
644 atomic_set(&host
->stuck_timeout
, 0);
645 host
->status_reg
= stat
;
646 set_bit(IMXMCI_PEND_DMA_END_b
, &host
->pending_events
);
647 tasklet_schedule(&host
->tasklet
);
650 static irqreturn_t
imxmci_irq(int irq
, void *devid
)
652 struct imxmci_host
*host
= devid
;
653 uint32_t stat
= MMC_STATUS
;
656 MMC_INT_MASK
= host
->imask
| INT_MASK_SDIO
| INT_MASK_AUTO_CARD_DETECT
;
658 atomic_set(&host
->stuck_timeout
, 0);
659 host
->status_reg
= stat
;
660 set_bit(IMXMCI_PEND_IRQ_b
, &host
->pending_events
);
661 set_bit(IMXMCI_PEND_STARTED_b
, &host
->pending_events
);
662 tasklet_schedule(&host
->tasklet
);
664 return IRQ_RETVAL(handled
);;
667 static void imxmci_tasklet_fnc(unsigned long data
)
669 struct imxmci_host
*host
= (struct imxmci_host
*)data
;
671 unsigned int data_dir_mask
= 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
674 if(atomic_read(&host
->stuck_timeout
) > 4) {
678 host
->status_reg
= stat
;
679 if (test_bit(IMXMCI_PEND_WAIT_RESP_b
, &host
->pending_events
))
680 if (test_bit(IMXMCI_PEND_DMA_DATA_b
, &host
->pending_events
))
685 if (test_bit(IMXMCI_PEND_DMA_DATA_b
, &host
->pending_events
))
686 if(test_bit(IMXMCI_PEND_DMA_END_b
, &host
->pending_events
))
693 dev_err(mmc_dev(host
->mmc
), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
694 what
, stat
, MMC_INT_MASK
);
695 dev_err(mmc_dev(host
->mmc
), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
696 MMC_CMD_DAT_CONT
, MMC_BLK_LEN
, MMC_NOB
, CCR(host
->dma
));
697 dev_err(mmc_dev(host
->mmc
), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
698 host
->cmd
?host
->cmd
->opcode
:0, host
->prev_cmd_code
, 1<<host
->actual_bus_width
, host
->dma_size
);
701 if(!host
->present
|| timeout
)
702 host
->status_reg
= STATUS_TIME_OUT_RESP
| STATUS_TIME_OUT_READ
|
703 STATUS_CRC_READ_ERR
| STATUS_CRC_WRITE_ERR
;
705 if(test_bit(IMXMCI_PEND_IRQ_b
, &host
->pending_events
) || timeout
) {
706 clear_bit(IMXMCI_PEND_IRQ_b
, &host
->pending_events
);
710 * This is not required in theory, but there is chance to miss some flag
711 * which clears automatically by mask write, FreeScale original code keeps
712 * stat from IRQ time so do I
714 stat
|= host
->status_reg
;
716 if(test_bit(IMXMCI_PEND_CPU_DATA_b
, &host
->pending_events
))
717 stat
&= ~STATUS_CRC_READ_ERR
;
719 if(test_bit(IMXMCI_PEND_WAIT_RESP_b
, &host
->pending_events
)) {
720 imxmci_busy_wait_for_status(host
, &stat
,
721 STATUS_END_CMD_RESP
| STATUS_ERR_MASK
,
722 20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
725 if(stat
& (STATUS_END_CMD_RESP
| STATUS_ERR_MASK
)) {
726 if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b
, &host
->pending_events
))
727 imxmci_cmd_done(host
, stat
);
728 if(host
->data
&& (stat
& STATUS_ERR_MASK
))
729 imxmci_data_done(host
, stat
);
732 if(test_bit(IMXMCI_PEND_CPU_DATA_b
, &host
->pending_events
)) {
734 if(imxmci_cpu_driven_data(host
, &stat
)){
735 if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b
, &host
->pending_events
))
736 imxmci_cmd_done(host
, stat
);
737 atomic_clear_mask(IMXMCI_PEND_IRQ_m
|IMXMCI_PEND_CPU_DATA_m
,
738 &host
->pending_events
);
739 imxmci_data_done(host
, stat
);
744 if(test_bit(IMXMCI_PEND_DMA_END_b
, &host
->pending_events
) &&
745 !test_bit(IMXMCI_PEND_WAIT_RESP_b
, &host
->pending_events
)) {
749 stat
|= host
->status_reg
;
751 if(host
->dma_dir
== DMA_TO_DEVICE
) {
752 data_dir_mask
= STATUS_WRITE_OP_DONE
;
754 data_dir_mask
= STATUS_DATA_TRANS_DONE
;
757 if(stat
& data_dir_mask
) {
758 clear_bit(IMXMCI_PEND_DMA_END_b
, &host
->pending_events
);
759 imxmci_data_done(host
, stat
);
763 if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b
, &host
->pending_events
)) {
766 imxmci_cmd_done(host
, STATUS_TIME_OUT_RESP
);
769 imxmci_data_done(host
, STATUS_TIME_OUT_READ
|
770 STATUS_CRC_READ_ERR
| STATUS_CRC_WRITE_ERR
);
773 imxmci_finish_request(host
, host
->req
);
775 mmc_detect_change(host
->mmc
, msecs_to_jiffies(100));
780 static void imxmci_request(struct mmc_host
*mmc
, struct mmc_request
*req
)
782 struct imxmci_host
*host
= mmc_priv(mmc
);
785 WARN_ON(host
->req
!= NULL
);
792 imxmci_setup_data(host
, req
->data
);
794 cmdat
|= CMD_DAT_CONT_DATA_ENABLE
;
796 if (req
->data
->flags
& MMC_DATA_WRITE
)
797 cmdat
|= CMD_DAT_CONT_WRITE
;
799 if (req
->data
->flags
& MMC_DATA_STREAM
) {
800 cmdat
|= CMD_DAT_CONT_STREAM_BLOCK
;
804 imxmci_start_cmd(host
, req
->cmd
, cmdat
);
807 #define CLK_RATE 19200000
809 static void imxmci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
811 struct imxmci_host
*host
= mmc_priv(mmc
);
814 if( ios
->bus_width
==MMC_BUS_WIDTH_4
) {
815 host
->actual_bus_width
= MMC_BUS_WIDTH_4
;
816 imx_gpio_mode(PB11_PF_SD_DAT3
);
818 host
->actual_bus_width
= MMC_BUS_WIDTH_1
;
819 imx_gpio_mode(GPIO_PORTB
| GPIO_IN
| GPIO_PUEN
| 11);
822 if ( host
->power_mode
!= ios
->power_mode
) {
823 switch (ios
->power_mode
) {
827 set_bit(IMXMCI_PEND_SET_INIT_b
, &host
->pending_events
);
832 host
->power_mode
= ios
->power_mode
;
838 /* The prescaler is 5 for PERCLK2 equal to 96MHz
839 * then 96MHz / 5 = 19.2 MHz
841 clk
= clk_get_rate(host
->clk
);
842 prescaler
=(clk
+(CLK_RATE
*7)/8)/CLK_RATE
;
845 case 1: prescaler
= 0;
847 case 2: prescaler
= 1;
849 case 3: prescaler
= 2;
851 case 4: prescaler
= 4;
854 case 5: prescaler
= 5;
858 dev_dbg(mmc_dev(host
->mmc
), "PERCLK2 %d MHz -> prescaler %d\n",
861 for(clk
=0; clk
<8; clk
++) {
863 x
= CLK_RATE
/ (1<<clk
);
868 MMC_STR_STP_CLK
|= STR_STP_CLK_ENABLE
; /* enable controller */
870 imxmci_stop_clock(host
);
871 MMC_CLK_RATE
= (prescaler
<<3) | clk
;
873 * Under my understanding, clock should not be started there, because it would
874 * initiate SDHC sequencer and send last or random command into card
876 /*imxmci_start_clock(host);*/
878 dev_dbg(mmc_dev(host
->mmc
), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE
);
880 imxmci_stop_clock(host
);
884 static int imxmci_get_ro(struct mmc_host
*mmc
)
886 struct imxmci_host
*host
= mmc_priv(mmc
);
888 if (host
->pdata
&& host
->pdata
->get_ro
)
889 return !!host
->pdata
->get_ro(mmc_dev(mmc
));
891 * Board doesn't support read only detection; let the mmc core
898 static const struct mmc_host_ops imxmci_ops
= {
899 .request
= imxmci_request
,
900 .set_ios
= imxmci_set_ios
,
901 .get_ro
= imxmci_get_ro
,
904 static void imxmci_check_status(unsigned long data
)
906 struct imxmci_host
*host
= (struct imxmci_host
*)data
;
908 if (host
->pdata
&& host
->pdata
->card_present
&&
909 host
->pdata
->card_present(mmc_dev(host
->mmc
)) != host
->present
) {
911 dev_info(mmc_dev(host
->mmc
), "card %s\n",
912 host
->present
? "inserted" : "removed");
914 set_bit(IMXMCI_PEND_CARD_XCHG_b
, &host
->pending_events
);
915 tasklet_schedule(&host
->tasklet
);
918 if(test_bit(IMXMCI_PEND_WAIT_RESP_b
, &host
->pending_events
) ||
919 test_bit(IMXMCI_PEND_DMA_DATA_b
, &host
->pending_events
)) {
920 atomic_inc(&host
->stuck_timeout
);
921 if(atomic_read(&host
->stuck_timeout
) > 4)
922 tasklet_schedule(&host
->tasklet
);
924 atomic_set(&host
->stuck_timeout
, 0);
928 mod_timer(&host
->timer
, jiffies
+ (HZ
>>1));
931 static int imxmci_probe(struct platform_device
*pdev
)
933 struct mmc_host
*mmc
;
934 struct imxmci_host
*host
= NULL
;
938 printk(KERN_INFO
"i.MX mmc driver\n");
940 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
941 irq
= platform_get_irq(pdev
, 0);
945 if (!request_mem_region(r
->start
, 0x100, pdev
->name
))
948 mmc
= mmc_alloc_host(sizeof(struct imxmci_host
), &pdev
->dev
);
954 mmc
->ops
= &imxmci_ops
;
956 mmc
->f_max
= CLK_RATE
/2;
957 mmc
->ocr_avail
= MMC_VDD_32_33
;
958 mmc
->caps
= MMC_CAP_4_BIT_DATA
;
960 /* MMC core transfer sizes tunable parameters */
961 mmc
->max_hw_segs
= 64;
962 mmc
->max_phys_segs
= 64;
963 mmc
->max_seg_size
= 64*512; /* default PAGE_CACHE_SIZE */
964 mmc
->max_req_size
= 64*512; /* default PAGE_CACHE_SIZE */
965 mmc
->max_blk_size
= 2048;
966 mmc
->max_blk_count
= 65535;
968 host
= mmc_priv(mmc
);
970 host
->dma_allocated
= 0;
971 host
->pdata
= pdev
->dev
.platform_data
;
973 dev_warn(&pdev
->dev
, "No platform data provided!\n");
975 spin_lock_init(&host
->lock
);
979 host
->clk
= clk_get(&pdev
->dev
, "perclk2");
980 if (IS_ERR(host
->clk
)) {
981 ret
= PTR_ERR(host
->clk
);
984 clk_enable(host
->clk
);
986 imx_gpio_mode(PB8_PF_SD_DAT0
);
987 imx_gpio_mode(PB9_PF_SD_DAT1
);
988 imx_gpio_mode(PB10_PF_SD_DAT2
);
989 /* Configured as GPIO with pull-up to ensure right MCC card mode */
990 /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */
991 imx_gpio_mode(GPIO_PORTB
| GPIO_IN
| GPIO_PUEN
| 11);
992 /* imx_gpio_mode(PB11_PF_SD_DAT3); */
993 imx_gpio_mode(PB12_PF_SD_CLK
);
994 imx_gpio_mode(PB13_PF_SD_CMD
);
998 if ( MMC_REV_NO
!= 0x390 ) {
999 dev_err(mmc_dev(host
->mmc
), "wrong rev.no. 0x%08x. aborting.\n",
1004 MMC_READ_TO
= 0x2db4; /* recommended in data sheet */
1006 host
->imask
= IMXMCI_INT_MASK_DEFAULT
;
1007 MMC_INT_MASK
= host
->imask
;
1009 host
->dma
= imx_dma_request_by_prio(DRIVER_NAME
, DMA_PRIO_LOW
);
1011 dev_err(mmc_dev(host
->mmc
), "imx_dma_request_by_prio failed\n");
1015 host
->dma_allocated
=1;
1016 imx_dma_setup_handlers(host
->dma
, imxmci_dma_irq
, NULL
, host
);
1018 tasklet_init(&host
->tasklet
, imxmci_tasklet_fnc
, (unsigned long)host
);
1020 host
->pending_events
=0;
1022 ret
= request_irq(host
->irq
, imxmci_irq
, 0, DRIVER_NAME
, host
);
1026 if (host
->pdata
&& host
->pdata
->card_present
)
1027 host
->present
= host
->pdata
->card_present(mmc_dev(mmc
));
1028 else /* if there is no way to detect assume that card is present */
1031 init_timer(&host
->timer
);
1032 host
->timer
.data
= (unsigned long)host
;
1033 host
->timer
.function
= imxmci_check_status
;
1034 add_timer(&host
->timer
);
1035 mod_timer(&host
->timer
, jiffies
+ (HZ
>>1));
1037 platform_set_drvdata(pdev
, mmc
);
1045 if(host
->dma_allocated
){
1046 imx_dma_free(host
->dma
);
1047 host
->dma_allocated
=0;
1050 clk_disable(host
->clk
);
1056 release_mem_region(r
->start
, 0x100);
1060 static int imxmci_remove(struct platform_device
*pdev
)
1062 struct mmc_host
*mmc
= platform_get_drvdata(pdev
);
1064 platform_set_drvdata(pdev
, NULL
);
1067 struct imxmci_host
*host
= mmc_priv(mmc
);
1069 tasklet_disable(&host
->tasklet
);
1071 del_timer_sync(&host
->timer
);
1072 mmc_remove_host(mmc
);
1074 free_irq(host
->irq
, host
);
1075 if(host
->dma_allocated
){
1076 imx_dma_free(host
->dma
);
1077 host
->dma_allocated
=0;
1080 tasklet_kill(&host
->tasklet
);
1082 clk_disable(host
->clk
);
1085 release_mem_region(host
->res
->start
, 0x100);
1093 static int imxmci_suspend(struct platform_device
*dev
, pm_message_t state
)
1095 struct mmc_host
*mmc
= platform_get_drvdata(dev
);
1099 ret
= mmc_suspend_host(mmc
, state
);
1104 static int imxmci_resume(struct platform_device
*dev
)
1106 struct mmc_host
*mmc
= platform_get_drvdata(dev
);
1107 struct imxmci_host
*host
;
1111 host
= mmc_priv(mmc
);
1113 set_bit(IMXMCI_PEND_SET_INIT_b
, &host
->pending_events
);
1114 ret
= mmc_resume_host(mmc
);
1120 #define imxmci_suspend NULL
1121 #define imxmci_resume NULL
1122 #endif /* CONFIG_PM */
1124 static struct platform_driver imxmci_driver
= {
1125 .probe
= imxmci_probe
,
1126 .remove
= imxmci_remove
,
1127 .suspend
= imxmci_suspend
,
1128 .resume
= imxmci_resume
,
1130 .name
= DRIVER_NAME
,
1131 .owner
= THIS_MODULE
,
1135 static int __init
imxmci_init(void)
1137 return platform_driver_register(&imxmci_driver
);
1140 static void __exit
imxmci_exit(void)
1142 platform_driver_unregister(&imxmci_driver
);
1145 module_init(imxmci_init
);
1146 module_exit(imxmci_exit
);
1148 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1149 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1150 MODULE_LICENSE("GPL");
1151 MODULE_ALIAS("platform:imx-mmc");