2 * linux/arch/arm/mach-at91rm9200/clock.c
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
17 #include <linux/debugfs.h>
18 #include <linux/seq_file.h>
19 #include <linux/list.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/spinlock.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
26 #include <asm/semaphore.h>
28 #include <asm/mach-types.h>
30 #include <asm/arch/hardware.h>
31 #include <asm/arch/board.h> /* for master clock global */
36 * There's a lot more which can be done with clocks, including cpufreq
37 * integration, slow clock mode support (for system suspend), letting
38 * PLLB be used at other rates (on boards that don't need USB), etc.
42 const char *name
; /* unique clock name */
43 const char *function
; /* function of the clock */
44 struct device
*dev
; /* device associated with function */
45 unsigned long rate_hz
;
48 void (*mode
)(struct clk
*, int);
49 unsigned id
:2; /* PCK0..3, or 32k/main/a/b */
52 unsigned programmable
:1;
56 static spinlock_t clk_lock
;
57 static u32 at91_pllb_usb_init
;
60 * Four primary clock sources: two crystal oscillators (32K, main), and
61 * two PLLs. PLLA usually runs the master clock; and PLLB must run at
62 * 48 MHz (unless no USB function clocks are needed). The main clock and
63 * both PLLs are turned off to run in "slow clock mode" (system suspend).
65 static struct clk clk32k
= {
67 .rate_hz
= AT91_SLOW_CLOCK
,
68 .users
= 1, /* always on */
72 static struct clk main_clk
= {
74 .pmc_mask
= AT91_PMC_MOSCS
, /* in PMC_SR */
78 static struct clk plla
= {
81 .pmc_mask
= AT91_PMC_LOCKA
, /* in PMC_SR */
87 static void pllb_mode(struct clk
*clk
, int is_on
)
92 is_on
= AT91_PMC_LOCKB
;
93 value
= at91_pllb_usb_init
;
97 at91_sys_write(AT91_CKGR_PLLBR
, value
);
101 } while ((at91_sys_read(AT91_PMC_SR
) & AT91_PMC_LOCKB
) != is_on
);
104 static struct clk pllb
= {
107 .pmc_mask
= AT91_PMC_LOCKB
, /* in PMC_SR */
114 static void pmc_sys_mode(struct clk
*clk
, int is_on
)
117 at91_sys_write(AT91_PMC_SCER
, clk
->pmc_mask
);
119 at91_sys_write(AT91_PMC_SCDR
, clk
->pmc_mask
);
122 /* USB function clocks (PLLB must be 48 MHz) */
123 static struct clk udpck
= {
126 .pmc_mask
= AT91_PMC_UDP
,
127 .mode
= pmc_sys_mode
,
129 static struct clk uhpck
= {
132 .pmc_mask
= AT91_PMC_UHP
,
133 .mode
= pmc_sys_mode
,
136 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
138 * The four programmable clocks can be parented by any primary clock.
139 * You must configure pin multiplexing to bring these signals out.
141 static struct clk pck0
= {
143 .pmc_mask
= AT91_PMC_PCK0
,
144 .mode
= pmc_sys_mode
,
148 static struct clk pck1
= {
150 .pmc_mask
= AT91_PMC_PCK1
,
151 .mode
= pmc_sys_mode
,
155 static struct clk pck2
= {
157 .pmc_mask
= AT91_PMC_PCK2
,
158 .mode
= pmc_sys_mode
,
162 static struct clk pck3
= {
164 .pmc_mask
= AT91_PMC_PCK3
,
165 .mode
= pmc_sys_mode
,
169 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
173 * The master clock is divided from the CPU clock (by 1-4). It's used for
174 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
175 * (e.g baud rate generation). It's sourced from one of the primary clocks.
177 static struct clk mck
= {
179 .pmc_mask
= AT91_PMC_MCKRDY
, /* in PMC_SR */
182 static void pmc_periph_mode(struct clk
*clk
, int is_on
)
185 at91_sys_write(AT91_PMC_PCER
, clk
->pmc_mask
);
187 at91_sys_write(AT91_PMC_PCDR
, clk
->pmc_mask
);
190 static struct clk udc_clk
= {
193 .pmc_mask
= 1 << AT91_ID_UDP
,
194 .mode
= pmc_periph_mode
,
196 static struct clk ohci_clk
= {
199 .pmc_mask
= 1 << AT91_ID_UHP
,
200 .mode
= pmc_periph_mode
,
202 static struct clk ether_clk
= {
205 .pmc_mask
= 1 << AT91_ID_EMAC
,
206 .mode
= pmc_periph_mode
,
208 static struct clk mmc_clk
= {
211 .pmc_mask
= 1 << AT91_ID_MCI
,
212 .mode
= pmc_periph_mode
,
214 static struct clk twi_clk
= {
217 .pmc_mask
= 1 << AT91_ID_TWI
,
218 .mode
= pmc_periph_mode
,
220 static struct clk usart0_clk
= {
221 .name
= "usart0_clk",
223 .pmc_mask
= 1 << AT91_ID_US0
,
224 .mode
= pmc_periph_mode
,
226 static struct clk usart1_clk
= {
227 .name
= "usart1_clk",
229 .pmc_mask
= 1 << AT91_ID_US1
,
230 .mode
= pmc_periph_mode
,
232 static struct clk usart2_clk
= {
233 .name
= "usart2_clk",
235 .pmc_mask
= 1 << AT91_ID_US2
,
236 .mode
= pmc_periph_mode
,
238 static struct clk usart3_clk
= {
239 .name
= "usart3_clk",
241 .pmc_mask
= 1 << AT91_ID_US3
,
242 .mode
= pmc_periph_mode
,
244 static struct clk spi_clk
= {
247 .pmc_mask
= 1 << AT91_ID_SPI
,
248 .mode
= pmc_periph_mode
,
250 static struct clk pioA_clk
= {
253 .pmc_mask
= 1 << AT91_ID_PIOA
,
254 .mode
= pmc_periph_mode
,
256 static struct clk pioB_clk
= {
259 .pmc_mask
= 1 << AT91_ID_PIOB
,
260 .mode
= pmc_periph_mode
,
262 static struct clk pioC_clk
= {
265 .pmc_mask
= 1 << AT91_ID_PIOC
,
266 .mode
= pmc_periph_mode
,
268 static struct clk pioD_clk
= {
271 .pmc_mask
= 1 << AT91_ID_PIOD
,
272 .mode
= pmc_periph_mode
,
275 static struct clk
*const clock_list
[] = {
276 /* four primary clocks -- MUST BE FIRST! */
282 /* PLLB children (USB) */
286 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
287 /* programmable clocks */
292 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
294 /* MCK and peripherals */
317 * Associate a particular clock with a function (eg, "uart") and device.
318 * The drivers can then request the same 'function' with several different
319 * devices and not care about which clock name to use.
321 void __init
at91_clock_associate(const char *id
, struct device
*dev
, const char *func
)
323 struct clk
*clk
= clk_get(NULL
, id
);
325 if (!dev
|| !clk
|| !IS_ERR(clk_get(dev
, func
)))
328 clk
->function
= func
;
332 /* clocks are all static for now; no refcounting necessary */
333 struct clk
*clk_get(struct device
*dev
, const char *id
)
337 for (i
= 0; i
< ARRAY_SIZE(clock_list
); i
++) {
338 struct clk
*clk
= clock_list
[i
];
340 if (strcmp(id
, clk
->name
) == 0)
342 if (clk
->function
&& (dev
== clk
->dev
) && strcmp(id
, clk
->function
) == 0)
346 return ERR_PTR(-ENOENT
);
348 EXPORT_SYMBOL(clk_get
);
350 void clk_put(struct clk
*clk
)
353 EXPORT_SYMBOL(clk_put
);
355 static void __clk_enable(struct clk
*clk
)
358 __clk_enable(clk
->parent
);
359 if (clk
->users
++ == 0 && clk
->mode
)
363 int clk_enable(struct clk
*clk
)
367 spin_lock_irqsave(&clk_lock
, flags
);
369 spin_unlock_irqrestore(&clk_lock
, flags
);
372 EXPORT_SYMBOL(clk_enable
);
374 static void __clk_disable(struct clk
*clk
)
376 BUG_ON(clk
->users
== 0);
377 if (--clk
->users
== 0 && clk
->mode
)
380 __clk_disable(clk
->parent
);
383 void clk_disable(struct clk
*clk
)
387 spin_lock_irqsave(&clk_lock
, flags
);
389 spin_unlock_irqrestore(&clk_lock
, flags
);
391 EXPORT_SYMBOL(clk_disable
);
393 unsigned long clk_get_rate(struct clk
*clk
)
398 spin_lock_irqsave(&clk_lock
, flags
);
401 if (rate
|| !clk
->parent
)
405 spin_unlock_irqrestore(&clk_lock
, flags
);
408 EXPORT_SYMBOL(clk_get_rate
);
410 /*------------------------------------------------------------------------*/
412 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
415 * For now, only the programmable clocks support reparenting (MCK could
416 * do this too, with care) or rate changing (the PLLs could do this too,
417 * ditto MCK but that's more for cpufreq). Drivers may reparent to get
418 * a better rate match; we don't.
421 long clk_round_rate(struct clk
*clk
, unsigned long rate
)
425 unsigned long actual
;
427 if (!clk
->programmable
)
429 spin_lock_irqsave(&clk_lock
, flags
);
431 actual
= clk
->parent
->rate_hz
;
432 for (prescale
= 0; prescale
< 7; prescale
++) {
433 if (actual
&& actual
<= rate
)
438 spin_unlock_irqrestore(&clk_lock
, flags
);
439 return (prescale
< 7) ? actual
: -ENOENT
;
441 EXPORT_SYMBOL(clk_round_rate
);
443 int clk_set_rate(struct clk
*clk
, unsigned long rate
)
447 unsigned long actual
;
449 if (!clk
->programmable
)
453 spin_lock_irqsave(&clk_lock
, flags
);
455 actual
= clk
->parent
->rate_hz
;
456 for (prescale
= 0; prescale
< 7; prescale
++) {
457 if (actual
&& actual
<= rate
) {
460 pckr
= at91_sys_read(AT91_PMC_PCKR(clk
->id
));
461 pckr
&= AT91_PMC_CSS_PLLB
; /* clock selection */
462 pckr
|= prescale
<< 2;
463 at91_sys_write(AT91_PMC_PCKR(clk
->id
), pckr
);
464 clk
->rate_hz
= actual
;
470 spin_unlock_irqrestore(&clk_lock
, flags
);
471 return (prescale
< 7) ? actual
: -ENOENT
;
473 EXPORT_SYMBOL(clk_set_rate
);
475 struct clk
*clk_get_parent(struct clk
*clk
)
479 EXPORT_SYMBOL(clk_get_parent
);
481 int clk_set_parent(struct clk
*clk
, struct clk
*parent
)
487 if (!parent
->primary
|| !clk
->programmable
)
489 spin_lock_irqsave(&clk_lock
, flags
);
491 clk
->rate_hz
= parent
->rate_hz
;
492 clk
->parent
= parent
;
493 at91_sys_write(AT91_PMC_PCKR(clk
->id
), parent
->id
);
495 spin_unlock_irqrestore(&clk_lock
, flags
);
498 EXPORT_SYMBOL(clk_set_parent
);
500 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
502 /*------------------------------------------------------------------------*/
504 #ifdef CONFIG_DEBUG_FS
506 static int at91_clk_show(struct seq_file
*s
, void *unused
)
511 seq_printf(s
, "SCSR = %8x\n", scsr
= at91_sys_read(AT91_PMC_SCSR
));
512 seq_printf(s
, "PCSR = %8x\n", pcsr
= at91_sys_read(AT91_PMC_PCSR
));
514 seq_printf(s
, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR
));
515 seq_printf(s
, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR
));
516 seq_printf(s
, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR
));
517 seq_printf(s
, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR
));
519 seq_printf(s
, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR
));
520 for (i
= 0; i
< 4; i
++)
521 seq_printf(s
, "PCK%d = %8x\n", i
, at91_sys_read(AT91_PMC_PCKR(i
)));
522 seq_printf(s
, "SR = %8x\n", sr
= at91_sys_read(AT91_PMC_SR
));
526 for (i
= 0; i
< ARRAY_SIZE(clock_list
); i
++) {
528 struct clk
*clk
= clock_list
[i
];
530 if (clk
->mode
== pmc_sys_mode
)
531 state
= (scsr
& clk
->pmc_mask
) ? "on" : "off";
532 else if (clk
->mode
== pmc_periph_mode
)
533 state
= (pcsr
& clk
->pmc_mask
) ? "on" : "off";
534 else if (clk
->pmc_mask
)
535 state
= (sr
& clk
->pmc_mask
) ? "on" : "off";
536 else if (clk
== &clk32k
|| clk
== &main_clk
)
541 seq_printf(s
, "%-10s users=%2d %-3s %9ld Hz %s\n",
542 clk
->name
, clk
->users
, state
, clk_get_rate(clk
),
543 clk
->parent
? clk
->parent
->name
: "");
548 static int at91_clk_open(struct inode
*inode
, struct file
*file
)
550 return single_open(file
, at91_clk_show
, NULL
);
553 static struct file_operations at91_clk_operations
= {
554 .open
= at91_clk_open
,
557 .release
= single_release
,
560 static int __init
at91_clk_debugfs_init(void)
562 /* /sys/kernel/debug/at91_clk */
563 (void) debugfs_create_file("at91_clk", S_IFREG
| S_IRUGO
, NULL
, NULL
, &at91_clk_operations
);
567 postcore_initcall(at91_clk_debugfs_init
);
571 /*------------------------------------------------------------------------*/
573 static u32 __init
at91_pll_rate(struct clk
*pll
, u32 freq
, u32 reg
)
578 mul
= (reg
>> 16) & 0x7ff;
588 static u32 __init
at91_usb_rate(struct clk
*pll
, u32 freq
, u32 reg
)
590 if (pll
== &pllb
&& (reg
& AT91_PMC_USB96M
))
596 static unsigned __init
at91_pll_calc(unsigned main_freq
, unsigned out_freq
)
598 unsigned i
, div
= 0, mul
= 0, diff
= 1 << 30;
599 unsigned ret
= (out_freq
> 155000000) ? 0xbe00 : 0x3e00;
601 /* PLL output max 240 MHz (or 180 MHz per errata) */
602 if (out_freq
> 240000000)
605 for (i
= 1; i
< 256; i
++) {
607 unsigned input
, mul1
;
610 * PLL input between 1MHz and 32MHz per spec, but lower
611 * frequences seem necessary in some cases so allow 100K.
613 input
= main_freq
/ i
;
616 if (input
> 32000000)
619 mul1
= out_freq
/ input
;
625 diff1
= out_freq
- input
* mul1
;
636 if (i
== 256 && diff
> (out_freq
>> 5))
638 return ret
| ((mul
- 1) << 16) | div
;
645 * Several unused clocks may be active. Turn them off.
647 static void at91_periphclk_reset(void)
652 reg
= at91_sys_read(AT91_PMC_PCSR
);
654 for (i
= 0; i
< ARRAY_SIZE(clock_list
); i
++) {
655 struct clk
*clk
= clock_list
[i
];
657 if (clk
->mode
!= pmc_periph_mode
)
661 reg
&= ~clk
->pmc_mask
;
664 at91_sys_write(AT91_PMC_PCDR
, reg
);
667 int __init
at91_clock_init(unsigned long main_clock
)
669 unsigned tmp
, freq
, mckr
;
671 spin_lock_init(&clk_lock
);
674 * When the bootloader initialized the main oscillator correctly,
675 * there's no problem using the cycle counter. But if it didn't,
676 * or when using oscillator bypass mode, we must be told the speed
681 tmp
= at91_sys_read(AT91_CKGR_MCFR
);
682 } while (!(tmp
& AT91_PMC_MAINRDY
));
683 main_clock
= (tmp
& AT91_PMC_MAINF
) * (AT91_SLOW_CLOCK
/ 16);
685 main_clk
.rate_hz
= main_clock
;
687 /* report if PLLA is more than mildly overclocked */
688 plla
.rate_hz
= at91_pll_rate(&plla
, main_clock
, at91_sys_read(AT91_CKGR_PLLAR
));
689 if (plla
.rate_hz
> 209000000)
690 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla
.rate_hz
/ 1000000);
693 * USB clock init: choose 48 MHz PLLB value, turn all clocks off,
694 * disable 48MHz clock during usb peripheral suspend.
696 * REVISIT: assumes MCK doesn't derive from PLLB!
698 at91_pllb_usb_init
= at91_pll_calc(main_clock
, 48000000 * 2) | AT91_PMC_USB96M
;
699 pllb
.rate_hz
= at91_pll_rate(&pllb
, main_clock
, at91_pllb_usb_init
);
700 at91_sys_write(AT91_PMC_SCDR
, AT91_PMC_UHP
| AT91_PMC_UDP
);
701 at91_sys_write(AT91_CKGR_PLLBR
, 0);
702 at91_sys_write(AT91_PMC_SCER
, AT91_PMC_MCKUDP
);
704 udpck
.rate_hz
= at91_usb_rate(&pllb
, pllb
.rate_hz
, at91_pllb_usb_init
);
705 uhpck
.rate_hz
= at91_usb_rate(&pllb
, pllb
.rate_hz
, at91_pllb_usb_init
);
708 * MCK and CPU derive from one of those primary clocks.
709 * For now, assume this parentage won't change.
711 mckr
= at91_sys_read(AT91_PMC_MCKR
);
712 mck
.parent
= clock_list
[mckr
& AT91_PMC_CSS
];
713 freq
= mck
.parent
->rate_hz
;
714 freq
/= (1 << ((mckr
>> 2) & 3)); /* prescale */
715 mck
.rate_hz
= freq
/ (1 + ((mckr
>> 8) & 3)); /* mdiv */
717 /* MCK and CPU clock are "always on" */
720 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
721 freq
/ 1000000, (unsigned) mck
.rate_hz
/ 1000000,
722 (unsigned) main_clock
/ 1000000,
723 ((unsigned) main_clock
% 1000000) / 1000);
725 /* FIXME get rid of master_clock global */
726 at91_master_clock
= mck
.rate_hz
;
728 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
729 /* establish PCK0..PCK3 parentage */
730 for (tmp
= 0; tmp
< ARRAY_SIZE(clock_list
); tmp
++) {
731 struct clk
*clk
= clock_list
[tmp
], *parent
;
734 if (!clk
->programmable
)
737 pckr
= at91_sys_read(AT91_PMC_PCKR(clk
->id
));
738 parent
= clock_list
[pckr
& AT91_PMC_CSS
];
739 clk
->parent
= parent
;
740 clk
->rate_hz
= parent
->rate_hz
/ (1 << ((pckr
>> 2) & 3));
742 if (clk
->users
== 0) {
743 /* not being used, so switch it off */
744 at91_sys_write(AT91_PMC_SCDR
, clk
->pmc_mask
);
748 /* disable all programmable clocks */
749 at91_sys_write(AT91_PMC_SCDR
, AT91_PMC_PCK0
| AT91_PMC_PCK1
| AT91_PMC_PCK2
| AT91_PMC_PCK3
);
752 /* enable the PIO clocks */
753 clk_enable(&pioA_clk
);
754 clk_enable(&pioB_clk
);
755 clk_enable(&pioC_clk
);
756 clk_enable(&pioD_clk
);
758 /* disable all other unused peripheral clocks */
759 at91_periphclk_reset();