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avr32: Enable SDRAMC clock at startup
[linux-2.6/pdupreez.git] / arch / avr32 / mach-at32ap / at32ap700x.c
blob3ee5e7278790c10836adbc3b272dda9a453411f4
1 /*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/fb.h>
11 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/spi/spi.h>
15 #include <linux/usb/atmel_usba_udc.h>
16
17 #include <asm/io.h>
18 #include <asm/irq.h>
19
20 #include <asm/arch/at32ap700x.h>
21 #include <asm/arch/board.h>
22 #include <asm/arch/portmux.h>
23
24 #include <video/atmel_lcdc.h>
25
26 #include "clock.h"
27 #include "hmatrix.h"
28 #include "pio.h"
29 #include "pm.h"
30
31
32 #define PBMEM(base) \
33 { \
34 .start = base, \
35 .end = base + 0x3ff, \
36 .flags = IORESOURCE_MEM, \
37 }
38 #define IRQ(num) \
39 { \
40 .start = num, \
41 .end = num, \
42 .flags = IORESOURCE_IRQ, \
43 }
44 #define NAMED_IRQ(num, _name) \
45 { \
46 .start = num, \
47 .end = num, \
48 .name = _name, \
49 .flags = IORESOURCE_IRQ, \
50 }
51
52 /* REVISIT these assume *every* device supports DMA, but several
53 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
54 */
55 #define DEFINE_DEV(_name, _id) \
56 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
57 static struct platform_device _name##_id##_device = { \
58 .name = #_name, \
59 .id = _id, \
60 .dev = { \
61 .dma_mask = &_name##_id##_dma_mask, \
62 .coherent_dma_mask = DMA_32BIT_MASK, \
63 }, \
64 .resource = _name##_id##_resource, \
65 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
66 }
67 #define DEFINE_DEV_DATA(_name, _id) \
68 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
69 static struct platform_device _name##_id##_device = { \
70 .name = #_name, \
71 .id = _id, \
72 .dev = { \
73 .dma_mask = &_name##_id##_dma_mask, \
74 .platform_data = &_name##_id##_data, \
75 .coherent_dma_mask = DMA_32BIT_MASK, \
76 }, \
77 .resource = _name##_id##_resource, \
78 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
79 }
80
81 #define select_peripheral(pin, periph, flags) \
82 at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
83
84 #define DEV_CLK(_name, devname, bus, _index) \
85 static struct clk devname##_##_name = { \
86 .name = #_name, \
87 .dev = &devname##_device.dev, \
88 .parent = &bus##_clk, \
89 .mode = bus##_clk_mode, \
90 .get_rate = bus##_clk_get_rate, \
91 .index = _index, \
92 }
93
94 static DEFINE_SPINLOCK(pm_lock);
95
96 static struct clk osc0;
97 static struct clk osc1;
98
99 static unsigned long osc_get_rate(struct clk *clk)
100 {
101 return at32_board_osc_rates[clk->index];
102 }
103
104 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
105 {
106 unsigned long div, mul, rate;
107
108 div = PM_BFEXT(PLLDIV, control) + 1;
109 mul = PM_BFEXT(PLLMUL, control) + 1;
110
111 rate = clk->parent->get_rate(clk->parent);
112 rate = (rate + div / 2) / div;
113 rate *= mul;
114
115 return rate;
116 }
117
118 static long pll_set_rate(struct clk *clk, unsigned long rate,
119 u32 *pll_ctrl)
120 {
121 unsigned long mul;
122 unsigned long mul_best_fit = 0;
123 unsigned long div;
124 unsigned long div_min;
125 unsigned long div_max;
126 unsigned long div_best_fit = 0;
127 unsigned long base;
128 unsigned long pll_in;
129 unsigned long actual = 0;
130 unsigned long rate_error;
131 unsigned long rate_error_prev = ~0UL;
132 u32 ctrl;
133
134 /* Rate must be between 80 MHz and 200 Mhz. */
135 if (rate < 80000000UL || rate > 200000000UL)
136 return -EINVAL;
137
138 ctrl = PM_BF(PLLOPT, 4);
139 base = clk->parent->get_rate(clk->parent);
140
141 /* PLL input frequency must be between 6 MHz and 32 MHz. */
142 div_min = DIV_ROUND_UP(base, 32000000UL);
143 div_max = base / 6000000UL;
144
145 if (div_max < div_min)
146 return -EINVAL;
147
148 for (div = div_min; div <= div_max; div++) {
149 pll_in = (base + div / 2) / div;
150 mul = (rate + pll_in / 2) / pll_in;
151
152 if (mul == 0)
153 continue;
154
155 actual = pll_in * mul;
156 rate_error = abs(actual - rate);
157
158 if (rate_error < rate_error_prev) {
159 mul_best_fit = mul;
160 div_best_fit = div;
161 rate_error_prev = rate_error;
162 }
163
164 if (rate_error == 0)
165 break;
166 }
167
168 if (div_best_fit == 0)
169 return -EINVAL;
170
171 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
172 ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
173 ctrl |= PM_BF(PLLCOUNT, 16);
174
175 if (clk->parent == &osc1)
176 ctrl |= PM_BIT(PLLOSC);
177
178 *pll_ctrl = ctrl;
179
180 return actual;
181 }
182
183 static unsigned long pll0_get_rate(struct clk *clk)
184 {
185 u32 control;
186
187 control = pm_readl(PLL0);
188
189 return pll_get_rate(clk, control);
190 }
191
192 static void pll1_mode(struct clk *clk, int enabled)
193 {
194 unsigned long timeout;
195 u32 status;
196 u32 ctrl;
197
198 ctrl = pm_readl(PLL1);
199
200 if (enabled) {
201 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
202 pr_debug("clk %s: failed to enable, rate not set\n",
203 clk->name);
204 return;
205 }
206
207 ctrl |= PM_BIT(PLLEN);
208 pm_writel(PLL1, ctrl);
209
210 /* Wait for PLL lock. */
211 for (timeout = 10000; timeout; timeout--) {
212 status = pm_readl(ISR);
213 if (status & PM_BIT(LOCK1))
214 break;
215 udelay(10);
216 }
217
218 if (!(status & PM_BIT(LOCK1)))
219 printk(KERN_ERR "clk %s: timeout waiting for lock\n",
220 clk->name);
221 } else {
222 ctrl &= ~PM_BIT(PLLEN);
223 pm_writel(PLL1, ctrl);
224 }
225 }
226
227 static unsigned long pll1_get_rate(struct clk *clk)
228 {
229 u32 control;
230
231 control = pm_readl(PLL1);
232
233 return pll_get_rate(clk, control);
234 }
235
236 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
237 {
238 u32 ctrl = 0;
239 unsigned long actual_rate;
240
241 actual_rate = pll_set_rate(clk, rate, &ctrl);
242
243 if (apply) {
244 if (actual_rate != rate)
245 return -EINVAL;
246 if (clk->users > 0)
247 return -EBUSY;
248 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
249 clk->name, rate, actual_rate);
250 pm_writel(PLL1, ctrl);
251 }
252
253 return actual_rate;
254 }
255
256 static int pll1_set_parent(struct clk *clk, struct clk *parent)
257 {
258 u32 ctrl;
259
260 if (clk->users > 0)
261 return -EBUSY;
262
263 ctrl = pm_readl(PLL1);
264 WARN_ON(ctrl & PM_BIT(PLLEN));
265
266 if (parent == &osc0)
267 ctrl &= ~PM_BIT(PLLOSC);
268 else if (parent == &osc1)
269 ctrl |= PM_BIT(PLLOSC);
270 else
271 return -EINVAL;
272
273 pm_writel(PLL1, ctrl);
274 clk->parent = parent;
275
276 return 0;
277 }
278
279 /*
280 * The AT32AP7000 has five primary clock sources: One 32kHz
281 * oscillator, two crystal oscillators and two PLLs.
282 */
283 static struct clk osc32k = {
284 .name = "osc32k",
285 .get_rate = osc_get_rate,
286 .users = 1,
287 .index = 0,
288 };
289 static struct clk osc0 = {
290 .name = "osc0",
291 .get_rate = osc_get_rate,
292 .users = 1,
293 .index = 1,
294 };
295 static struct clk osc1 = {
296 .name = "osc1",
297 .get_rate = osc_get_rate,
298 .index = 2,
299 };
300 static struct clk pll0 = {
301 .name = "pll0",
302 .get_rate = pll0_get_rate,
303 .parent = &osc0,
304 };
305 static struct clk pll1 = {
306 .name = "pll1",
307 .mode = pll1_mode,
308 .get_rate = pll1_get_rate,
309 .set_rate = pll1_set_rate,
310 .set_parent = pll1_set_parent,
311 .parent = &osc0,
312 };
313
314 /*
315 * The main clock can be either osc0 or pll0. The boot loader may
316 * have chosen one for us, so we don't really know which one until we
317 * have a look at the SM.
318 */
319 static struct clk *main_clock;
320
321 /*
322 * Synchronous clocks are generated from the main clock. The clocks
323 * must satisfy the constraint
324 * fCPU >= fHSB >= fPB
325 * i.e. each clock must not be faster than its parent.
326 */
327 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
328 {
329 return main_clock->get_rate(main_clock) >> shift;
330 };
331
332 static void cpu_clk_mode(struct clk *clk, int enabled)
333 {
334 unsigned long flags;
335 u32 mask;
336
337 spin_lock_irqsave(&pm_lock, flags);
338 mask = pm_readl(CPU_MASK);
339 if (enabled)
340 mask |= 1 << clk->index;
341 else
342 mask &= ~(1 << clk->index);
343 pm_writel(CPU_MASK, mask);
344 spin_unlock_irqrestore(&pm_lock, flags);
345 }
346
347 static unsigned long cpu_clk_get_rate(struct clk *clk)
348 {
349 unsigned long cksel, shift = 0;
350
351 cksel = pm_readl(CKSEL);
352 if (cksel & PM_BIT(CPUDIV))
353 shift = PM_BFEXT(CPUSEL, cksel) + 1;
354
355 return bus_clk_get_rate(clk, shift);
356 }
357
358 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
359 {
360 u32 control;
361 unsigned long parent_rate, child_div, actual_rate, div;
362
363 parent_rate = clk->parent->get_rate(clk->parent);
364 control = pm_readl(CKSEL);
365
366 if (control & PM_BIT(HSBDIV))
367 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
368 else
369 child_div = 1;
370
371 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
372 actual_rate = parent_rate;
373 control &= ~PM_BIT(CPUDIV);
374 } else {
375 unsigned int cpusel;
376 div = (parent_rate + rate / 2) / rate;
377 if (div > child_div)
378 div = child_div;
379 cpusel = (div > 1) ? (fls(div) - 2) : 0;
380 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
381 actual_rate = parent_rate / (1 << (cpusel + 1));
382 }
383
384 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
385 clk->name, rate, actual_rate);
386
387 if (apply)
388 pm_writel(CKSEL, control);
389
390 return actual_rate;
391 }
392
393 static void hsb_clk_mode(struct clk *clk, int enabled)
394 {
395 unsigned long flags;
396 u32 mask;
397
398 spin_lock_irqsave(&pm_lock, flags);
399 mask = pm_readl(HSB_MASK);
400 if (enabled)
401 mask |= 1 << clk->index;
402 else
403 mask &= ~(1 << clk->index);
404 pm_writel(HSB_MASK, mask);
405 spin_unlock_irqrestore(&pm_lock, flags);
406 }
407
408 static unsigned long hsb_clk_get_rate(struct clk *clk)
409 {
410 unsigned long cksel, shift = 0;
411
412 cksel = pm_readl(CKSEL);
413 if (cksel & PM_BIT(HSBDIV))
414 shift = PM_BFEXT(HSBSEL, cksel) + 1;
415
416 return bus_clk_get_rate(clk, shift);
417 }
418
419 static void pba_clk_mode(struct clk *clk, int enabled)
420 {
421 unsigned long flags;
422 u32 mask;
423
424 spin_lock_irqsave(&pm_lock, flags);
425 mask = pm_readl(PBA_MASK);
426 if (enabled)
427 mask |= 1 << clk->index;
428 else
429 mask &= ~(1 << clk->index);
430 pm_writel(PBA_MASK, mask);
431 spin_unlock_irqrestore(&pm_lock, flags);
432 }
433
434 static unsigned long pba_clk_get_rate(struct clk *clk)
435 {
436 unsigned long cksel, shift = 0;
437
438 cksel = pm_readl(CKSEL);
439 if (cksel & PM_BIT(PBADIV))
440 shift = PM_BFEXT(PBASEL, cksel) + 1;
441
442 return bus_clk_get_rate(clk, shift);
443 }
444
445 static void pbb_clk_mode(struct clk *clk, int enabled)
446 {
447 unsigned long flags;
448 u32 mask;
449
450 spin_lock_irqsave(&pm_lock, flags);
451 mask = pm_readl(PBB_MASK);
452 if (enabled)
453 mask |= 1 << clk->index;
454 else
455 mask &= ~(1 << clk->index);
456 pm_writel(PBB_MASK, mask);
457 spin_unlock_irqrestore(&pm_lock, flags);
458 }
459
460 static unsigned long pbb_clk_get_rate(struct clk *clk)
461 {
462 unsigned long cksel, shift = 0;
463
464 cksel = pm_readl(CKSEL);
465 if (cksel & PM_BIT(PBBDIV))
466 shift = PM_BFEXT(PBBSEL, cksel) + 1;
467
468 return bus_clk_get_rate(clk, shift);
469 }
470
471 static struct clk cpu_clk = {
472 .name = "cpu",
473 .get_rate = cpu_clk_get_rate,
474 .set_rate = cpu_clk_set_rate,
475 .users = 1,
476 };
477 static struct clk hsb_clk = {
478 .name = "hsb",
479 .parent = &cpu_clk,
480 .get_rate = hsb_clk_get_rate,
481 };
482 static struct clk pba_clk = {
483 .name = "pba",
484 .parent = &hsb_clk,
485 .mode = hsb_clk_mode,
486 .get_rate = pba_clk_get_rate,
487 .index = 1,
488 };
489 static struct clk pbb_clk = {
490 .name = "pbb",
491 .parent = &hsb_clk,
492 .mode = hsb_clk_mode,
493 .get_rate = pbb_clk_get_rate,
494 .users = 1,
495 .index = 2,
496 };
497
498 /* --------------------------------------------------------------------
499 * Generic Clock operations
500 * -------------------------------------------------------------------- */
501
502 static void genclk_mode(struct clk *clk, int enabled)
503 {
504 u32 control;
505
506 control = pm_readl(GCCTRL(clk->index));
507 if (enabled)
508 control |= PM_BIT(CEN);
509 else
510 control &= ~PM_BIT(CEN);
511 pm_writel(GCCTRL(clk->index), control);
512 }
513
514 static unsigned long genclk_get_rate(struct clk *clk)
515 {
516 u32 control;
517 unsigned long div = 1;
518
519 control = pm_readl(GCCTRL(clk->index));
520 if (control & PM_BIT(DIVEN))
521 div = 2 * (PM_BFEXT(DIV, control) + 1);
522
523 return clk->parent->get_rate(clk->parent) / div;
524 }
525
526 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
527 {
528 u32 control;
529 unsigned long parent_rate, actual_rate, div;
530
531 parent_rate = clk->parent->get_rate(clk->parent);
532 control = pm_readl(GCCTRL(clk->index));
533
534 if (rate > 3 * parent_rate / 4) {
535 actual_rate = parent_rate;
536 control &= ~PM_BIT(DIVEN);
537 } else {
538 div = (parent_rate + rate) / (2 * rate) - 1;
539 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
540 actual_rate = parent_rate / (2 * (div + 1));
541 }
542
543 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
544 clk->name, rate, actual_rate);
545
546 if (apply)
547 pm_writel(GCCTRL(clk->index), control);
548
549 return actual_rate;
550 }
551
552 int genclk_set_parent(struct clk *clk, struct clk *parent)
553 {
554 u32 control;
555
556 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
557 clk->name, parent->name, clk->parent->name);
558
559 control = pm_readl(GCCTRL(clk->index));
560
561 if (parent == &osc1 || parent == &pll1)
562 control |= PM_BIT(OSCSEL);
563 else if (parent == &osc0 || parent == &pll0)
564 control &= ~PM_BIT(OSCSEL);
565 else
566 return -EINVAL;
567
568 if (parent == &pll0 || parent == &pll1)
569 control |= PM_BIT(PLLSEL);
570 else
571 control &= ~PM_BIT(PLLSEL);
572
573 pm_writel(GCCTRL(clk->index), control);
574 clk->parent = parent;
575
576 return 0;
577 }
578
579 static void __init genclk_init_parent(struct clk *clk)
580 {
581 u32 control;
582 struct clk *parent;
583
584 BUG_ON(clk->index > 7);
585
586 control = pm_readl(GCCTRL(clk->index));
587 if (control & PM_BIT(OSCSEL))
588 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
589 else
590 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
591
592 clk->parent = parent;
593 }
594
595 /* --------------------------------------------------------------------
596 * System peripherals
597 * -------------------------------------------------------------------- */
598 static struct resource at32_pm0_resource[] = {
599 {
600 .start = 0xfff00000,
601 .end = 0xfff0007f,
602 .flags = IORESOURCE_MEM,
603 },
604 IRQ(20),
605 };
606
607 static struct resource at32ap700x_rtc0_resource[] = {
608 {
609 .start = 0xfff00080,
610 .end = 0xfff000af,
611 .flags = IORESOURCE_MEM,
612 },
613 IRQ(21),
614 };
615
616 static struct resource at32_wdt0_resource[] = {
617 {
618 .start = 0xfff000b0,
619 .end = 0xfff000cf,
620 .flags = IORESOURCE_MEM,
621 },
622 };
623
624 static struct resource at32_eic0_resource[] = {
625 {
626 .start = 0xfff00100,
627 .end = 0xfff0013f,
628 .flags = IORESOURCE_MEM,
629 },
630 IRQ(19),
631 };
632
633 DEFINE_DEV(at32_pm, 0);
634 DEFINE_DEV(at32ap700x_rtc, 0);
635 DEFINE_DEV(at32_wdt, 0);
636 DEFINE_DEV(at32_eic, 0);
637
638 /*
639 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
640 * is always running.
641 */
642 static struct clk at32_pm_pclk = {
643 .name = "pclk",
644 .dev = &at32_pm0_device.dev,
645 .parent = &pbb_clk,
646 .mode = pbb_clk_mode,
647 .get_rate = pbb_clk_get_rate,
648 .users = 1,
649 .index = 0,
650 };
651
652 static struct resource intc0_resource[] = {
653 PBMEM(0xfff00400),
654 };
655 struct platform_device at32_intc0_device = {
656 .name = "intc",
657 .id = 0,
658 .resource = intc0_resource,
659 .num_resources = ARRAY_SIZE(intc0_resource),
660 };
661 DEV_CLK(pclk, at32_intc0, pbb, 1);
662
663 static struct clk ebi_clk = {
664 .name = "ebi",
665 .parent = &hsb_clk,
666 .mode = hsb_clk_mode,
667 .get_rate = hsb_clk_get_rate,
668 .users = 1,
669 };
670 static struct clk hramc_clk = {
671 .name = "hramc",
672 .parent = &hsb_clk,
673 .mode = hsb_clk_mode,
674 .get_rate = hsb_clk_get_rate,
675 .users = 1,
676 .index = 3,
677 };
678 static struct clk sdramc_clk = {
679 .name = "sdramc_clk",
680 .parent = &pbb_clk,
681 .mode = pbb_clk_mode,
682 .get_rate = pbb_clk_get_rate,
683 .users = 1,
684 .index = 14,
685 };
686
687 static struct resource smc0_resource[] = {
688 PBMEM(0xfff03400),
689 };
690 DEFINE_DEV(smc, 0);
691 DEV_CLK(pclk, smc0, pbb, 13);
692 DEV_CLK(mck, smc0, hsb, 0);
693
694 static struct platform_device pdc_device = {
695 .name = "pdc",
696 .id = 0,
697 };
698 DEV_CLK(hclk, pdc, hsb, 4);
699 DEV_CLK(pclk, pdc, pba, 16);
700
701 static struct clk pico_clk = {
702 .name = "pico",
703 .parent = &cpu_clk,
704 .mode = cpu_clk_mode,
705 .get_rate = cpu_clk_get_rate,
706 .users = 1,
707 };
708
709 static struct resource dmaca0_resource[] = {
710 {
711 .start = 0xff200000,
712 .end = 0xff20ffff,
713 .flags = IORESOURCE_MEM,
714 },
715 IRQ(2),
716 };
717 DEFINE_DEV(dmaca, 0);
718 DEV_CLK(hclk, dmaca0, hsb, 10);
719
720 /* --------------------------------------------------------------------
721 * HMATRIX
722 * -------------------------------------------------------------------- */
723
724 static struct clk hmatrix_clk = {
725 .name = "hmatrix_clk",
726 .parent = &pbb_clk,
727 .mode = pbb_clk_mode,
728 .get_rate = pbb_clk_get_rate,
729 .index = 2,
730 .users = 1,
731 };
732 #define HMATRIX_BASE ((void __iomem *)0xfff00800)
733
734 #define hmatrix_readl(reg) \
735 __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
736 #define hmatrix_writel(reg,value) \
737 __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
738
739 /*
740 * Set bits in the HMATRIX Special Function Register (SFR) used by the
741 * External Bus Interface (EBI). This can be used to enable special
742 * features like CompactFlash support, NAND Flash support, etc. on
743 * certain chipselects.
744 */
745 static inline void set_ebi_sfr_bits(u32 mask)
746 {
747 u32 sfr;
748
749 clk_enable(&hmatrix_clk);
750 sfr = hmatrix_readl(SFR4);
751 sfr |= mask;
752 hmatrix_writel(SFR4, sfr);
753 clk_disable(&hmatrix_clk);
754 }
755
756 /* --------------------------------------------------------------------
757 * Timer/Counter (TC)
758 * -------------------------------------------------------------------- */
759
760 static struct resource at32_tcb0_resource[] = {
761 PBMEM(0xfff00c00),
762 IRQ(22),
763 };
764 static struct platform_device at32_tcb0_device = {
765 .name = "atmel_tcb",
766 .id = 0,
767 .resource = at32_tcb0_resource,
768 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
769 };
770 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
771
772 static struct resource at32_tcb1_resource[] = {
773 PBMEM(0xfff01000),
774 IRQ(23),
775 };
776 static struct platform_device at32_tcb1_device = {
777 .name = "atmel_tcb",
778 .id = 1,
779 .resource = at32_tcb1_resource,
780 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
781 };
782 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
783
784 /* --------------------------------------------------------------------
785 * PIO
786 * -------------------------------------------------------------------- */
787
788 static struct resource pio0_resource[] = {
789 PBMEM(0xffe02800),
790 IRQ(13),
791 };
792 DEFINE_DEV(pio, 0);
793 DEV_CLK(mck, pio0, pba, 10);
794
795 static struct resource pio1_resource[] = {
796 PBMEM(0xffe02c00),
797 IRQ(14),
798 };
799 DEFINE_DEV(pio, 1);
800 DEV_CLK(mck, pio1, pba, 11);
801
802 static struct resource pio2_resource[] = {
803 PBMEM(0xffe03000),
804 IRQ(15),
805 };
806 DEFINE_DEV(pio, 2);
807 DEV_CLK(mck, pio2, pba, 12);
808
809 static struct resource pio3_resource[] = {
810 PBMEM(0xffe03400),
811 IRQ(16),
812 };
813 DEFINE_DEV(pio, 3);
814 DEV_CLK(mck, pio3, pba, 13);
815
816 static struct resource pio4_resource[] = {
817 PBMEM(0xffe03800),
818 IRQ(17),
819 };
820 DEFINE_DEV(pio, 4);
821 DEV_CLK(mck, pio4, pba, 14);
822
823 void __init at32_add_system_devices(void)
824 {
825 platform_device_register(&at32_pm0_device);
826 platform_device_register(&at32_intc0_device);
827 platform_device_register(&at32ap700x_rtc0_device);
828 platform_device_register(&at32_wdt0_device);
829 platform_device_register(&at32_eic0_device);
830 platform_device_register(&smc0_device);
831 platform_device_register(&pdc_device);
832 platform_device_register(&dmaca0_device);
833
834 platform_device_register(&at32_tcb0_device);
835 platform_device_register(&at32_tcb1_device);
836
837 platform_device_register(&pio0_device);
838 platform_device_register(&pio1_device);
839 platform_device_register(&pio2_device);
840 platform_device_register(&pio3_device);
841 platform_device_register(&pio4_device);
842 }
843
844 /* --------------------------------------------------------------------
845 * PSIF
846 * -------------------------------------------------------------------- */
847 static struct resource atmel_psif0_resource[] __initdata = {
848 {
849 .start = 0xffe03c00,
850 .end = 0xffe03cff,
851 .flags = IORESOURCE_MEM,
852 },
853 IRQ(18),
854 };
855 static struct clk atmel_psif0_pclk = {
856 .name = "pclk",
857 .parent = &pba_clk,
858 .mode = pba_clk_mode,
859 .get_rate = pba_clk_get_rate,
860 .index = 15,
861 };
862
863 static struct resource atmel_psif1_resource[] __initdata = {
864 {
865 .start = 0xffe03d00,
866 .end = 0xffe03dff,
867 .flags = IORESOURCE_MEM,
868 },
869 IRQ(18),
870 };
871 static struct clk atmel_psif1_pclk = {
872 .name = "pclk",
873 .parent = &pba_clk,
874 .mode = pba_clk_mode,
875 .get_rate = pba_clk_get_rate,
876 .index = 15,
877 };
878
879 struct platform_device *__init at32_add_device_psif(unsigned int id)
880 {
881 struct platform_device *pdev;
882
883 if (!(id == 0 || id == 1))
884 return NULL;
885
886 pdev = platform_device_alloc("atmel_psif", id);
887 if (!pdev)
888 return NULL;
889
890 switch (id) {
891 case 0:
892 if (platform_device_add_resources(pdev, atmel_psif0_resource,
893 ARRAY_SIZE(atmel_psif0_resource)))
894 goto err_add_resources;
895 atmel_psif0_pclk.dev = &pdev->dev;
896 select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
897 select_peripheral(PA(9), PERIPH_A, 0); /* DATA */
898 break;
899 case 1:
900 if (platform_device_add_resources(pdev, atmel_psif1_resource,
901 ARRAY_SIZE(atmel_psif1_resource)))
902 goto err_add_resources;
903 atmel_psif1_pclk.dev = &pdev->dev;
904 select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
905 select_peripheral(PB(12), PERIPH_A, 0); /* DATA */
906 break;
907 default:
908 return NULL;
909 }
910
911 platform_device_add(pdev);
912 return pdev;
913
914 err_add_resources:
915 platform_device_put(pdev);
916 return NULL;
917 }
918
919 /* --------------------------------------------------------------------
920 * USART
921 * -------------------------------------------------------------------- */
922
923 static struct atmel_uart_data atmel_usart0_data = {
924 .use_dma_tx = 1,
925 .use_dma_rx = 1,
926 };
927 static struct resource atmel_usart0_resource[] = {
928 PBMEM(0xffe00c00),
929 IRQ(6),
930 };
931 DEFINE_DEV_DATA(atmel_usart, 0);
932 DEV_CLK(usart, atmel_usart0, pba, 3);
933
934 static struct atmel_uart_data atmel_usart1_data = {
935 .use_dma_tx = 1,
936 .use_dma_rx = 1,
937 };
938 static struct resource atmel_usart1_resource[] = {
939 PBMEM(0xffe01000),
940 IRQ(7),
941 };
942 DEFINE_DEV_DATA(atmel_usart, 1);
943 DEV_CLK(usart, atmel_usart1, pba, 4);
944
945 static struct atmel_uart_data atmel_usart2_data = {
946 .use_dma_tx = 1,
947 .use_dma_rx = 1,
948 };
949 static struct resource atmel_usart2_resource[] = {
950 PBMEM(0xffe01400),
951 IRQ(8),
952 };
953 DEFINE_DEV_DATA(atmel_usart, 2);
954 DEV_CLK(usart, atmel_usart2, pba, 5);
955
956 static struct atmel_uart_data atmel_usart3_data = {
957 .use_dma_tx = 1,
958 .use_dma_rx = 1,
959 };
960 static struct resource atmel_usart3_resource[] = {
961 PBMEM(0xffe01800),
962 IRQ(9),
963 };
964 DEFINE_DEV_DATA(atmel_usart, 3);
965 DEV_CLK(usart, atmel_usart3, pba, 6);
966
967 static inline void configure_usart0_pins(void)
968 {
969 select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
970 select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
971 }
972
973 static inline void configure_usart1_pins(void)
974 {
975 select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
976 select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
977 }
978
979 static inline void configure_usart2_pins(void)
980 {
981 select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
982 select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
983 }
984
985 static inline void configure_usart3_pins(void)
986 {
987 select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
988 select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
989 }
990
991 static struct platform_device *__initdata at32_usarts[4];
992
993 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
994 {
995 struct platform_device *pdev;
996
997 switch (hw_id) {
998 case 0:
999 pdev = &atmel_usart0_device;
1000 configure_usart0_pins();
1001 break;
1002 case 1:
1003 pdev = &atmel_usart1_device;
1004 configure_usart1_pins();
1005 break;
1006 case 2:
1007 pdev = &atmel_usart2_device;
1008 configure_usart2_pins();
1009 break;
1010 case 3:
1011 pdev = &atmel_usart3_device;
1012 configure_usart3_pins();
1013 break;
1014 default:
1015 return;
1016 }
1017
1018 if (PXSEG(pdev->resource[0].start) == P4SEG) {
1019 /* Addresses in the P4 segment are permanently mapped 1:1 */
1020 struct atmel_uart_data *data = pdev->dev.platform_data;
1021 data->regs = (void __iomem *)pdev->resource[0].start;
1022 }
1023
1024 pdev->id = line;
1025 at32_usarts[line] = pdev;
1026 }
1027
1028 struct platform_device *__init at32_add_device_usart(unsigned int id)
1029 {
1030 platform_device_register(at32_usarts[id]);
1031 return at32_usarts[id];
1032 }
1033
1034 struct platform_device *atmel_default_console_device;
1035
1036 void __init at32_setup_serial_console(unsigned int usart_id)
1037 {
1038 atmel_default_console_device = at32_usarts[usart_id];
1039 }
1040
1041 /* --------------------------------------------------------------------
1042 * Ethernet
1043 * -------------------------------------------------------------------- */
1044
1045 #ifdef CONFIG_CPU_AT32AP7000
1046 static struct eth_platform_data macb0_data;
1047 static struct resource macb0_resource[] = {
1048 PBMEM(0xfff01800),
1049 IRQ(25),
1050 };
1051 DEFINE_DEV_DATA(macb, 0);
1052 DEV_CLK(hclk, macb0, hsb, 8);
1053 DEV_CLK(pclk, macb0, pbb, 6);
1054
1055 static struct eth_platform_data macb1_data;
1056 static struct resource macb1_resource[] = {
1057 PBMEM(0xfff01c00),
1058 IRQ(26),
1059 };
1060 DEFINE_DEV_DATA(macb, 1);
1061 DEV_CLK(hclk, macb1, hsb, 9);
1062 DEV_CLK(pclk, macb1, pbb, 7);
1063
1064 struct platform_device *__init
1065 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1066 {
1067 struct platform_device *pdev;
1068
1069 switch (id) {
1070 case 0:
1071 pdev = &macb0_device;
1072
1073 select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
1074 select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
1075 select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
1076 select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
1077 select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
1078 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
1079 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
1080 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
1081 select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
1082 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
1083
1084 if (!data->is_rmii) {
1085 select_peripheral(PC(0), PERIPH_A, 0); /* COL */
1086 select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
1087 select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
1088 select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
1089 select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
1090 select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
1091 select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
1092 select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
1093 select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
1094 }
1095 break;
1096
1097 case 1:
1098 pdev = &macb1_device;
1099
1100 select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
1101 select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
1102 select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
1103 select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
1104 select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
1105 select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
1106 select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
1107 select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
1108 select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
1109 select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
1110
1111 if (!data->is_rmii) {
1112 select_peripheral(PC(19), PERIPH_B, 0); /* COL */
1113 select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
1114 select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
1115 select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
1116 select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
1117 select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
1118 select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
1119 select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
1120 select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
1121 }
1122 break;
1123
1124 default:
1125 return NULL;
1126 }
1127
1128 memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1129 platform_device_register(pdev);
1130
1131 return pdev;
1132 }
1133 #endif
1134
1135 /* --------------------------------------------------------------------
1136 * SPI
1137 * -------------------------------------------------------------------- */
1138 static struct resource atmel_spi0_resource[] = {
1139 PBMEM(0xffe00000),
1140 IRQ(3),
1141 };
1142 DEFINE_DEV(atmel_spi, 0);
1143 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1144
1145 static struct resource atmel_spi1_resource[] = {
1146 PBMEM(0xffe00400),
1147 IRQ(4),
1148 };
1149 DEFINE_DEV(atmel_spi, 1);
1150 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1151
1152 static void __init
1153 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1154 unsigned int n, const u8 *pins)
1155 {
1156 unsigned int pin, mode;
1157
1158 for (; n; n--, b++) {
1159 b->bus_num = bus_num;
1160 if (b->chip_select >= 4)
1161 continue;
1162 pin = (unsigned)b->controller_data;
1163 if (!pin) {
1164 pin = pins[b->chip_select];
1165 b->controller_data = (void *)pin;
1166 }
1167 mode = AT32_GPIOF_OUTPUT;
1168 if (!(b->mode & SPI_CS_HIGH))
1169 mode |= AT32_GPIOF_HIGH;
1170 at32_select_gpio(pin, mode);
1171 }
1172 }
1173
1174 struct platform_device *__init
1175 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1176 {
1177 /*
1178 * Manage the chipselects as GPIOs, normally using the same pins
1179 * the SPI controller expects; but boards can use other pins.
1180 */
1181 static u8 __initdata spi0_pins[] =
1182 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1183 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1184 static u8 __initdata spi1_pins[] =
1185 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1186 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1187 struct platform_device *pdev;
1188
1189 switch (id) {
1190 case 0:
1191 pdev = &atmel_spi0_device;
1192 /* pullup MISO so a level is always defined */
1193 select_peripheral(PA(0), PERIPH_A, AT32_GPIOF_PULLUP);
1194 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
1195 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
1196 at32_spi_setup_slaves(0, b, n, spi0_pins);
1197 break;
1198
1199 case 1:
1200 pdev = &atmel_spi1_device;
1201 /* pullup MISO so a level is always defined */
1202 select_peripheral(PB(0), PERIPH_B, AT32_GPIOF_PULLUP);
1203 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
1204 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
1205 at32_spi_setup_slaves(1, b, n, spi1_pins);
1206 break;
1207
1208 default:
1209 return NULL;
1210 }
1211
1212 spi_register_board_info(b, n);
1213 platform_device_register(pdev);
1214 return pdev;
1215 }
1216
1217 /* --------------------------------------------------------------------
1218 * TWI
1219 * -------------------------------------------------------------------- */
1220 static struct resource atmel_twi0_resource[] __initdata = {
1221 PBMEM(0xffe00800),
1222 IRQ(5),
1223 };
1224 static struct clk atmel_twi0_pclk = {
1225 .name = "twi_pclk",
1226 .parent = &pba_clk,
1227 .mode = pba_clk_mode,
1228 .get_rate = pba_clk_get_rate,
1229 .index = 2,
1230 };
1231
1232 struct platform_device *__init at32_add_device_twi(unsigned int id,
1233 struct i2c_board_info *b,
1234 unsigned int n)
1235 {
1236 struct platform_device *pdev;
1237
1238 if (id != 0)
1239 return NULL;
1240
1241 pdev = platform_device_alloc("atmel_twi", id);
1242 if (!pdev)
1243 return NULL;
1244
1245 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1246 ARRAY_SIZE(atmel_twi0_resource)))
1247 goto err_add_resources;
1248
1249 select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
1250 select_peripheral(PA(7), PERIPH_A, 0); /* SDL */
1251
1252 atmel_twi0_pclk.dev = &pdev->dev;
1253
1254 if (b)
1255 i2c_register_board_info(id, b, n);
1256
1257 platform_device_add(pdev);
1258 return pdev;
1259
1260 err_add_resources:
1261 platform_device_put(pdev);
1262 return NULL;
1263 }
1264
1265 /* --------------------------------------------------------------------
1266 * MMC
1267 * -------------------------------------------------------------------- */
1268 static struct resource atmel_mci0_resource[] __initdata = {
1269 PBMEM(0xfff02400),
1270 IRQ(28),
1271 };
1272 static struct clk atmel_mci0_pclk = {
1273 .name = "mci_clk",
1274 .parent = &pbb_clk,
1275 .mode = pbb_clk_mode,
1276 .get_rate = pbb_clk_get_rate,
1277 .index = 9,
1278 };
1279
1280 struct platform_device *__init at32_add_device_mci(unsigned int id)
1281 {
1282 struct platform_device *pdev;
1283
1284 if (id != 0)
1285 return NULL;
1286
1287 pdev = platform_device_alloc("atmel_mci", id);
1288 if (!pdev)
1289 return NULL;
1290
1291 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1292 ARRAY_SIZE(atmel_mci0_resource)))
1293 goto err_add_resources;
1294
1295 select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
1296 select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
1297 select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1298 select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1299 select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1300 select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1301
1302 atmel_mci0_pclk.dev = &pdev->dev;
1303
1304 platform_device_add(pdev);
1305 return pdev;
1306
1307 err_add_resources:
1308 platform_device_put(pdev);
1309 return NULL;
1310 }
1311
1312 /* --------------------------------------------------------------------
1313 * LCDC
1314 * -------------------------------------------------------------------- */
1315 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1316 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1317 static struct resource atmel_lcdfb0_resource[] = {
1318 {
1319 .start = 0xff000000,
1320 .end = 0xff000fff,
1321 .flags = IORESOURCE_MEM,
1322 },
1323 IRQ(1),
1324 {
1325 /* Placeholder for pre-allocated fb memory */
1326 .start = 0x00000000,
1327 .end = 0x00000000,
1328 .flags = 0,
1329 },
1330 };
1331 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1332 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1333 static struct clk atmel_lcdfb0_pixclk = {
1334 .name = "lcdc_clk",
1335 .dev = &atmel_lcdfb0_device.dev,
1336 .mode = genclk_mode,
1337 .get_rate = genclk_get_rate,
1338 .set_rate = genclk_set_rate,
1339 .set_parent = genclk_set_parent,
1340 .index = 7,
1341 };
1342
1343 struct platform_device *__init
1344 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1345 unsigned long fbmem_start, unsigned long fbmem_len,
1346 unsigned int pin_config)
1347 {
1348 struct platform_device *pdev;
1349 struct atmel_lcdfb_info *info;
1350 struct fb_monspecs *monspecs;
1351 struct fb_videomode *modedb;
1352 unsigned int modedb_size;
1353
1354 /*
1355 * Do a deep copy of the fb data, monspecs and modedb. Make
1356 * sure all allocations are done before setting up the
1357 * portmux.
1358 */
1359 monspecs = kmemdup(data->default_monspecs,
1360 sizeof(struct fb_monspecs), GFP_KERNEL);
1361 if (!monspecs)
1362 return NULL;
1363
1364 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1365 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1366 if (!modedb)
1367 goto err_dup_modedb;
1368 monspecs->modedb = modedb;
1369
1370 switch (id) {
1371 case 0:
1372 pdev = &atmel_lcdfb0_device;
1373
1374 switch (pin_config) {
1375 case 0:
1376 select_peripheral(PC(19), PERIPH_A, 0); /* CC */
1377 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1378 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1379 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1380 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
1381 select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
1382 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1383 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
1384 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
1385 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
1386 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
1387 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
1388 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1389 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1390 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1391 select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
1392 select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
1393 select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
1394 select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
1395 select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
1396 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1397 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1398 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1399 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1400 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1401 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1402 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1403 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1404 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1405 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1406 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1407 break;
1408 case 1:
1409 select_peripheral(PE(0), PERIPH_B, 0); /* CC */
1410 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1411 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1412 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1413 select_peripheral(PE(1), PERIPH_B, 0); /* DVAL */
1414 select_peripheral(PE(2), PERIPH_B, 0); /* MODE */
1415 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1416 select_peripheral(PE(3), PERIPH_B, 0); /* DATA0 */
1417 select_peripheral(PE(4), PERIPH_B, 0); /* DATA1 */
1418 select_peripheral(PE(5), PERIPH_B, 0); /* DATA2 */
1419 select_peripheral(PE(6), PERIPH_B, 0); /* DATA3 */
1420 select_peripheral(PE(7), PERIPH_B, 0); /* DATA4 */
1421 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1422 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1423 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1424 select_peripheral(PE(8), PERIPH_B, 0); /* DATA8 */
1425 select_peripheral(PE(9), PERIPH_B, 0); /* DATA9 */
1426 select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
1427 select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
1428 select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
1429 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1430 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1431 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1432 select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
1433 select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
1434 select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
1435 select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
1436 select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
1437 select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
1438 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1439 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1440 break;
1441 default:
1442 goto err_invalid_id;
1443 }
1444
1445 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1446 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1447 break;
1448
1449 default:
1450 goto err_invalid_id;
1451 }
1452
1453 if (fbmem_len) {
1454 pdev->resource[2].start = fbmem_start;
1455 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1456 pdev->resource[2].flags = IORESOURCE_MEM;
1457 }
1458
1459 info = pdev->dev.platform_data;
1460 memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1461 info->default_monspecs = monspecs;
1462
1463 platform_device_register(pdev);
1464 return pdev;
1465
1466 err_invalid_id:
1467 kfree(modedb);
1468 err_dup_modedb:
1469 kfree(monspecs);
1470 return NULL;
1471 }
1472 #endif
1473
1474 /* --------------------------------------------------------------------
1475 * PWM
1476 * -------------------------------------------------------------------- */
1477 static struct resource atmel_pwm0_resource[] __initdata = {
1478 PBMEM(0xfff01400),
1479 IRQ(24),
1480 };
1481 static struct clk atmel_pwm0_mck = {
1482 .name = "pwm_clk",
1483 .parent = &pbb_clk,
1484 .mode = pbb_clk_mode,
1485 .get_rate = pbb_clk_get_rate,
1486 .index = 5,
1487 };
1488
1489 struct platform_device *__init at32_add_device_pwm(u32 mask)
1490 {
1491 struct platform_device *pdev;
1492
1493 if (!mask)
1494 return NULL;
1495
1496 pdev = platform_device_alloc("atmel_pwm", 0);
1497 if (!pdev)
1498 return NULL;
1499
1500 if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1501 ARRAY_SIZE(atmel_pwm0_resource)))
1502 goto out_free_pdev;
1503
1504 if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1505 goto out_free_pdev;
1506
1507 if (mask & (1 << 0))
1508 select_peripheral(PA(28), PERIPH_A, 0);
1509 if (mask & (1 << 1))
1510 select_peripheral(PA(29), PERIPH_A, 0);
1511 if (mask & (1 << 2))
1512 select_peripheral(PA(21), PERIPH_B, 0);
1513 if (mask & (1 << 3))
1514 select_peripheral(PA(22), PERIPH_B, 0);
1515
1516 atmel_pwm0_mck.dev = &pdev->dev;
1517
1518 platform_device_add(pdev);
1519
1520 return pdev;
1521
1522 out_free_pdev:
1523 platform_device_put(pdev);
1524 return NULL;
1525 }
1526
1527 /* --------------------------------------------------------------------
1528 * SSC
1529 * -------------------------------------------------------------------- */
1530 static struct resource ssc0_resource[] = {
1531 PBMEM(0xffe01c00),
1532 IRQ(10),
1533 };
1534 DEFINE_DEV(ssc, 0);
1535 DEV_CLK(pclk, ssc0, pba, 7);
1536
1537 static struct resource ssc1_resource[] = {
1538 PBMEM(0xffe02000),
1539 IRQ(11),
1540 };
1541 DEFINE_DEV(ssc, 1);
1542 DEV_CLK(pclk, ssc1, pba, 8);
1543
1544 static struct resource ssc2_resource[] = {
1545 PBMEM(0xffe02400),
1546 IRQ(12),
1547 };
1548 DEFINE_DEV(ssc, 2);
1549 DEV_CLK(pclk, ssc2, pba, 9);
1550
1551 struct platform_device *__init
1552 at32_add_device_ssc(unsigned int id, unsigned int flags)
1553 {
1554 struct platform_device *pdev;
1555
1556 switch (id) {
1557 case 0:
1558 pdev = &ssc0_device;
1559 if (flags & ATMEL_SSC_RF)
1560 select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1561 if (flags & ATMEL_SSC_RK)
1562 select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1563 if (flags & ATMEL_SSC_TK)
1564 select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1565 if (flags & ATMEL_SSC_TF)
1566 select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1567 if (flags & ATMEL_SSC_TD)
1568 select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1569 if (flags & ATMEL_SSC_RD)
1570 select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1571 break;
1572 case 1:
1573 pdev = &ssc1_device;
1574 if (flags & ATMEL_SSC_RF)
1575 select_peripheral(PA(0), PERIPH_B, 0); /* RF */
1576 if (flags & ATMEL_SSC_RK)
1577 select_peripheral(PA(1), PERIPH_B, 0); /* RK */
1578 if (flags & ATMEL_SSC_TK)
1579 select_peripheral(PA(2), PERIPH_B, 0); /* TK */
1580 if (flags & ATMEL_SSC_TF)
1581 select_peripheral(PA(3), PERIPH_B, 0); /* TF */
1582 if (flags & ATMEL_SSC_TD)
1583 select_peripheral(PA(4), PERIPH_B, 0); /* TD */
1584 if (flags & ATMEL_SSC_RD)
1585 select_peripheral(PA(5), PERIPH_B, 0); /* RD */
1586 break;
1587 case 2:
1588 pdev = &ssc2_device;
1589 if (flags & ATMEL_SSC_TD)
1590 select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1591 if (flags & ATMEL_SSC_RD)
1592 select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1593 if (flags & ATMEL_SSC_TK)
1594 select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1595 if (flags & ATMEL_SSC_TF)
1596 select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1597 if (flags & ATMEL_SSC_RF)
1598 select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1599 if (flags & ATMEL_SSC_RK)
1600 select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1601 break;
1602 default:
1603 return NULL;
1604 }
1605
1606 platform_device_register(pdev);
1607 return pdev;
1608 }
1609
1610 /* --------------------------------------------------------------------
1611 * USB Device Controller
1612 * -------------------------------------------------------------------- */
1613 static struct resource usba0_resource[] __initdata = {
1614 {
1615 .start = 0xff300000,
1616 .end = 0xff3fffff,
1617 .flags = IORESOURCE_MEM,
1618 }, {
1619 .start = 0xfff03000,
1620 .end = 0xfff033ff,
1621 .flags = IORESOURCE_MEM,
1622 },
1623 IRQ(31),
1624 };
1625 static struct clk usba0_pclk = {
1626 .name = "pclk",
1627 .parent = &pbb_clk,
1628 .mode = pbb_clk_mode,
1629 .get_rate = pbb_clk_get_rate,
1630 .index = 12,
1631 };
1632 static struct clk usba0_hclk = {
1633 .name = "hclk",
1634 .parent = &hsb_clk,
1635 .mode = hsb_clk_mode,
1636 .get_rate = hsb_clk_get_rate,
1637 .index = 6,
1638 };
1639
1640 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1641 [idx] = { \
1642 .name = nam, \
1643 .index = idx, \
1644 .fifo_size = maxpkt, \
1645 .nr_banks = maxbk, \
1646 .can_dma = dma, \
1647 .can_isoc = isoc, \
1648 }
1649
1650 static struct usba_ep_data at32_usba_ep[] __initdata = {
1651 EP("ep0", 0, 64, 1, 0, 0),
1652 EP("ep1", 1, 512, 2, 1, 1),
1653 EP("ep2", 2, 512, 2, 1, 1),
1654 EP("ep3-int", 3, 64, 3, 1, 0),
1655 EP("ep4-int", 4, 64, 3, 1, 0),
1656 EP("ep5", 5, 1024, 3, 1, 1),
1657 EP("ep6", 6, 1024, 3, 1, 1),
1658 };
1659
1660 #undef EP
1661
1662 struct platform_device *__init
1663 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1664 {
1665 /*
1666 * pdata doesn't have room for any endpoints, so we need to
1667 * append room for the ones we need right after it.
1668 */
1669 struct {
1670 struct usba_platform_data pdata;
1671 struct usba_ep_data ep[7];
1672 } usba_data;
1673 struct platform_device *pdev;
1674
1675 if (id != 0)
1676 return NULL;
1677
1678 pdev = platform_device_alloc("atmel_usba_udc", 0);
1679 if (!pdev)
1680 return NULL;
1681
1682 if (platform_device_add_resources(pdev, usba0_resource,
1683 ARRAY_SIZE(usba0_resource)))
1684 goto out_free_pdev;
1685
1686 if (data)
1687 usba_data.pdata.vbus_pin = data->vbus_pin;
1688 else
1689 usba_data.pdata.vbus_pin = -EINVAL;
1690
1691 data = &usba_data.pdata;
1692 data->num_ep = ARRAY_SIZE(at32_usba_ep);
1693 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1694
1695 if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1696 goto out_free_pdev;
1697
1698 if (data->vbus_pin >= 0)
1699 at32_select_gpio(data->vbus_pin, 0);
1700
1701 usba0_pclk.dev = &pdev->dev;
1702 usba0_hclk.dev = &pdev->dev;
1703
1704 platform_device_add(pdev);
1705
1706 return pdev;
1707
1708 out_free_pdev:
1709 platform_device_put(pdev);
1710 return NULL;
1711 }
1712
1713 /* --------------------------------------------------------------------
1714 * IDE / CompactFlash
1715 * -------------------------------------------------------------------- */
1716 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1717 static struct resource at32_smc_cs4_resource[] __initdata = {
1718 {
1719 .start = 0x04000000,
1720 .end = 0x07ffffff,
1721 .flags = IORESOURCE_MEM,
1722 },
1723 IRQ(~0UL), /* Magic IRQ will be overridden */
1724 };
1725 static struct resource at32_smc_cs5_resource[] __initdata = {
1726 {
1727 .start = 0x20000000,
1728 .end = 0x23ffffff,
1729 .flags = IORESOURCE_MEM,
1730 },
1731 IRQ(~0UL), /* Magic IRQ will be overridden */
1732 };
1733
1734 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1735 unsigned int cs, unsigned int extint)
1736 {
1737 static unsigned int extint_pin_map[4] __initdata = {
1738 GPIO_PIN_PB(25),
1739 GPIO_PIN_PB(26),
1740 GPIO_PIN_PB(27),
1741 GPIO_PIN_PB(28),
1742 };
1743 static bool common_pins_initialized __initdata = false;
1744 unsigned int extint_pin;
1745 int ret;
1746
1747 if (extint >= ARRAY_SIZE(extint_pin_map))
1748 return -EINVAL;
1749 extint_pin = extint_pin_map[extint];
1750
1751 switch (cs) {
1752 case 4:
1753 ret = platform_device_add_resources(pdev,
1754 at32_smc_cs4_resource,
1755 ARRAY_SIZE(at32_smc_cs4_resource));
1756 if (ret)
1757 return ret;
1758
1759 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
1760 set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
1761 break;
1762 case 5:
1763 ret = platform_device_add_resources(pdev,
1764 at32_smc_cs5_resource,
1765 ARRAY_SIZE(at32_smc_cs5_resource));
1766 if (ret)
1767 return ret;
1768
1769 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
1770 set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
1771 break;
1772 default:
1773 return -EINVAL;
1774 }
1775
1776 if (!common_pins_initialized) {
1777 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */
1778 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */
1779 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */
1780 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */
1781 common_pins_initialized = true;
1782 }
1783
1784 at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1785
1786 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1787 pdev->resource[1].end = pdev->resource[1].start;
1788
1789 return 0;
1790 }
1791
1792 struct platform_device *__init
1793 at32_add_device_ide(unsigned int id, unsigned int extint,
1794 struct ide_platform_data *data)
1795 {
1796 struct platform_device *pdev;
1797
1798 pdev = platform_device_alloc("at32_ide", id);
1799 if (!pdev)
1800 goto fail;
1801
1802 if (platform_device_add_data(pdev, data,
1803 sizeof(struct ide_platform_data)))
1804 goto fail;
1805
1806 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1807 goto fail;
1808
1809 platform_device_add(pdev);
1810 return pdev;
1811
1812 fail:
1813 platform_device_put(pdev);
1814 return NULL;
1815 }
1816
1817 struct platform_device *__init
1818 at32_add_device_cf(unsigned int id, unsigned int extint,
1819 struct cf_platform_data *data)
1820 {
1821 struct platform_device *pdev;
1822
1823 pdev = platform_device_alloc("at32_cf", id);
1824 if (!pdev)
1825 goto fail;
1826
1827 if (platform_device_add_data(pdev, data,
1828 sizeof(struct cf_platform_data)))
1829 goto fail;
1830
1831 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1832 goto fail;
1833
1834 if (data->detect_pin != GPIO_PIN_NONE)
1835 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1836 if (data->reset_pin != GPIO_PIN_NONE)
1837 at32_select_gpio(data->reset_pin, 0);
1838 if (data->vcc_pin != GPIO_PIN_NONE)
1839 at32_select_gpio(data->vcc_pin, 0);
1840 /* READY is used as extint, so we can't select it as gpio */
1841
1842 platform_device_add(pdev);
1843 return pdev;
1844
1845 fail:
1846 platform_device_put(pdev);
1847 return NULL;
1848 }
1849 #endif
1850
1851 /* --------------------------------------------------------------------
1852 * AC97C
1853 * -------------------------------------------------------------------- */
1854 static struct resource atmel_ac97c0_resource[] __initdata = {
1855 PBMEM(0xfff02800),
1856 IRQ(29),
1857 };
1858 static struct clk atmel_ac97c0_pclk = {
1859 .name = "pclk",
1860 .parent = &pbb_clk,
1861 .mode = pbb_clk_mode,
1862 .get_rate = pbb_clk_get_rate,
1863 .index = 10,
1864 };
1865
1866 struct platform_device *__init at32_add_device_ac97c(unsigned int id)
1867 {
1868 struct platform_device *pdev;
1869
1870 if (id != 0)
1871 return NULL;
1872
1873 pdev = platform_device_alloc("atmel_ac97c", id);
1874 if (!pdev)
1875 return NULL;
1876
1877 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1878 ARRAY_SIZE(atmel_ac97c0_resource)))
1879 goto err_add_resources;
1880
1881 select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
1882 select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
1883 select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
1884 select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
1885
1886 atmel_ac97c0_pclk.dev = &pdev->dev;
1887
1888 platform_device_add(pdev);
1889 return pdev;
1890
1891 err_add_resources:
1892 platform_device_put(pdev);
1893 return NULL;
1894 }
1895
1896 /* --------------------------------------------------------------------
1897 * ABDAC
1898 * -------------------------------------------------------------------- */
1899 static struct resource abdac0_resource[] __initdata = {
1900 PBMEM(0xfff02000),
1901 IRQ(27),
1902 };
1903 static struct clk abdac0_pclk = {
1904 .name = "pclk",
1905 .parent = &pbb_clk,
1906 .mode = pbb_clk_mode,
1907 .get_rate = pbb_clk_get_rate,
1908 .index = 8,
1909 };
1910 static struct clk abdac0_sample_clk = {
1911 .name = "sample_clk",
1912 .mode = genclk_mode,
1913 .get_rate = genclk_get_rate,
1914 .set_rate = genclk_set_rate,
1915 .set_parent = genclk_set_parent,
1916 .index = 6,
1917 };
1918
1919 struct platform_device *__init at32_add_device_abdac(unsigned int id)
1920 {
1921 struct platform_device *pdev;
1922
1923 if (id != 0)
1924 return NULL;
1925
1926 pdev = platform_device_alloc("abdac", id);
1927 if (!pdev)
1928 return NULL;
1929
1930 if (platform_device_add_resources(pdev, abdac0_resource,
1931 ARRAY_SIZE(abdac0_resource)))
1932 goto err_add_resources;
1933
1934 select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
1935 select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
1936 select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
1937 select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
1938
1939 abdac0_pclk.dev = &pdev->dev;
1940 abdac0_sample_clk.dev = &pdev->dev;
1941
1942 platform_device_add(pdev);
1943 return pdev;
1944
1945 err_add_resources:
1946 platform_device_put(pdev);
1947 return NULL;
1948 }
1949
1950 /* --------------------------------------------------------------------
1951 * GCLK
1952 * -------------------------------------------------------------------- */
1953 static struct clk gclk0 = {
1954 .name = "gclk0",
1955 .mode = genclk_mode,
1956 .get_rate = genclk_get_rate,
1957 .set_rate = genclk_set_rate,
1958 .set_parent = genclk_set_parent,
1959 .index = 0,
1960 };
1961 static struct clk gclk1 = {
1962 .name = "gclk1",
1963 .mode = genclk_mode,
1964 .get_rate = genclk_get_rate,
1965 .set_rate = genclk_set_rate,
1966 .set_parent = genclk_set_parent,
1967 .index = 1,
1968 };
1969 static struct clk gclk2 = {
1970 .name = "gclk2",
1971 .mode = genclk_mode,
1972 .get_rate = genclk_get_rate,
1973 .set_rate = genclk_set_rate,
1974 .set_parent = genclk_set_parent,
1975 .index = 2,
1976 };
1977 static struct clk gclk3 = {
1978 .name = "gclk3",
1979 .mode = genclk_mode,
1980 .get_rate = genclk_get_rate,
1981 .set_rate = genclk_set_rate,
1982 .set_parent = genclk_set_parent,
1983 .index = 3,
1984 };
1985 static struct clk gclk4 = {
1986 .name = "gclk4",
1987 .mode = genclk_mode,
1988 .get_rate = genclk_get_rate,
1989 .set_rate = genclk_set_rate,
1990 .set_parent = genclk_set_parent,
1991 .index = 4,
1992 };
1993
1994 struct clk *at32_clock_list[] = {
1995 &osc32k,
1996 &osc0,
1997 &osc1,
1998 &pll0,
1999 &pll1,
2000 &cpu_clk,
2001 &hsb_clk,
2002 &pba_clk,
2003 &pbb_clk,
2004 &at32_pm_pclk,
2005 &at32_intc0_pclk,
2006 &hmatrix_clk,
2007 &ebi_clk,
2008 &hramc_clk,
2009 &sdramc_clk,
2010 &smc0_pclk,
2011 &smc0_mck,
2012 &pdc_hclk,
2013 &pdc_pclk,
2014 &dmaca0_hclk,
2015 &pico_clk,
2016 &pio0_mck,
2017 &pio1_mck,
2018 &pio2_mck,
2019 &pio3_mck,
2020 &pio4_mck,
2021 &at32_tcb0_t0_clk,
2022 &at32_tcb1_t0_clk,
2023 &atmel_psif0_pclk,
2024 &atmel_psif1_pclk,
2025 &atmel_usart0_usart,
2026 &atmel_usart1_usart,
2027 &atmel_usart2_usart,
2028 &atmel_usart3_usart,
2029 &atmel_pwm0_mck,
2030 #if defined(CONFIG_CPU_AT32AP7000)
2031 &macb0_hclk,
2032 &macb0_pclk,
2033 &macb1_hclk,
2034 &macb1_pclk,
2035 #endif
2036 &atmel_spi0_spi_clk,
2037 &atmel_spi1_spi_clk,
2038 &atmel_twi0_pclk,
2039 &atmel_mci0_pclk,
2040 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2041 &atmel_lcdfb0_hck1,
2042 &atmel_lcdfb0_pixclk,
2043 #endif
2044 &ssc0_pclk,
2045 &ssc1_pclk,
2046 &ssc2_pclk,
2047 &usba0_hclk,
2048 &usba0_pclk,
2049 &atmel_ac97c0_pclk,
2050 &abdac0_pclk,
2051 &abdac0_sample_clk,
2052 &gclk0,
2053 &gclk1,
2054 &gclk2,
2055 &gclk3,
2056 &gclk4,
2057 };
2058 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
2059
2060 void __init setup_platform(void)
2061 {
2062 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2063 int i;
2064
2065 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2066 main_clock = &pll0;
2067 cpu_clk.parent = &pll0;
2068 } else {
2069 main_clock = &osc0;
2070 cpu_clk.parent = &osc0;
2071 }
2072
2073 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2074 pll0.parent = &osc1;
2075 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2076 pll1.parent = &osc1;
2077
2078 genclk_init_parent(&gclk0);
2079 genclk_init_parent(&gclk1);
2080 genclk_init_parent(&gclk2);
2081 genclk_init_parent(&gclk3);
2082 genclk_init_parent(&gclk4);
2083 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2084 genclk_init_parent(&atmel_lcdfb0_pixclk);
2085 #endif
2086 genclk_init_parent(&abdac0_sample_clk);
2087
2088 /*
2089 * Turn on all clocks that have at least one user already, and
2090 * turn off everything else. We only do this for module
2091 * clocks, and even though it isn't particularly pretty to
2092 * check the address of the mode function, it should do the
2093 * trick...
2094 */
2095 for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
2096 struct clk *clk = at32_clock_list[i];
2097
2098 if (clk->users == 0)
2099 continue;
2100
2101 if (clk->mode == &cpu_clk_mode)
2102 cpu_mask |= 1 << clk->index;
2103 else if (clk->mode == &hsb_clk_mode)
2104 hsb_mask |= 1 << clk->index;
2105 else if (clk->mode == &pba_clk_mode)
2106 pba_mask |= 1 << clk->index;
2107 else if (clk->mode == &pbb_clk_mode)
2108 pbb_mask |= 1 << clk->index;
2109 }
2110
2111 pm_writel(CPU_MASK, cpu_mask);
2112 pm_writel(HSB_MASK, hsb_mask);
2113 pm_writel(PBA_MASK, pba_mask);
2114 pm_writel(PBB_MASK, pbb_mask);
2115
2116 /* Initialize the port muxes */
2117 at32_init_pio(&pio0_device);
2118 at32_init_pio(&pio1_device);
2119 at32_init_pio(&pio2_device);
2120 at32_init_pio(&pio3_device);
2121 at32_init_pio(&pio4_device);
2122 }
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