1 /* $Id: pgtable.h,v 1.156 2002/02/09 19:49:31 davem Exp $
2 * pgtable.h: SpitFire page table operations.
4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #ifndef _SPARC64_PGTABLE_H
9 #define _SPARC64_PGTABLE_H
11 /* This file contains the functions and defines necessary to modify and use
12 * the SpitFire page tables.
15 #include <asm-generic/pgtable-nopud.h>
17 #include <linux/compiler.h>
18 #include <asm/types.h>
19 #include <asm/spitfire.h>
21 #include <asm/system.h>
23 #include <asm/processor.h>
24 #include <asm/const.h>
26 /* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB).
27 * The page copy blockops can use 0x2000000 to 0x4000000.
28 * The TSB is mapped in the 0x4000000 to 0x6000000 range.
29 * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
30 * The vmalloc area spans 0x100000000 to 0x200000000.
31 * Since modules need to be in the lowest 32-bits of the address space,
32 * we place them right before the OBP area from 0x10000000 to 0xf0000000.
33 * There is a single static kernel PMD which maps from 0x0 to address
36 #define TLBTEMP_BASE _AC(0x0000000002000000,UL)
37 #define TSBMAP_BASE _AC(0x0000000004000000,UL)
38 #define MODULES_VADDR _AC(0x0000000010000000,UL)
39 #define MODULES_LEN _AC(0x00000000e0000000,UL)
40 #define MODULES_END _AC(0x00000000f0000000,UL)
41 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
42 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
43 #define VMALLOC_START _AC(0x0000000100000000,UL)
44 #define VMALLOC_END _AC(0x0000000200000000,UL)
46 /* XXX All of this needs to be rethought so we can take advantage
47 * XXX cheetah's full 64-bit virtual address space, ie. no more hole
48 * XXX in the middle like on spitfire. -DaveM
51 * Given a virtual address, the lowest PAGE_SHIFT bits determine offset
52 * into the page; the next higher PAGE_SHIFT-3 bits determine the pte#
53 * in the proper pagetable (the -3 is from the 8 byte ptes, and each page
54 * table is a single page long). The next higher PMD_BITS determine pmd#
55 * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2)
56 * since the pmd entries are 4 bytes, and each pmd page is a single page
57 * long). Finally, the higher few bits determine pgde#.
60 /* PMD_SHIFT determines the size of the area a second-level page
63 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
64 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
65 #define PMD_MASK (~(PMD_SIZE-1))
66 #define PMD_BITS (PAGE_SHIFT - 2)
68 /* PGDIR_SHIFT determines what a third-level page table entry can map */
69 #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
70 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
71 #define PGDIR_MASK (~(PGDIR_SIZE-1))
72 #define PGDIR_BITS (PAGE_SHIFT - 2)
76 #include <linux/sched.h>
78 /* Entries per page directory level. */
79 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
80 #define PTRS_PER_PMD (1UL << PMD_BITS)
81 #define PTRS_PER_PGD (1UL << PGDIR_BITS)
83 /* Kernel has a separate 44bit address space. */
84 #define FIRST_USER_ADDRESS 0
86 #define pte_ERROR(e) __builtin_trap()
87 #define pmd_ERROR(e) __builtin_trap()
88 #define pgd_ERROR(e) __builtin_trap()
90 #endif /* !(__ASSEMBLY__) */
92 /* PTE bits which are the same in SUN4U and SUN4V format. */
93 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
94 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
96 /* SUN4U pte bits... */
97 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */
98 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */
99 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */
100 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */
101 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */
102 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */
103 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
104 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */
105 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
106 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
107 #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */
108 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
109 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */
110 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */
111 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */
112 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */
113 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */
114 #define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */
115 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
116 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */
117 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */
118 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */
119 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */
120 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
121 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
122 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */
123 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */
124 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */
126 /* SUN4V pte bits... */
127 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */
128 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
129 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */
130 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */
131 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */
132 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */
133 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */
134 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */
135 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */
136 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
137 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
138 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */
139 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */
140 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */
141 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */
142 #define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */
143 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */
144 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */
145 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */
146 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */
147 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */
148 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */
149 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */
150 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */
151 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */
152 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */
153 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */
156 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
157 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
158 #elif PAGE_SHIFT == 16
159 #define _PAGE_SZBITS_4U _PAGE_SZ64K_4U
160 #define _PAGE_SZBITS_4V _PAGE_SZ64K_4V
161 #elif PAGE_SHIFT == 19
162 #define _PAGE_SZBITS_4U _PAGE_SZ512K_4U
163 #define _PAGE_SZBITS_4V _PAGE_SZ512K_4V
164 #elif PAGE_SHIFT == 22
165 #define _PAGE_SZBITS_4U _PAGE_SZ4MB_4U
166 #define _PAGE_SZBITS_4V _PAGE_SZ4MB_4V
168 #error Wrong PAGE_SHIFT specified
171 #if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
172 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
173 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
174 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
175 #define _PAGE_SZHUGE_4U _PAGE_SZ512K_4U
176 #define _PAGE_SZHUGE_4V _PAGE_SZ512K_4V
177 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
178 #define _PAGE_SZHUGE_4U _PAGE_SZ64K_4U
179 #define _PAGE_SZHUGE_4V _PAGE_SZ64K_4V
182 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
183 #define __P000 __pgprot(0)
184 #define __P001 __pgprot(0)
185 #define __P010 __pgprot(0)
186 #define __P011 __pgprot(0)
187 #define __P100 __pgprot(0)
188 #define __P101 __pgprot(0)
189 #define __P110 __pgprot(0)
190 #define __P111 __pgprot(0)
192 #define __S000 __pgprot(0)
193 #define __S001 __pgprot(0)
194 #define __S010 __pgprot(0)
195 #define __S011 __pgprot(0)
196 #define __S100 __pgprot(0)
197 #define __S101 __pgprot(0)
198 #define __S110 __pgprot(0)
199 #define __S111 __pgprot(0)
203 extern pte_t
mk_pte_io(unsigned long, pgprot_t
, int, unsigned long);
205 extern unsigned long pte_sz_bits(unsigned long size
);
207 extern pgprot_t PAGE_KERNEL
;
208 extern pgprot_t PAGE_KERNEL_LOCKED
;
209 extern pgprot_t PAGE_COPY
;
210 extern pgprot_t PAGE_SHARED
;
212 /* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */
213 extern unsigned long _PAGE_IE
;
214 extern unsigned long _PAGE_E
;
215 extern unsigned long _PAGE_CACHE
;
217 extern unsigned long pg_iobits
;
218 extern unsigned long _PAGE_ALL_SZ_BITS
;
219 extern unsigned long _PAGE_SZBITS
;
221 extern struct page
*mem_map_zero
;
222 #define ZERO_PAGE(vaddr) (mem_map_zero)
224 /* PFNs are real physical page numbers. However, mem_map only begins to record
225 * per-page information starting at pfn_base. This is to handle systems where
226 * the first physical page in the machine is at some huge physical address,
227 * such as 4GB. This is common on a partitioned E10000, for example.
229 static inline pte_t
pfn_pte(unsigned long pfn
, pgprot_t prot
)
231 unsigned long paddr
= pfn
<< PAGE_SHIFT
;
232 unsigned long sz_bits
;
235 if (_PAGE_SZBITS_4U
!= 0UL || _PAGE_SZBITS_4V
!= 0UL) {
236 __asm__
__volatile__(
237 "\n661: sethi %uhi(%1), %0\n"
239 " .section .sun4v_2insn_patch, \"ax\"\n"
245 : "i" (_PAGE_SZBITS_4U
), "i" (_PAGE_SZBITS_4V
));
247 return __pte(paddr
| sz_bits
| pgprot_val(prot
));
249 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
251 /* This one can be done with two shifts. */
252 static inline unsigned long pte_pfn(pte_t pte
)
256 __asm__
__volatile__(
257 "\n661: sllx %1, %2, %0\n"
259 " .section .sun4v_2insn_patch, \"ax\"\n"
265 : "r" (pte_val(pte
)),
266 "i" (21), "i" (21 + PAGE_SHIFT
),
267 "i" (8), "i" (8 + PAGE_SHIFT
));
271 #define pte_page(x) pfn_to_page(pte_pfn(x))
273 static inline pte_t
pte_modify(pte_t pte
, pgprot_t prot
)
275 unsigned long mask
, tmp
;
277 /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347)
278 * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8)
280 * Even if we use negation tricks the result is still a 6
281 * instruction sequence, so don't try to play fancy and just
282 * do the most straightforward implementation.
284 * Note: We encode this into 3 sun4v 2-insn patch sequences.
287 __asm__
__volatile__(
288 "\n661: sethi %%uhi(%2), %1\n"
289 " sethi %%hi(%2), %0\n"
290 "\n662: or %1, %%ulo(%2), %1\n"
291 " or %0, %%lo(%2), %0\n"
292 "\n663: sllx %1, 32, %1\n"
294 " .section .sun4v_2insn_patch, \"ax\"\n"
296 " sethi %%uhi(%3), %1\n"
297 " sethi %%hi(%3), %0\n"
299 " or %1, %%ulo(%3), %1\n"
300 " or %0, %%lo(%3), %0\n"
305 : "=r" (mask
), "=r" (tmp
)
306 : "i" (_PAGE_PADDR_4U
| _PAGE_MODIFIED_4U
| _PAGE_ACCESSED_4U
|
307 _PAGE_CP_4U
| _PAGE_CV_4U
| _PAGE_E_4U
| _PAGE_PRESENT_4U
|
309 "i" (_PAGE_PADDR_4V
| _PAGE_MODIFIED_4V
| _PAGE_ACCESSED_4V
|
310 _PAGE_CP_4V
| _PAGE_CV_4V
| _PAGE_E_4V
| _PAGE_PRESENT_4V
|
313 return __pte((pte_val(pte
) & mask
) | (pgprot_val(prot
) & ~mask
));
316 static inline pte_t
pgoff_to_pte(unsigned long off
)
320 __asm__
__volatile__(
321 "\n661: or %0, %2, %0\n"
322 " .section .sun4v_1insn_patch, \"ax\"\n"
327 : "0" (off
), "i" (_PAGE_FILE_4U
), "i" (_PAGE_FILE_4V
));
332 static inline pgprot_t
pgprot_noncached(pgprot_t prot
)
334 unsigned long val
= pgprot_val(prot
);
336 __asm__
__volatile__(
337 "\n661: andn %0, %2, %0\n"
339 " .section .sun4v_2insn_patch, \"ax\"\n"
345 : "0" (val
), "i" (_PAGE_CP_4U
| _PAGE_CV_4U
), "i" (_PAGE_E_4U
),
346 "i" (_PAGE_CP_4V
| _PAGE_CV_4V
), "i" (_PAGE_E_4V
));
348 return __pgprot(val
);
350 /* Various pieces of code check for platform support by ifdef testing
351 * on "pgprot_noncached". That's broken and should be fixed, but for
354 #define pgprot_noncached pgprot_noncached
356 #ifdef CONFIG_HUGETLB_PAGE
357 static inline pte_t
pte_mkhuge(pte_t pte
)
361 __asm__
__volatile__(
362 "\n661: sethi %%uhi(%1), %0\n"
364 " .section .sun4v_2insn_patch, \"ax\"\n"
370 : "i" (_PAGE_SZHUGE_4U
), "i" (_PAGE_SZHUGE_4V
));
372 return __pte(pte_val(pte
) | mask
);
376 static inline pte_t
pte_mkdirty(pte_t pte
)
378 unsigned long val
= pte_val(pte
), tmp
;
380 __asm__
__volatile__(
381 "\n661: or %0, %3, %0\n"
385 " .section .sun4v_2insn_patch, \"ax\"\n"
387 " sethi %%uhi(%4), %1\n"
390 " or %1, %%lo(%4), %1\n"
393 : "=r" (val
), "=r" (tmp
)
394 : "0" (val
), "i" (_PAGE_MODIFIED_4U
| _PAGE_W_4U
),
395 "i" (_PAGE_MODIFIED_4V
| _PAGE_W_4V
));
400 static inline pte_t
pte_mkclean(pte_t pte
)
402 unsigned long val
= pte_val(pte
), tmp
;
404 __asm__
__volatile__(
405 "\n661: andn %0, %3, %0\n"
409 " .section .sun4v_2insn_patch, \"ax\"\n"
411 " sethi %%uhi(%4), %1\n"
414 " or %1, %%lo(%4), %1\n"
417 : "=r" (val
), "=r" (tmp
)
418 : "0" (val
), "i" (_PAGE_MODIFIED_4U
| _PAGE_W_4U
),
419 "i" (_PAGE_MODIFIED_4V
| _PAGE_W_4V
));
424 static inline pte_t
pte_mkwrite(pte_t pte
)
426 unsigned long val
= pte_val(pte
), mask
;
428 __asm__
__volatile__(
429 "\n661: mov %1, %0\n"
431 " .section .sun4v_2insn_patch, \"ax\"\n"
433 " sethi %%uhi(%2), %0\n"
437 : "i" (_PAGE_WRITE_4U
), "i" (_PAGE_WRITE_4V
));
439 return __pte(val
| mask
);
442 static inline pte_t
pte_wrprotect(pte_t pte
)
444 unsigned long val
= pte_val(pte
), tmp
;
446 __asm__
__volatile__(
447 "\n661: andn %0, %3, %0\n"
451 " .section .sun4v_2insn_patch, \"ax\"\n"
453 " sethi %%uhi(%4), %1\n"
456 " or %1, %%lo(%4), %1\n"
459 : "=r" (val
), "=r" (tmp
)
460 : "0" (val
), "i" (_PAGE_WRITE_4U
| _PAGE_W_4U
),
461 "i" (_PAGE_WRITE_4V
| _PAGE_W_4V
));
466 static inline pte_t
pte_mkold(pte_t pte
)
470 __asm__
__volatile__(
471 "\n661: mov %1, %0\n"
473 " .section .sun4v_2insn_patch, \"ax\"\n"
475 " sethi %%uhi(%2), %0\n"
479 : "i" (_PAGE_ACCESSED_4U
), "i" (_PAGE_ACCESSED_4V
));
483 return __pte(pte_val(pte
) & ~mask
);
486 static inline pte_t
pte_mkyoung(pte_t pte
)
490 __asm__
__volatile__(
491 "\n661: mov %1, %0\n"
493 " .section .sun4v_2insn_patch, \"ax\"\n"
495 " sethi %%uhi(%2), %0\n"
499 : "i" (_PAGE_ACCESSED_4U
), "i" (_PAGE_ACCESSED_4V
));
503 return __pte(pte_val(pte
) | mask
);
506 static inline unsigned long pte_young(pte_t pte
)
510 __asm__
__volatile__(
511 "\n661: mov %1, %0\n"
513 " .section .sun4v_2insn_patch, \"ax\"\n"
515 " sethi %%uhi(%2), %0\n"
519 : "i" (_PAGE_ACCESSED_4U
), "i" (_PAGE_ACCESSED_4V
));
521 return (pte_val(pte
) & mask
);
524 static inline unsigned long pte_dirty(pte_t pte
)
528 __asm__
__volatile__(
529 "\n661: mov %1, %0\n"
531 " .section .sun4v_2insn_patch, \"ax\"\n"
533 " sethi %%uhi(%2), %0\n"
537 : "i" (_PAGE_MODIFIED_4U
), "i" (_PAGE_MODIFIED_4V
));
539 return (pte_val(pte
) & mask
);
542 static inline unsigned long pte_write(pte_t pte
)
546 __asm__
__volatile__(
547 "\n661: mov %1, %0\n"
549 " .section .sun4v_2insn_patch, \"ax\"\n"
551 " sethi %%uhi(%2), %0\n"
555 : "i" (_PAGE_WRITE_4U
), "i" (_PAGE_WRITE_4V
));
557 return (pte_val(pte
) & mask
);
560 static inline unsigned long pte_exec(pte_t pte
)
564 __asm__
__volatile__(
565 "\n661: sethi %%hi(%1), %0\n"
566 " .section .sun4v_1insn_patch, \"ax\"\n"
571 : "i" (_PAGE_EXEC_4U
), "i" (_PAGE_EXEC_4V
));
573 return (pte_val(pte
) & mask
);
576 static inline unsigned long pte_read(pte_t pte
)
580 __asm__
__volatile__(
581 "\n661: mov %1, %0\n"
583 " .section .sun4v_2insn_patch, \"ax\"\n"
585 " sethi %%uhi(%2), %0\n"
589 : "i" (_PAGE_READ_4U
), "i" (_PAGE_READ_4V
));
591 return (pte_val(pte
) & mask
);
594 static inline unsigned long pte_file(pte_t pte
)
596 unsigned long val
= pte_val(pte
);
598 __asm__
__volatile__(
599 "\n661: and %0, %2, %0\n"
600 " .section .sun4v_1insn_patch, \"ax\"\n"
605 : "0" (val
), "i" (_PAGE_FILE_4U
), "i" (_PAGE_FILE_4V
));
610 static inline unsigned long pte_present(pte_t pte
)
612 unsigned long val
= pte_val(pte
);
614 __asm__
__volatile__(
615 "\n661: and %0, %2, %0\n"
616 " .section .sun4v_1insn_patch, \"ax\"\n"
621 : "0" (val
), "i" (_PAGE_PRESENT_4U
), "i" (_PAGE_PRESENT_4V
));
626 #define pmd_set(pmdp, ptep) \
627 (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
628 #define pud_set(pudp, pmdp) \
629 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
630 #define __pmd_page(pmd) \
631 ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL)))
632 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
633 #define pud_page(pud) \
634 ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL)))
635 #define pmd_none(pmd) (!pmd_val(pmd))
636 #define pmd_bad(pmd) (0)
637 #define pmd_present(pmd) (pmd_val(pmd) != 0U)
638 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0U)
639 #define pud_none(pud) (!pud_val(pud))
640 #define pud_bad(pud) (0)
641 #define pud_present(pud) (pud_val(pud) != 0U)
642 #define pud_clear(pudp) (pud_val(*(pudp)) = 0U)
644 /* Same in both SUN4V and SUN4U. */
645 #define pte_none(pte) (!pte_val(pte))
647 /* to find an entry in a page-table-directory. */
648 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
649 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
651 /* to find an entry in a kernel page-table-directory */
652 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
654 /* Find an entry in the second-level page table.. */
655 #define pmd_offset(pudp, address) \
656 ((pmd_t *) pud_page(*(pudp)) + \
657 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
659 /* Find an entry in the third-level page table.. */
660 #define pte_index(dir, address) \
661 ((pte_t *) __pmd_page(*(dir)) + \
662 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
663 #define pte_offset_kernel pte_index
664 #define pte_offset_map pte_index
665 #define pte_offset_map_nested pte_index
666 #define pte_unmap(pte) do { } while (0)
667 #define pte_unmap_nested(pte) do { } while (0)
669 /* Actual page table PTE updates. */
670 extern void tlb_batch_add(struct mm_struct
*mm
, unsigned long vaddr
, pte_t
*ptep
, pte_t orig
);
672 static inline void set_pte_at(struct mm_struct
*mm
, unsigned long addr
, pte_t
*ptep
, pte_t pte
)
678 /* It is more efficient to let flush_tlb_kernel_range()
679 * handle init_mm tlb flushes.
681 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
682 * and SUN4V pte layout, so this inline test is fine.
684 if (likely(mm
!= &init_mm
) && (pte_val(orig
) & _PAGE_VALID
))
685 tlb_batch_add(mm
, addr
, ptep
, orig
);
688 #define pte_clear(mm,addr,ptep) \
689 set_pte_at((mm), (addr), (ptep), __pte(0UL))
691 extern pgd_t swapper_pg_dir
[2048];
692 extern pmd_t swapper_low_pmd_dir
[2048];
694 extern void paging_init(void);
695 extern unsigned long find_ecache_flush_span(unsigned long size
);
697 /* These do nothing with the way I have things setup. */
698 #define mmu_lockarea(vaddr, len) (vaddr)
699 #define mmu_unlockarea(vaddr, len) do { } while(0)
701 struct vm_area_struct
;
702 extern void update_mmu_cache(struct vm_area_struct
*, unsigned long, pte_t
);
704 /* Encode and de-code a swap entry */
705 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
706 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
707 #define __swp_entry(type, offset) \
710 (((long)(type) << PAGE_SHIFT) | \
711 ((long)(offset) << (PAGE_SHIFT + 8UL))) \
713 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
714 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
716 /* File offset in PTE support. */
717 extern unsigned long pte_file(pte_t
);
718 #define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT)
719 extern pte_t
pgoff_to_pte(unsigned long);
720 #define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
722 extern unsigned long prom_virt_to_phys(unsigned long, int *);
724 extern unsigned long sun4u_get_pte(unsigned long);
726 static inline unsigned long __get_phys(unsigned long addr
)
728 return sun4u_get_pte(addr
);
731 static inline int __get_iospace(unsigned long addr
)
733 return ((sun4u_get_pte(addr
) & 0xf0000000) >> 28);
736 extern unsigned long *sparc64_valid_addr_bitmap
;
738 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
739 #define kern_addr_valid(addr) \
740 (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
742 extern int io_remap_pfn_range(struct vm_area_struct
*vma
, unsigned long from
,
744 unsigned long size
, pgprot_t prot
);
747 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
748 * its high 4 bits. These macros/functions put it there or get it from there.
750 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
751 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
752 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
754 #include <asm-generic/pgtable.h>
756 /* We provide our own get_unmapped_area to cope with VA holes and
757 * SHM area cache aliasing for userland.
759 #define HAVE_ARCH_UNMAPPED_AREA
760 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
762 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use
763 * the largest alignment possible such that larget PTEs can be used.
765 extern unsigned long get_fb_unmapped_area(struct file
*filp
, unsigned long,
766 unsigned long, unsigned long,
768 #define HAVE_ARCH_FB_UNMAPPED_AREA
770 extern void pgtable_cache_init(void);
771 extern void sun4v_register_fault_status(void);
772 extern void sun4v_ktsb_register(void);
774 #endif /* !(__ASSEMBLY__) */
776 #endif /* !(_SPARC64_PGTABLE_H) */