2 * AMD Alchemy DB1x00 Reference Boards
4 * Copyright 2001 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc.
6 * ppopov@mvista.com or source@mvista.com
7 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
9 * ########################################################################
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 * ########################################################################
28 #ifndef __ASM_DB1X00_H
29 #define __ASM_DB1X00_H
32 #ifdef CONFIG_MIPS_DB1550
33 #define BCSR_KSEG1_ADDR 0xAF000000
34 #define NAND_PHYS_ADDR 0x20000000
36 #define BCSR_KSEG1_ADDR 0xAE000000
40 * Overlay data structure of the Db1x00 board registers.
41 * Registers located at physical 0E0000xx, KSEG1 0xAE0000xx
43 typedef volatile struct
45 /*00*/ unsigned short whoami
;
46 unsigned short reserved0
;
47 /*04*/ unsigned short status
;
48 unsigned short reserved1
;
49 /*08*/ unsigned short switches
;
50 unsigned short reserved2
;
51 /*0C*/ unsigned short resets
;
52 unsigned short reserved3
;
53 /*10*/ unsigned short pcmcia
;
54 unsigned short reserved4
;
55 /*14*/ unsigned short specific
;
56 unsigned short reserved5
;
57 /*18*/ unsigned short leds
;
58 unsigned short reserved6
;
59 /*1C*/ unsigned short swreset
;
60 unsigned short reserved7
;
66 * Register/mask bit definitions for the BCSRs
68 #define BCSR_WHOAMI_DCID 0x000F
69 #define BCSR_WHOAMI_CPLD 0x00F0
70 #define BCSR_WHOAMI_BOARD 0x0F00
72 #define BCSR_STATUS_PC0VS 0x0003
73 #define BCSR_STATUS_PC1VS 0x000C
74 #define BCSR_STATUS_PC0FI 0x0010
75 #define BCSR_STATUS_PC1FI 0x0020
76 #define BCSR_STATUS_FLASHBUSY 0x0100
77 #define BCSR_STATUS_ROMBUSY 0x0400
78 #define BCSR_STATUS_SWAPBOOT 0x2000
79 #define BCSR_STATUS_FLASHDEN 0xC000
81 #define BCSR_SWITCHES_DIP 0x00FF
82 #define BCSR_SWITCHES_DIP_1 0x0080
83 #define BCSR_SWITCHES_DIP_2 0x0040
84 #define BCSR_SWITCHES_DIP_3 0x0020
85 #define BCSR_SWITCHES_DIP_4 0x0010
86 #define BCSR_SWITCHES_DIP_5 0x0008
87 #define BCSR_SWITCHES_DIP_6 0x0004
88 #define BCSR_SWITCHES_DIP_7 0x0002
89 #define BCSR_SWITCHES_DIP_8 0x0001
90 #define BCSR_SWITCHES_ROTARY 0x0F00
92 #define BCSR_RESETS_PHY0 0x0001
93 #define BCSR_RESETS_PHY1 0x0002
94 #define BCSR_RESETS_DC 0x0004
95 #define BCSR_RESETS_FIR_SEL 0x2000
96 #define BCSR_RESETS_IRDA_MODE_MASK 0xC000
97 #define BCSR_RESETS_IRDA_MODE_FULL 0x0000
98 #define BCSR_RESETS_IRDA_MODE_OFF 0x4000
99 #define BCSR_RESETS_IRDA_MODE_2_3 0x8000
100 #define BCSR_RESETS_IRDA_MODE_1_3 0xC000
102 #define BCSR_PCMCIA_PC0VPP 0x0003
103 #define BCSR_PCMCIA_PC0VCC 0x000C
104 #define BCSR_PCMCIA_PC0DRVEN 0x0010
105 #define BCSR_PCMCIA_PC0RST 0x0080
106 #define BCSR_PCMCIA_PC1VPP 0x0300
107 #define BCSR_PCMCIA_PC1VCC 0x0C00
108 #define BCSR_PCMCIA_PC1DRVEN 0x1000
109 #define BCSR_PCMCIA_PC1RST 0x8000
111 #define BCSR_BOARD_PCIM66EN 0x0001
112 #define BCSR_BOARD_SD0_PWR 0x0040
113 #define BCSR_BOARD_SD1_PWR 0x0080
114 #define BCSR_BOARD_PCIM33 0x0100
115 #define BCSR_BOARD_GPIO200RST 0x0400
116 #define BCSR_BOARD_PCICFG 0x1000
117 #define BCSR_BOARD_SD0_WP 0x4000
118 #define BCSR_BOARD_SD1_WP 0x8000
120 #define BCSR_LEDS_DECIMALS 0x0003
121 #define BCSR_LEDS_LED0 0x0100
122 #define BCSR_LEDS_LED1 0x0200
123 #define BCSR_LEDS_LED2 0x0400
124 #define BCSR_LEDS_LED3 0x0800
126 #define BCSR_SWRESET_RESET 0x0080
128 /* PCMCIA Db1x00 specific defines */
129 #define PCMCIA_MAX_SOCK 1
130 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
133 #define SET_VCC_VPP(VCC, VPP, SLOT)\
134 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
136 /* SD controller macros */
140 #define mmc_card_inserted(_n_, _res_) \
142 BCSR * const bcsr = (BCSR *)0xAE000000; \
143 unsigned long mmc_wp, board_specific; \
145 mmc_wp = BCSR_BOARD_SD1_WP; \
147 mmc_wp = BCSR_BOARD_SD0_WP; \
149 board_specific = au_readl((unsigned long)(&bcsr->specific)); \
150 if (!(board_specific & mmc_wp)) {/* low means card present */ \
151 *(int *)(_res_) = 1; \
153 *(int *)(_res_) = 0; \
158 * Apply power to card slot(s).
160 #define mmc_power_on(_n_) \
162 BCSR * const bcsr = (BCSR *)0xAE000000; \
163 unsigned long mmc_pwr, mmc_wp, board_specific; \
165 mmc_pwr = BCSR_BOARD_SD1_PWR; \
166 mmc_wp = BCSR_BOARD_SD1_WP; \
168 mmc_pwr = BCSR_BOARD_SD0_PWR; \
169 mmc_wp = BCSR_BOARD_SD0_WP; \
171 board_specific = au_readl((unsigned long)(&bcsr->specific)); \
172 if (!(board_specific & mmc_wp)) {/* low means card present */ \
173 board_specific |= mmc_pwr; \
174 au_writel(board_specific, (int)(&bcsr->specific)); \
181 /* Timing values as described in databook, * ns value stripped of
183 * These defines are here rather than an SOC1550 generic file because
184 * the parts chosen on another board may be different and may require
187 #define NAND_T_H (18 >> 2)
188 #define NAND_T_PUL (30 >> 2)
189 #define NAND_T_SU (30 >> 2)
190 #define NAND_T_WH (30 >> 2)
192 /* Bitfield shift amounts */
193 #define NAND_T_H_SHIFT 0
194 #define NAND_T_PUL_SHIFT 4
195 #define NAND_T_SU_SHIFT 8
196 #define NAND_T_WH_SHIFT 12
198 #define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
199 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
200 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
201 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
204 /* should be done by yamon */
205 #define NAND_STCFG 0x00400005 /* 8-bit NAND */
206 #define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
207 #define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
209 #endif /* __ASM_DB1X00_H */