include/asm-arm/system.h

   1 #ifndef __ASM_ARM_SYSTEM_H
   2 #define __ASM_ARM_SYSTEM_H
   3
   4 #ifdef __KERNEL__
   5
   6
   7 #define CPU_ARCH_UNKNOWN        0
   8 #define CPU_ARCH_ARMv3          1
   9 #define CPU_ARCH_ARMv4          2
  10 #define CPU_ARCH_ARMv4T         3
  11 #define CPU_ARCH_ARMv5          4
  12 #define CPU_ARCH_ARMv5T         5
  13 #define CPU_ARCH_ARMv5TE        6
  14 #define CPU_ARCH_ARMv5TEJ       7
  15 #define CPU_ARCH_ARMv6          8
  16
  17 /*
  18  * CR1 bits (CP#15 CR1)
  19  */
  20 #define CR_M    (1 << 0)        /* MMU enable                           */
  21 #define CR_A    (1 << 1)        /* Alignment abort enable               */
  22 #define CR_C    (1 << 2)        /* Dcache enable                        */
  23 #define CR_W    (1 << 3)        /* Write buffer enable                  */
  24 #define CR_P    (1 << 4)        /* 32-bit exception handler             */
  25 #define CR_D    (1 << 5)        /* 32-bit data address range            */
  26 #define CR_L    (1 << 6)        /* Implementation defined               */
  27 #define CR_B    (1 << 7)        /* Big endian                           */
  28 #define CR_S    (1 << 8)        /* System MMU protection                */
  29 #define CR_R    (1 << 9)        /* ROM MMU protection                   */
  30 #define CR_F    (1 << 10)       /* Implementation defined               */
  31 #define CR_Z    (1 << 11)       /* Implementation defined               */
  32 #define CR_I    (1 << 12)       /* Icache enable                        */
  33 #define CR_V    (1 << 13)       /* Vectors relocated to 0xffff0000      */
  34 #define CR_RR   (1 << 14)       /* Round Robin cache replacement        */
  35 #define CR_L4   (1 << 15)       /* LDR pc can set T bit                 */
  36 #define CR_DT   (1 << 16)
  37 #define CR_IT   (1 << 18)
  38 #define CR_ST   (1 << 19)
  39 #define CR_FI   (1 << 21)       /* Fast interrupt (lower latency mode)  */
  40 #define CR_U    (1 << 22)       /* Unaligned access operation           */
  41 #define CR_XP   (1 << 23)       /* Extended page tables                 */
  42 #define CR_VE   (1 << 24)       /* Vectored interrupts                  */
  43
  44 #define CPUID_ID        0
  45 #define CPUID_CACHETYPE 1
  46 #define CPUID_TCM       2
  47 #define CPUID_TLBTYPE   3
  48
  49 #define read_cpuid(reg)                                                 \
  50         ({                                                              \
  51                 unsigned int __val;                                     \
  52                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
  53                     : "=r" (__val)                                      \
  54                     :                                                   \
  55                     : "cc");                                            \
  56                 __val;                                                  \
  57         })
  58
  59 /*
  60  * This is used to ensure the compiler did actually allocate the register we
  61  * asked it for some inline assembly sequences.  Apparently we can't trust
  62  * the compiler from one version to another so a bit of paranoia won't hurt.
  63  * This string is meant to be concatenated with the inline asm string and
  64  * will cause compilation to stop on mismatch.
  65  * (for details, see gcc PR 15089)
  66  */
  67 #define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
  68
  69 #ifndef __ASSEMBLY__
  70
  71 #include <linux/linkage.h>
  72
  73 struct thread_info;
  74 struct task_struct;
  75
  76 /* information about the system we're running on */
  77 extern unsigned int system_rev;
  78 extern unsigned int system_serial_low;
  79 extern unsigned int system_serial_high;
  80 extern unsigned int mem_fclk_21285;
  81
  82 struct pt_regs;
  83
  84 void die(const char *msg, struct pt_regs *regs, int err)
  85                 __attribute__((noreturn));
  86
  87 struct siginfo;
  88 void notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
  89                 unsigned long err, unsigned long trap);
  90
  91 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
  92                                        struct pt_regs *),
  93                      int sig, const char *name);
  94
  95 #define xchg(ptr,x) \
  96         ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
  97
  98 #define tas(ptr) (xchg((ptr),1))
  99
 100 extern asmlinkage void __backtrace(void);
 101 extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
 102
 103 struct mm_struct;
 104 extern void show_pte(struct mm_struct *mm, unsigned long addr);
 105 extern void __show_regs(struct pt_regs *);
 106
 107 extern int cpu_architecture(void);
 108 extern void cpu_init(void);
 109
 110 /*
 111  * Intel's XScale3 core supports some v6 features (supersections, L2)
 112  * but advertises itself as v5 as it does not support the v6 ISA.  For
 113  * this reason, we need a way to explicitly test for this type of CPU.
 114  */
 115 #ifndef CONFIG_CPU_XSC3
 116 #define cpu_is_xsc3()   0
 117 #else
 118 static inline int cpu_is_xsc3(void)
 119 {
 120         extern unsigned int processor_id;
 121
 122         if ((processor_id & 0xffffe000) == 0x69056000)
 123                 return 1;
 124
 125         return 0;
 126 }
 127 #endif
 128
 129 #define set_cr(x)                                       \
 130         __asm__ __volatile__(                           \
 131         "mcr    p15, 0, %0, c1, c0, 0   @ set CR"       \
 132         : : "r" (x) : "cc")
 133
 134 #define get_cr()                                        \
 135         ({                                              \
 136         unsigned int __val;                             \
 137         __asm__ __volatile__(                           \
 138         "mrc    p15, 0, %0, c1, c0, 0   @ get CR"       \
 139         : "=r" (__val) : : "cc");                       \
 140         __val;                                          \
 141         })
 142
 143 extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
 144 extern unsigned long cr_alignment;      /* defined in entry-armv.S */
 145
 146 #define UDBG_UNDEFINED  (1 << 0)
 147 #define UDBG_SYSCALL    (1 << 1)
 148 #define UDBG_BADABORT   (1 << 2)
 149 #define UDBG_SEGV       (1 << 3)
 150 #define UDBG_BUS        (1 << 4)
 151
 152 extern unsigned int user_debug;
 153
 154 #if __LINUX_ARM_ARCH__ >= 4
 155 #define vectors_high()  (cr_alignment & CR_V)
 156 #else
 157 #define vectors_high()  (0)
 158 #endif
 159
 160 #if __LINUX_ARM_ARCH__ >= 6
 161 #define mb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
 162                                    : : "r" (0) : "memory")
 163 #else
 164 #define mb() __asm__ __volatile__ ("" : : : "memory")
 165 #endif
 166 #define rmb() mb()
 167 #define wmb() mb()
 168 #define read_barrier_depends() do { } while(0)
 169 #define set_mb(var, value)  do { var = value; mb(); } while (0)
 170 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
 171 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 172
 173 /*
 174  * switch_mm() may do a full cache flush over the context switch,
 175  * so enable interrupts over the context switch to avoid high
 176  * latency.
 177  */
 178 #define __ARCH_WANT_INTERRUPTS_ON_CTXSW
 179
 180 /*
 181  * switch_to(prev, next) should switch from task `prev' to `next'
 182  * `prev' will never be the same as `next'.  schedule() itself
 183  * contains the memory barrier to tell GCC not to cache `current'.
 184  */
 185 extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
 186
 187 #define switch_to(prev,next,last)                                       \
 188 do {                                                                    \
 189         last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));        \
 190 } while (0)
 191
 192 /*
 193  * On SMP systems, when the scheduler does migration-cost autodetection,
 194  * it needs a way to flush as much of the CPU's caches as possible.
 195  *
 196  * TODO: fill this in!
 197  */
 198 static inline void sched_cacheflush(void)
 199 {
 200 }
 201
 202 /*
 203  * CPU interrupt mask handling.
 204  */
 205 #if __LINUX_ARM_ARCH__ >= 6
 206
 207 #define local_irq_save(x)                                       \
 208         ({                                                      \
 209         __asm__ __volatile__(                                   \
 210         "mrs    %0, cpsr                @ local_irq_save\n"     \
 211         "cpsid  i"                                              \
 212         : "=r" (x) : : "memory", "cc");                         \
 213         })
 214
 215 #define local_irq_enable()  __asm__("cpsie i    @ __sti" : : : "memory", "cc")
 216 #define local_irq_disable() __asm__("cpsid i    @ __cli" : : : "memory", "cc")
 217 #define local_fiq_enable()  __asm__("cpsie f    @ __stf" : : : "memory", "cc")
 218 #define local_fiq_disable() __asm__("cpsid f    @ __clf" : : : "memory", "cc")
 219
 220 #else
 221
 222 /*
 223  * Save the current interrupt enable state & disable IRQs
 224  */
 225 #define local_irq_save(x)                                       \
 226         ({                                                      \
 227                 unsigned long temp;                             \
 228                 (void) (&temp == &x);                           \
 229         __asm__ __volatile__(                                   \
 230         "mrs    %0, cpsr                @ local_irq_save\n"     \
 231 "       orr     %1, %0, #128\n"                                 \
 232 "       msr     cpsr_c, %1"                                     \
 233         : "=r" (x), "=r" (temp)                                 \
 234         :                                                       \
 235         : "memory", "cc");                                      \
 236         })
 237
 238 /*
 239  * Enable IRQs
 240  */
 241 #define local_irq_enable()                                      \
 242         ({                                                      \
 243                 unsigned long temp;                             \
 244         __asm__ __volatile__(                                   \
 245         "mrs    %0, cpsr                @ local_irq_enable\n"   \
 246 "       bic     %0, %0, #128\n"                                 \
 247 "       msr     cpsr_c, %0"                                     \
 248         : "=r" (temp)                                           \
 249         :                                                       \
 250         : "memory", "cc");                                      \
 251         })
 252
 253 /*
 254  * Disable IRQs
 255  */
 256 #define local_irq_disable()                                     \
 257         ({                                                      \
 258                 unsigned long temp;                             \
 259         __asm__ __volatile__(                                   \
 260         "mrs    %0, cpsr                @ local_irq_disable\n"  \
 261 "       orr     %0, %0, #128\n"                                 \
 262 "       msr     cpsr_c, %0"                                     \
 263         : "=r" (temp)                                           \
 264         :                                                       \
 265         : "memory", "cc");                                      \
 266         })
 267
 268 /*
 269  * Enable FIQs
 270  */
 271 #define local_fiq_enable()                                      \
 272         ({                                                      \
 273                 unsigned long temp;                             \
 274         __asm__ __volatile__(                                   \
 275         "mrs    %0, cpsr                @ stf\n"                \
 276 "       bic     %0, %0, #64\n"                                  \
 277 "       msr     cpsr_c, %0"                                     \
 278         : "=r" (temp)                                           \
 279         :                                                       \
 280         : "memory", "cc");                                      \
 281         })
 282
 283 /*
 284  * Disable FIQs
 285  */
 286 #define local_fiq_disable()                                     \
 287         ({                                                      \
 288                 unsigned long temp;                             \
 289         __asm__ __volatile__(                                   \
 290         "mrs    %0, cpsr                @ clf\n"                \
 291 "       orr     %0, %0, #64\n"                                  \
 292 "       msr     cpsr_c, %0"                                     \
 293         : "=r" (temp)                                           \
 294         :                                                       \
 295         : "memory", "cc");                                      \
 296         })
 297
 298 #endif
 299
 300 /*
 301  * Save the current interrupt enable state.
 302  */
 303 #define local_save_flags(x)                                     \
 304         ({                                                      \
 305         __asm__ __volatile__(                                   \
 306         "mrs    %0, cpsr                @ local_save_flags"     \
 307         : "=r" (x) : : "memory", "cc");                         \
 308         })
 309
 310 /*
 311  * restore saved IRQ & FIQ state
 312  */
 313 #define local_irq_restore(x)                                    \
 314         __asm__ __volatile__(                                   \
 315         "msr    cpsr_c, %0              @ local_irq_restore\n"  \
 316         :                                                       \
 317         : "r" (x)                                               \
 318         : "memory", "cc")
 319
 320 #define irqs_disabled()                 \
 321 ({                                      \
 322         unsigned long flags;            \
 323         local_save_flags(flags);        \
 324         (int)(flags & PSR_I_BIT);       \
 325 })
 326
 327 #ifdef CONFIG_SMP
 328
 329 #define smp_mb()                mb()
 330 #define smp_rmb()               rmb()
 331 #define smp_wmb()               wmb()
 332 #define smp_read_barrier_depends()              read_barrier_depends()
 333
 334 #else
 335
 336 #define smp_mb()                barrier()
 337 #define smp_rmb()               barrier()
 338 #define smp_wmb()               barrier()
 339 #define smp_read_barrier_depends()              do { } while(0)
 340
 341 #endif /* CONFIG_SMP */
 342
 343 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
 344 /*
 345  * On the StrongARM, "swp" is terminally broken since it bypasses the
 346  * cache totally.  This means that the cache becomes inconsistent, and,
 347  * since we use normal loads/stores as well, this is really bad.
 348  * Typically, this causes oopsen in filp_close, but could have other,
 349  * more disasterous effects.  There are two work-arounds:
 350  *  1. Disable interrupts and emulate the atomic swap
 351  *  2. Clean the cache, perform atomic swap, flush the cache
 352  *
 353  * We choose (1) since its the "easiest" to achieve here and is not
 354  * dependent on the processor type.
 355  *
 356  * NOTE that this solution won't work on an SMP system, so explcitly
 357  * forbid it here.
 358  */
 359 #define swp_is_buggy
 360 #endif
 361
 362 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
 363 {
 364         extern void __bad_xchg(volatile void *, int);
 365         unsigned long ret;
 366 #ifdef swp_is_buggy
 367         unsigned long flags;
 368 #endif
 369 #if __LINUX_ARM_ARCH__ >= 6
 370         unsigned int tmp;
 371 #endif
 372
 373         switch (size) {
 374 #if __LINUX_ARM_ARCH__ >= 6
 375         case 1:
 376                 asm volatile("@ __xchg1\n"
 377                 "1:     ldrexb  %0, [%3]\n"
 378                 "       strexb  %1, %2, [%3]\n"
 379                 "       teq     %1, #0\n"
 380                 "       bne     1b"
 381                         : "=&r" (ret), "=&r" (tmp)
 382                         : "r" (x), "r" (ptr)
 383                         : "memory", "cc");
 384                 break;
 385         case 4:
 386                 asm volatile("@ __xchg4\n"
 387                 "1:     ldrex   %0, [%3]\n"
 388                 "       strex   %1, %2, [%3]\n"
 389                 "       teq     %1, #0\n"
 390                 "       bne     1b"
 391                         : "=&r" (ret), "=&r" (tmp)
 392                         : "r" (x), "r" (ptr)
 393                         : "memory", "cc");
 394                 break;
 395 #elif defined(swp_is_buggy)
 396 #ifdef CONFIG_SMP
 397 #error SMP is not supported on this platform
 398 #endif
 399         case 1:
 400                 local_irq_save(flags);
 401                 ret = *(volatile unsigned char *)ptr;
 402                 *(volatile unsigned char *)ptr = x;
 403                 local_irq_restore(flags);
 404                 break;
 405
 406         case 4:
 407                 local_irq_save(flags);
 408                 ret = *(volatile unsigned long *)ptr;
 409                 *(volatile unsigned long *)ptr = x;
 410                 local_irq_restore(flags);
 411                 break;
 412 #else
 413         case 1:
 414                 asm volatile("@ __xchg1\n"
 415                 "       swpb    %0, %1, [%2]"
 416                         : "=&r" (ret)
 417                         : "r" (x), "r" (ptr)
 418                         : "memory", "cc");
 419                 break;
 420         case 4:
 421                 asm volatile("@ __xchg4\n"
 422                 "       swp     %0, %1, [%2]"
 423                         : "=&r" (ret)
 424                         : "r" (x), "r" (ptr)
 425                         : "memory", "cc");
 426                 break;
 427 #endif
 428         default:
 429                 __bad_xchg(ptr, size), ret = 0;
 430                 break;
 431         }
 432
 433         return ret;
 434 }
 435
 436 extern void disable_hlt(void);
 437 extern void enable_hlt(void);
 438
 439 #endif /* __ASSEMBLY__ */
 440
 441 #define arch_align_stack(x) (x)
 442
 443 #endif /* __KERNEL__ */
 444
 445 #endif