[PATCH] x86_64: Fix VSMP build
[linux-2.6/pdupreez.git] / arch / x86_64 / kernel / nmi.c
blob5fae6f0cd9947d16cc5530777268c80d36490a0b
1 /*
2 * linux/arch/x86_64/nmi.c
4 * NMI watchdog support on APIC systems
6 * Started by Ingo Molnar <mingo@redhat.com>
8 * Fixes:
9 * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
10 * Mikael Pettersson : Power Management for local APIC NMI watchdog.
11 * Pavel Machek and
12 * Mikael Pettersson : PM converted to driver model. Disable/enable API.
15 #include <linux/config.h>
16 #include <linux/mm.h>
17 #include <linux/delay.h>
18 #include <linux/bootmem.h>
19 #include <linux/smp_lock.h>
20 #include <linux/interrupt.h>
21 #include <linux/mc146818rtc.h>
22 #include <linux/kernel_stat.h>
23 #include <linux/module.h>
24 #include <linux/sysdev.h>
25 #include <linux/nmi.h>
26 #include <linux/sysctl.h>
28 #include <asm/smp.h>
29 #include <asm/mtrr.h>
30 #include <asm/mpspec.h>
31 #include <asm/nmi.h>
32 #include <asm/msr.h>
33 #include <asm/proto.h>
34 #include <asm/kdebug.h>
35 #include <asm/local.h>
38 * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
39 * - it may be reserved by some other driver, or not
40 * - when not reserved by some other driver, it may be used for
41 * the NMI watchdog, or not
43 * This is maintained separately from nmi_active because the NMI
44 * watchdog may also be driven from the I/O APIC timer.
46 static DEFINE_SPINLOCK(lapic_nmi_owner_lock);
47 static unsigned int lapic_nmi_owner;
48 #define LAPIC_NMI_WATCHDOG (1<<0)
49 #define LAPIC_NMI_RESERVED (1<<1)
51 /* nmi_active:
52 * +1: the lapic NMI watchdog is active, but can be disabled
53 * 0: the lapic NMI watchdog has not been set up, and cannot
54 * be enabled
55 * -1: the lapic NMI watchdog is disabled, but can be enabled
57 int nmi_active; /* oprofile uses this */
58 int panic_on_timeout;
60 unsigned int nmi_watchdog = NMI_DEFAULT;
61 static unsigned int nmi_hz = HZ;
62 static unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
63 static unsigned int nmi_p4_cccr_val;
65 /* Note that these events don't tick when the CPU idles. This means
66 the frequency varies with CPU load. */
68 #define K7_EVNTSEL_ENABLE (1 << 22)
69 #define K7_EVNTSEL_INT (1 << 20)
70 #define K7_EVNTSEL_OS (1 << 17)
71 #define K7_EVNTSEL_USR (1 << 16)
72 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
73 #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
75 #define MSR_P4_MISC_ENABLE 0x1A0
76 #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
77 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
78 #define MSR_P4_PERFCTR0 0x300
79 #define MSR_P4_CCCR0 0x360
80 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
81 #define P4_ESCR_OS (1<<3)
82 #define P4_ESCR_USR (1<<2)
83 #define P4_CCCR_OVF_PMI0 (1<<26)
84 #define P4_CCCR_OVF_PMI1 (1<<27)
85 #define P4_CCCR_THRESHOLD(N) ((N)<<20)
86 #define P4_CCCR_COMPLEMENT (1<<19)
87 #define P4_CCCR_COMPARE (1<<18)
88 #define P4_CCCR_REQUIRED (3<<16)
89 #define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
90 #define P4_CCCR_ENABLE (1<<12)
91 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
92 CRU_ESCR0 (with any non-null event selector) through a complemented
93 max threshold. [IA32-Vol3, Section 14.9.9] */
94 #define MSR_P4_IQ_COUNTER0 0x30C
95 #define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
96 #define P4_NMI_IQ_CCCR0 \
97 (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
98 P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
100 static __cpuinit inline int nmi_known_cpu(void)
102 switch (boot_cpu_data.x86_vendor) {
103 case X86_VENDOR_AMD:
104 return boot_cpu_data.x86 == 15;
105 case X86_VENDOR_INTEL:
106 return boot_cpu_data.x86 == 15;
108 return 0;
111 /* Run after command line and cpu_init init, but before all other checks */
112 void __cpuinit nmi_watchdog_default(void)
114 if (nmi_watchdog != NMI_DEFAULT)
115 return;
116 if (nmi_known_cpu())
117 nmi_watchdog = NMI_LOCAL_APIC;
118 else
119 nmi_watchdog = NMI_IO_APIC;
122 #ifdef CONFIG_SMP
123 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
124 * the CPU is idle. To make sure the NMI watchdog really ticks on all
125 * CPUs during the test make them busy.
127 static __init void nmi_cpu_busy(void *data)
129 volatile int *endflag = data;
130 local_irq_enable();
131 /* Intentionally don't use cpu_relax here. This is
132 to make sure that the performance counter really ticks,
133 even if there is a simulator or similar that catches the
134 pause instruction. On a real HT machine this is fine because
135 all other CPUs are busy with "useless" delay loops and don't
136 care if they get somewhat less cycles. */
137 while (*endflag == 0)
138 barrier();
140 #endif
142 int __init check_nmi_watchdog (void)
144 volatile int endflag = 0;
145 int *counts;
146 int cpu;
148 counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
149 if (!counts)
150 return -1;
152 printk(KERN_INFO "testing NMI watchdog ... ");
154 #ifdef CONFIG_SMP
155 if (nmi_watchdog == NMI_LOCAL_APIC)
156 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
157 #endif
159 for (cpu = 0; cpu < NR_CPUS; cpu++)
160 counts[cpu] = cpu_pda(cpu)->__nmi_count;
161 local_irq_enable();
162 mdelay((10*1000)/nmi_hz); // wait 10 ticks
164 for (cpu = 0; cpu < NR_CPUS; cpu++) {
165 if (!cpu_online(cpu))
166 continue;
167 if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
168 endflag = 1;
169 printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
170 cpu,
171 counts[cpu],
172 cpu_pda(cpu)->__nmi_count);
173 nmi_active = 0;
174 lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
175 nmi_perfctr_msr = 0;
176 kfree(counts);
177 return -1;
180 endflag = 1;
181 printk("OK.\n");
183 /* now that we know it works we can reduce NMI frequency to
184 something more reasonable; makes a difference in some configs */
185 if (nmi_watchdog == NMI_LOCAL_APIC)
186 nmi_hz = 1;
188 kfree(counts);
189 return 0;
192 int __init setup_nmi_watchdog(char *str)
194 int nmi;
196 if (!strncmp(str,"panic",5)) {
197 panic_on_timeout = 1;
198 str = strchr(str, ',');
199 if (!str)
200 return 1;
201 ++str;
204 get_option(&str, &nmi);
206 if (nmi >= NMI_INVALID)
207 return 0;
208 nmi_watchdog = nmi;
209 return 1;
212 __setup("nmi_watchdog=", setup_nmi_watchdog);
214 static void disable_lapic_nmi_watchdog(void)
216 if (nmi_active <= 0)
217 return;
218 switch (boot_cpu_data.x86_vendor) {
219 case X86_VENDOR_AMD:
220 wrmsr(MSR_K7_EVNTSEL0, 0, 0);
221 break;
222 case X86_VENDOR_INTEL:
223 if (boot_cpu_data.x86 == 15) {
224 wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
225 wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
227 break;
229 nmi_active = -1;
230 /* tell do_nmi() and others that we're not active any more */
231 nmi_watchdog = 0;
234 static void enable_lapic_nmi_watchdog(void)
236 if (nmi_active < 0) {
237 nmi_watchdog = NMI_LOCAL_APIC;
238 setup_apic_nmi_watchdog();
242 int reserve_lapic_nmi(void)
244 unsigned int old_owner;
246 spin_lock(&lapic_nmi_owner_lock);
247 old_owner = lapic_nmi_owner;
248 lapic_nmi_owner |= LAPIC_NMI_RESERVED;
249 spin_unlock(&lapic_nmi_owner_lock);
250 if (old_owner & LAPIC_NMI_RESERVED)
251 return -EBUSY;
252 if (old_owner & LAPIC_NMI_WATCHDOG)
253 disable_lapic_nmi_watchdog();
254 return 0;
257 void release_lapic_nmi(void)
259 unsigned int new_owner;
261 spin_lock(&lapic_nmi_owner_lock);
262 new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
263 lapic_nmi_owner = new_owner;
264 spin_unlock(&lapic_nmi_owner_lock);
265 if (new_owner & LAPIC_NMI_WATCHDOG)
266 enable_lapic_nmi_watchdog();
269 void disable_timer_nmi_watchdog(void)
271 if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
272 return;
274 disable_irq(0);
275 unset_nmi_callback();
276 nmi_active = -1;
277 nmi_watchdog = NMI_NONE;
280 void enable_timer_nmi_watchdog(void)
282 if (nmi_active < 0) {
283 nmi_watchdog = NMI_IO_APIC;
284 touch_nmi_watchdog();
285 nmi_active = 1;
286 enable_irq(0);
290 #ifdef CONFIG_PM
292 static int nmi_pm_active; /* nmi_active before suspend */
294 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
296 nmi_pm_active = nmi_active;
297 disable_lapic_nmi_watchdog();
298 return 0;
301 static int lapic_nmi_resume(struct sys_device *dev)
303 if (nmi_pm_active > 0)
304 enable_lapic_nmi_watchdog();
305 return 0;
308 static struct sysdev_class nmi_sysclass = {
309 set_kset_name("lapic_nmi"),
310 .resume = lapic_nmi_resume,
311 .suspend = lapic_nmi_suspend,
314 static struct sys_device device_lapic_nmi = {
315 .id = 0,
316 .cls = &nmi_sysclass,
319 static int __init init_lapic_nmi_sysfs(void)
321 int error;
323 if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
324 return 0;
326 error = sysdev_class_register(&nmi_sysclass);
327 if (!error)
328 error = sysdev_register(&device_lapic_nmi);
329 return error;
331 /* must come after the local APIC's device_initcall() */
332 late_initcall(init_lapic_nmi_sysfs);
334 #endif /* CONFIG_PM */
337 * Activate the NMI watchdog via the local APIC.
338 * Original code written by Keith Owens.
341 static void clear_msr_range(unsigned int base, unsigned int n)
343 unsigned int i;
345 for(i = 0; i < n; ++i)
346 wrmsr(base+i, 0, 0);
349 static void setup_k7_watchdog(void)
351 int i;
352 unsigned int evntsel;
354 nmi_perfctr_msr = MSR_K7_PERFCTR0;
356 for(i = 0; i < 4; ++i) {
357 /* Simulator may not support it */
358 if (checking_wrmsrl(MSR_K7_EVNTSEL0+i, 0UL)) {
359 nmi_perfctr_msr = 0;
360 return;
362 wrmsrl(MSR_K7_PERFCTR0+i, 0UL);
365 evntsel = K7_EVNTSEL_INT
366 | K7_EVNTSEL_OS
367 | K7_EVNTSEL_USR
368 | K7_NMI_EVENT;
370 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
371 wrmsrl(MSR_K7_PERFCTR0, -((u64)cpu_khz * 1000 / nmi_hz));
372 apic_write(APIC_LVTPC, APIC_DM_NMI);
373 evntsel |= K7_EVNTSEL_ENABLE;
374 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
378 static int setup_p4_watchdog(void)
380 unsigned int misc_enable, dummy;
382 rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
383 if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
384 return 0;
386 nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
387 nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
388 #ifdef CONFIG_SMP
389 if (smp_num_siblings == 2)
390 nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
391 #endif
393 if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
394 clear_msr_range(0x3F1, 2);
395 /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
396 docs doesn't fully define it, so leave it alone for now. */
397 if (boot_cpu_data.x86_model >= 0x3) {
398 /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
399 clear_msr_range(0x3A0, 26);
400 clear_msr_range(0x3BC, 3);
401 } else {
402 clear_msr_range(0x3A0, 31);
404 clear_msr_range(0x3C0, 6);
405 clear_msr_range(0x3C8, 6);
406 clear_msr_range(0x3E0, 2);
407 clear_msr_range(MSR_P4_CCCR0, 18);
408 clear_msr_range(MSR_P4_PERFCTR0, 18);
410 wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
411 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
412 Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz * 1000UL / nmi_hz));
413 wrmsrl(MSR_P4_IQ_COUNTER0, -((u64)cpu_khz * 1000 / nmi_hz));
414 apic_write(APIC_LVTPC, APIC_DM_NMI);
415 wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
416 return 1;
419 void setup_apic_nmi_watchdog(void)
421 switch (boot_cpu_data.x86_vendor) {
422 case X86_VENDOR_AMD:
423 if (boot_cpu_data.x86 != 15)
424 return;
425 if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
426 return;
427 setup_k7_watchdog();
428 break;
429 case X86_VENDOR_INTEL:
430 if (boot_cpu_data.x86 != 15)
431 return;
432 if (!setup_p4_watchdog())
433 return;
434 break;
436 default:
437 return;
439 lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
440 nmi_active = 1;
444 * the best way to detect whether a CPU has a 'hard lockup' problem
445 * is to check it's local APIC timer IRQ counts. If they are not
446 * changing then that CPU has some problem.
448 * as these watchdog NMI IRQs are generated on every CPU, we only
449 * have to check the current processor.
452 static DEFINE_PER_CPU(unsigned, last_irq_sum);
453 static DEFINE_PER_CPU(local_t, alert_counter);
454 static DEFINE_PER_CPU(int, nmi_touch);
456 void touch_nmi_watchdog (void)
458 int i;
461 * Tell other CPUs to reset their alert counters. We cannot
462 * do it ourselves because the alert count increase is not
463 * atomic.
465 for (i = 0; i < NR_CPUS; i++)
466 per_cpu(nmi_touch, i) = 1;
468 touch_softlockup_watchdog();
471 void nmi_watchdog_tick (struct pt_regs * regs, unsigned reason)
473 int sum;
474 int touched = 0;
476 sum = read_pda(apic_timer_irqs);
477 if (__get_cpu_var(nmi_touch)) {
478 __get_cpu_var(nmi_touch) = 0;
479 touched = 1;
481 if (!touched && __get_cpu_var(last_irq_sum) == sum) {
483 * Ayiee, looks like this CPU is stuck ...
484 * wait a few IRQs (5 seconds) before doing the oops ...
486 local_inc(&__get_cpu_var(alert_counter));
487 if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz) {
488 if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
489 == NOTIFY_STOP) {
490 local_set(&__get_cpu_var(alert_counter), 0);
491 return;
493 die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs);
495 } else {
496 __get_cpu_var(last_irq_sum) = sum;
497 local_set(&__get_cpu_var(alert_counter), 0);
499 if (nmi_perfctr_msr) {
500 if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
502 * P4 quirks:
503 * - An overflown perfctr will assert its interrupt
504 * until the OVF flag in its CCCR is cleared.
505 * - LVTPC is masked on interrupt and must be
506 * unmasked by the LVTPC handler.
508 wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
509 apic_write(APIC_LVTPC, APIC_DM_NMI);
511 wrmsrl(nmi_perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
515 static int dummy_nmi_callback(struct pt_regs * regs, int cpu)
517 return 0;
520 static nmi_callback_t nmi_callback = dummy_nmi_callback;
522 asmlinkage void do_nmi(struct pt_regs * regs, long error_code)
524 int cpu = safe_smp_processor_id();
526 nmi_enter();
527 add_pda(__nmi_count,1);
528 if (!rcu_dereference(nmi_callback)(regs, cpu))
529 default_do_nmi(regs);
530 nmi_exit();
533 void set_nmi_callback(nmi_callback_t callback)
535 rcu_assign_pointer(nmi_callback, callback);
538 void unset_nmi_callback(void)
540 nmi_callback = dummy_nmi_callback;
543 #ifdef CONFIG_SYSCTL
545 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
547 unsigned char reason = get_nmi_reason();
548 char buf[64];
550 if (!(reason & 0xc0)) {
551 sprintf(buf, "NMI received for unknown reason %02x\n", reason);
552 die_nmi(buf,regs);
554 return 0;
558 * proc handler for /proc/sys/kernel/unknown_nmi_panic
560 int proc_unknown_nmi_panic(struct ctl_table *table, int write, struct file *file,
561 void __user *buffer, size_t *length, loff_t *ppos)
563 int old_state;
565 old_state = unknown_nmi_panic;
566 proc_dointvec(table, write, file, buffer, length, ppos);
567 if (!!old_state == !!unknown_nmi_panic)
568 return 0;
570 if (unknown_nmi_panic) {
571 if (reserve_lapic_nmi() < 0) {
572 unknown_nmi_panic = 0;
573 return -EBUSY;
574 } else {
575 set_nmi_callback(unknown_nmi_panic_callback);
577 } else {
578 release_lapic_nmi();
579 unset_nmi_callback();
581 return 0;
584 #endif
586 EXPORT_SYMBOL(nmi_active);
587 EXPORT_SYMBOL(nmi_watchdog);
588 EXPORT_SYMBOL(reserve_lapic_nmi);
589 EXPORT_SYMBOL(release_lapic_nmi);
590 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
591 EXPORT_SYMBOL(enable_timer_nmi_watchdog);
592 EXPORT_SYMBOL(touch_nmi_watchdog);