1 #ifndef _ASM_M32R_BITOPS_H
2 #define _ASM_M32R_BITOPS_H
5 * linux/include/asm-m32r/bitops.h
7 * Copyright 1992, Linus Torvalds.
10 * Copyright (C) 2001, 2002 Hitoshi Yamamoto
11 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
14 #include <linux/compiler.h>
15 #include <asm/assembler.h>
16 #include <asm/system.h>
17 #include <asm/byteorder.h>
18 #include <asm/types.h>
21 * These have to be done with inline assembly: that way the bit-setting
22 * is guaranteed to be atomic. All bit operations return 0 if the bit
23 * was cleared before the operation and != 0 if it was not.
25 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
29 * set_bit - Atomically set a bit in memory
31 * @addr: the address to start counting from
33 * This function is atomic and may not be reordered. See __set_bit()
34 * if you do not require the atomic guarantees.
35 * Note that @nr may be almost arbitrarily large; this function is not
36 * restricted to acting on a single-word quantity.
38 static __inline__
void set_bit(int nr
, volatile void * addr
)
41 volatile __u32
*a
= addr
;
46 mask
= (1 << (nr
& 0x1F));
48 local_irq_save(flags
);
49 __asm__
__volatile__ (
50 DCACHE_CLEAR("%0", "r6", "%1")
51 M32R_LOCK
" %0, @%1; \n\t"
53 M32R_UNLOCK
" %0, @%1; \n\t"
57 #ifdef CONFIG_CHIP_M32700_TS1
59 #endif /* CONFIG_CHIP_M32700_TS1 */
61 local_irq_restore(flags
);
65 * clear_bit - Clears a bit in memory
67 * @addr: Address to start counting from
69 * clear_bit() is atomic and may not be reordered. However, it does
70 * not contain a memory barrier, so if it is used for locking purposes,
71 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
72 * in order to ensure changes are visible on other processors.
74 static __inline__
void clear_bit(int nr
, volatile void * addr
)
77 volatile __u32
*a
= addr
;
82 mask
= (1 << (nr
& 0x1F));
84 local_irq_save(flags
);
86 __asm__
__volatile__ (
87 DCACHE_CLEAR("%0", "r6", "%1")
88 M32R_LOCK
" %0, @%1; \n\t"
90 M32R_UNLOCK
" %0, @%1; \n\t"
92 : "r" (a
), "r" (~mask
)
94 #ifdef CONFIG_CHIP_M32700_TS1
96 #endif /* CONFIG_CHIP_M32700_TS1 */
98 local_irq_restore(flags
);
101 #define smp_mb__before_clear_bit() barrier()
102 #define smp_mb__after_clear_bit() barrier()
105 * change_bit - Toggle a bit in memory
107 * @addr: Address to start counting from
109 * change_bit() is atomic and may not be reordered.
110 * Note that @nr may be almost arbitrarily large; this function is not
111 * restricted to acting on a single-word quantity.
113 static __inline__
void change_bit(int nr
, volatile void * addr
)
116 volatile __u32
*a
= addr
;
121 mask
= (1 << (nr
& 0x1F));
123 local_irq_save(flags
);
124 __asm__
__volatile__ (
125 DCACHE_CLEAR("%0", "r6", "%1")
126 M32R_LOCK
" %0, @%1; \n\t"
128 M32R_UNLOCK
" %0, @%1; \n\t"
130 : "r" (a
), "r" (mask
)
132 #ifdef CONFIG_CHIP_M32700_TS1
134 #endif /* CONFIG_CHIP_M32700_TS1 */
136 local_irq_restore(flags
);
140 * test_and_set_bit - Set a bit and return its old value
142 * @addr: Address to count from
144 * This operation is atomic and cannot be reordered.
145 * It also implies a memory barrier.
147 static __inline__
int test_and_set_bit(int nr
, volatile void * addr
)
150 volatile __u32
*a
= addr
;
155 mask
= (1 << (nr
& 0x1F));
157 local_irq_save(flags
);
158 __asm__
__volatile__ (
159 DCACHE_CLEAR("%0", "%1", "%2")
160 M32R_LOCK
" %0, @%2; \n\t"
164 M32R_UNLOCK
" %1, @%2; \n\t"
165 : "=&r" (oldbit
), "=&r" (tmp
)
166 : "r" (a
), "r" (mask
)
169 local_irq_restore(flags
);
171 return (oldbit
!= 0);
175 * test_and_clear_bit - Clear a bit and return its old value
177 * @addr: Address to count from
179 * This operation is atomic and cannot be reordered.
180 * It also implies a memory barrier.
182 static __inline__
int test_and_clear_bit(int nr
, volatile void * addr
)
185 volatile __u32
*a
= addr
;
190 mask
= (1 << (nr
& 0x1F));
192 local_irq_save(flags
);
194 __asm__
__volatile__ (
195 DCACHE_CLEAR("%0", "%1", "%3")
196 M32R_LOCK
" %0, @%3; \n\t"
201 M32R_UNLOCK
" %1, @%3; \n\t"
202 : "=&r" (oldbit
), "=&r" (tmp
), "+r" (mask
)
206 local_irq_restore(flags
);
208 return (oldbit
!= 0);
212 * test_and_change_bit - Change a bit and return its old value
214 * @addr: Address to count from
216 * This operation is atomic and cannot be reordered.
217 * It also implies a memory barrier.
219 static __inline__
int test_and_change_bit(int nr
, volatile void * addr
)
222 volatile __u32
*a
= addr
;
227 mask
= (1 << (nr
& 0x1F));
229 local_irq_save(flags
);
230 __asm__
__volatile__ (
231 DCACHE_CLEAR("%0", "%1", "%2")
232 M32R_LOCK
" %0, @%2; \n\t"
236 M32R_UNLOCK
" %1, @%2; \n\t"
237 : "=&r" (oldbit
), "=&r" (tmp
)
238 : "r" (a
), "r" (mask
)
241 local_irq_restore(flags
);
243 return (oldbit
!= 0);
246 #include <asm-generic/bitops/non-atomic.h>
247 #include <asm-generic/bitops/ffz.h>
248 #include <asm-generic/bitops/__ffs.h>
249 #include <asm-generic/bitops/fls.h>
250 #include <asm-generic/bitops/fls64.h>
254 #include <asm-generic/bitops/sched.h>
255 #include <asm-generic/bitops/find.h>
256 #include <asm-generic/bitops/ffs.h>
257 #include <asm-generic/bitops/hweight.h>
258 #include <asm-generic/bitops/lock.h>
260 #endif /* __KERNEL__ */
264 #include <asm-generic/bitops/ext2-non-atomic.h>
265 #include <asm-generic/bitops/ext2-atomic.h>
266 #include <asm-generic/bitops/minix.h>
268 #endif /* __KERNEL__ */
270 #endif /* _ASM_M32R_BITOPS_H */