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pm2fb: Permedia 2V initialization fixes
[linux-2.6/pdupreez.git] / drivers / video / pm2fb.c
bloba5ccddc141a0f4d65543b89437a8de5862a2f0ca
1 /*
2 * Permedia2 framebuffer driver.
3 *
4 * 2.5/2.6 driver:
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
6 *
7 * based on 2.4 driver:
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
10 *
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
12 * driver.
13 *
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
19 *
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
25 * more details.
26 *
27 *
28 */
29
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/kernel.h>
33 #include <linux/errno.h>
34 #include <linux/string.h>
35 #include <linux/mm.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38 #include <linux/fb.h>
39 #include <linux/init.h>
40 #include <linux/pci.h>
41 #ifdef CONFIG_MTRR
42 #include <asm/mtrr.h>
43 #endif
44
45 #include <video/permedia2.h>
46 #include <video/cvisionppc.h>
47
48 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
49 #error "The endianness of the target host has not been defined."
50 #endif
51
52 #if !defined(CONFIG_PCI)
53 #error "Only generic PCI cards supported."
54 #endif
55
56 #undef PM2FB_MASTER_DEBUG
57 #ifdef PM2FB_MASTER_DEBUG
58 #define DPRINTK(a,b...) printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)
59 #else
60 #define DPRINTK(a,b...)
61 #endif
62
63 #define PM2_PIXMAP_SIZE (1600 * 4)
64
65 /*
66 * Driver data
67 */
68 static char *mode __devinitdata = NULL;
69
70 /*
71 * The XFree GLINT driver will (I think to implement hardware cursor
72 * support on TVP4010 and similar where there is no RAMDAC - see
73 * comment in set_video) always request +ve sync regardless of what
74 * the mode requires. This screws me because I have a Sun
75 * fixed-frequency monitor which absolutely has to have -ve sync. So
76 * these flags allow the user to specify that requests for +ve sync
77 * should be silently turned in -ve sync.
78 */
79 static int lowhsync;
80 static int lowvsync;
81 static int noaccel __devinitdata;
82 /* mtrr option */
83 #ifdef CONFIG_MTRR
84 static int nomtrr __devinitdata;
85 #endif
86
87 /*
88 * The hardware state of the graphics card that isn't part of the
89 * screeninfo.
90 */
91 struct pm2fb_par
92 {
93 pm2type_t type; /* Board type */
94 unsigned char __iomem *v_regs;/* virtual address of p_regs */
95 u32 memclock; /* memclock */
96 u32 video; /* video flags before blanking */
97 u32 mem_config; /* MemConfig reg at probe */
98 u32 mem_control; /* MemControl reg at probe */
99 u32 boot_address; /* BootAddress reg at probe */
100 u32 palette[16];
101 int mtrr_handle;
102 };
103
104 /*
105 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
106 * if we don't use modedb.
107 */
108 static struct fb_fix_screeninfo pm2fb_fix __devinitdata = {
109 .id = "",
110 .type = FB_TYPE_PACKED_PIXELS,
111 .visual = FB_VISUAL_PSEUDOCOLOR,
112 .xpanstep = 1,
113 .ypanstep = 1,
114 .ywrapstep = 0,
115 .accel = FB_ACCEL_3DLABS_PERMEDIA2,
116 };
117
118 /*
119 * Default video mode. In case the modedb doesn't work.
120 */
121 static struct fb_var_screeninfo pm2fb_var __devinitdata = {
122 /* "640x480, 8 bpp @ 60 Hz */
123 .xres = 640,
124 .yres = 480,
125 .xres_virtual = 640,
126 .yres_virtual = 480,
127 .bits_per_pixel = 8,
128 .red = {0, 8, 0},
129 .blue = {0, 8, 0},
130 .green = {0, 8, 0},
131 .activate = FB_ACTIVATE_NOW,
132 .height = -1,
133 .width = -1,
134 .accel_flags = 0,
135 .pixclock = 39721,
136 .left_margin = 40,
137 .right_margin = 24,
138 .upper_margin = 32,
139 .lower_margin = 11,
140 .hsync_len = 96,
141 .vsync_len = 2,
142 .vmode = FB_VMODE_NONINTERLACED
143 };
144
145 /*
146 * Utility functions
147 */
148
149 static inline u32 pm2_RD(struct pm2fb_par* p, s32 off)
150 {
151 return fb_readl(p->v_regs + off);
152 }
153
154 static inline void pm2_WR(struct pm2fb_par* p, s32 off, u32 v)
155 {
156 fb_writel(v, p->v_regs + off);
157 }
158
159 static inline u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)
160 {
161 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
162 mb();
163 return pm2_RD(p, PM2R_RD_INDEXED_DATA);
164 }
165
166 static inline u32 pm2v_RDAC_RD(struct pm2fb_par* p, s32 idx)
167 {
168 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
169 mb();
170 return pm2_RD(p, PM2VR_RD_INDEXED_DATA);
171 }
172
173 static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
174 {
175 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
176 wmb();
177 pm2_WR(p, PM2R_RD_INDEXED_DATA, v);
178 wmb();
179 }
180
181 static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
182 {
183 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
184 wmb();
185 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
186 wmb();
187 }
188
189 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
190 #define WAIT_FIFO(p, a)
191 #else
192 static inline void WAIT_FIFO(struct pm2fb_par* p, u32 a)
193 {
194 while(pm2_RD(p, PM2R_IN_FIFO_SPACE) < a);
195 mb();
196 }
197 #endif
198
199 /*
200 * partial products for the supported horizontal resolutions.
201 */
202 #define PACKPP(p0, p1, p2) (((p2) << 6) | ((p1) << 3) | (p0))
203 static const struct {
204 u16 width;
205 u16 pp;
206 } pp_table[] = {
207 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
208 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
209 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
210 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
211 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
212 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
213 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
214 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
215 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
216 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
217 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
218 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
219 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
220 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
221 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
222 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
223 { 0, 0 } };
224
225 static u32 partprod(u32 xres)
226 {
227 int i;
228
229 for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
230 ;
231 if (pp_table[i].width == 0)
232 DPRINTK("invalid width %u\n", xres);
233 return pp_table[i].pp;
234 }
235
236 static u32 to3264(u32 timing, int bpp, int is64)
237 {
238 switch (bpp) {
239 case 24:
240 timing *= 3;
241 case 8:
242 timing >>= 1;
243 case 16:
244 timing >>= 1;
245 case 32:
246 break;
247 }
248 if (is64)
249 timing >>= 1;
250 return timing;
251 }
252
253 static void pm2_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
254 unsigned char* pp)
255 {
256 unsigned char m;
257 unsigned char n;
258 unsigned char p;
259 u32 f;
260 s32 curr;
261 s32 delta = 100000;
262
263 *mm = *nn = *pp = 0;
264 for (n = 2; n < 15; n++) {
265 for (m = 2; m; m++) {
266 f = PM2_REFERENCE_CLOCK * m / n;
267 if (f >= 150000 && f <= 300000) {
268 for (p = 0; p < 5; p++, f >>= 1) {
269 curr = (clk > f) ? clk - f : f - clk;
270 if (curr < delta) {
271 delta = curr;
272 *mm = m;
273 *nn = n;
274 *pp = p;
275 }
276 }
277 }
278 }
279 }
280 }
281
282 static void pm2v_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
283 unsigned char* pp)
284 {
285 unsigned char m;
286 unsigned char n;
287 unsigned char p;
288 u32 f;
289 s32 delta = 1000;
290
291 *mm = *nn = *pp = 0;
292 for (m = 1; m < 128; m++) {
293 for (n = 2 * m + 1; n; n++) {
294 for (p = 0; p < 2; p++) {
295 f = (PM2_REFERENCE_CLOCK >> (p + 1)) * n / m;
296 if (clk > f - delta && clk < f + delta) {
297 delta = (clk > f) ? clk - f : f - clk;
298 *mm = m;
299 *nn = n;
300 *pp = p;
301 }
302 }
303 }
304 }
305 }
306
307 static void clear_palette(struct pm2fb_par* p) {
308 int i = 256;
309
310 WAIT_FIFO(p, 1);
311 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
312 wmb();
313 while (i--) {
314 WAIT_FIFO(p, 3);
315 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
316 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
317 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
318 }
319 }
320
321 static void reset_card(struct pm2fb_par* p)
322 {
323 if (p->type == PM2_TYPE_PERMEDIA2V)
324 pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
325 pm2_WR(p, PM2R_RESET_STATUS, 0);
326 mb();
327 while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
328 ;
329 mb();
330 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
331 DPRINTK("FIFO disconnect enabled\n");
332 pm2_WR(p, PM2R_FIFO_DISCON, 1);
333 mb();
334 #endif
335
336 /* Restore stashed memory config information from probe */
337 WAIT_FIFO(p, 3);
338 pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
339 pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
340 wmb();
341 pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
342 }
343
344 static void reset_config(struct pm2fb_par* p)
345 {
346 WAIT_FIFO(p, 53);
347 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) &
348 ~(PM2F_VGA_ENABLE | PM2F_VGA_FIXED));
349 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
350 pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
351 pm2_WR(p, PM2R_FIFO_CONTROL, 0);
352 pm2_WR(p, PM2R_APERTURE_ONE, 0);
353 pm2_WR(p, PM2R_APERTURE_TWO, 0);
354 pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
355 pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
356 pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
357 pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
358 pm2_WR(p, PM2R_LB_READ_MODE, 0);
359 pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
360 pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
361 pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
362 pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
363 pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
364 pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
365 pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
366 pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
367 pm2_WR(p, PM2R_DITHER_MODE, 0);
368 pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
369 pm2_WR(p, PM2R_DEPTH_MODE, 0);
370 pm2_WR(p, PM2R_STENCIL_MODE, 0);
371 pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
372 pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
373 pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
374 pm2_WR(p, PM2R_YUV_MODE, 0);
375 pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
376 pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
377 pm2_WR(p, PM2R_FOG_MODE, 0);
378 pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
379 pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
380 pm2_WR(p, PM2R_STATISTICS_MODE, 0);
381 pm2_WR(p, PM2R_SCISSOR_MODE, 0);
382 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
383 pm2_WR(p, PM2R_RD_PIXEL_MASK, 0xff);
384 switch (p->type) {
385 case PM2_TYPE_PERMEDIA2:
386 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
387 pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
388 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
389 pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
390 pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
391 pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
392 pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
393 pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
394 break;
395 case PM2_TYPE_PERMEDIA2V:
396 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
397 break;
398 }
399 }
400
401 static void set_aperture(struct pm2fb_par* p, u32 depth)
402 {
403 /*
404 * The hardware is little-endian. When used in big-endian
405 * hosts, the on-chip aperture settings are used where
406 * possible to translate from host to card byte order.
407 */
408 WAIT_FIFO(p, 2);
409 #ifdef __LITTLE_ENDIAN
410 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
411 #else
412 switch (depth) {
413 case 24: /* RGB->BGR */
414 /*
415 * We can't use the aperture to translate host to
416 * card byte order here, so we switch to BGR mode
417 * in pm2fb_set_par().
418 */
419 case 8: /* B->B */
420 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
421 break;
422 case 16: /* HL->LH */
423 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
424 break;
425 case 32: /* RGBA->ABGR */
426 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
427 break;
428 }
429 #endif
430
431 // We don't use aperture two, so this may be superflous
432 pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
433 }
434
435 static void set_color(struct pm2fb_par* p, unsigned char regno,
436 unsigned char r, unsigned char g, unsigned char b)
437 {
438 WAIT_FIFO(p, 4);
439 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
440 wmb();
441 pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
442 wmb();
443 pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
444 wmb();
445 pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
446 }
447
448 static void set_memclock(struct pm2fb_par* par, u32 clk)
449 {
450 int i;
451 unsigned char m, n, p;
452
453 switch (par->type) {
454 case PM2_TYPE_PERMEDIA2V:
455 pm2v_mnp(clk/2, &m, &n, &p);
456 WAIT_FIFO(par, 12);
457 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8);
458 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0);
459 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m);
460 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n);
461 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p);
462 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1);
463 rmb();
464 for (i = 256; i; i--)
465 if (pm2v_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2)
466 break;
467 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
468 break;
469 case PM2_TYPE_PERMEDIA2:
470 pm2_mnp(clk, &m, &n, &p);
471 WAIT_FIFO(par, 10);
472 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
473 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
474 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
475 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
476 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
477 rmb();
478 for (i = 256; i; i--)
479 if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED)
480 break;
481 break;
482 }
483 }
484
485 static void set_pixclock(struct pm2fb_par* par, u32 clk)
486 {
487 int i;
488 unsigned char m, n, p;
489
490 switch (par->type) {
491 case PM2_TYPE_PERMEDIA2:
492 pm2_mnp(clk, &m, &n, &p);
493 WAIT_FIFO(par, 10);
494 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
495 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
496 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
497 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
498 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
499 rmb();
500 for (i = 256; i; i--)
501 if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED)
502 break;
503 break;
504 case PM2_TYPE_PERMEDIA2V:
505 pm2v_mnp(clk/2, &m, &n, &p);
506 WAIT_FIFO(par, 8);
507 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
508 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
509 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
510 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
511 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
512 break;
513 }
514 }
515
516 static void set_video(struct pm2fb_par* p, u32 video) {
517 u32 tmp;
518 u32 vsync = video;
519
520 DPRINTK("video = 0x%x\n", video);
521
522 /*
523 * The hardware cursor needs +vsync to recognise vert retrace.
524 * We may not be using the hardware cursor, but the X Glint
525 * driver may well. So always set +hsync/+vsync and then set
526 * the RAMDAC to invert the sync if necessary.
527 */
528 vsync &= ~(PM2F_HSYNC_MASK | PM2F_VSYNC_MASK);
529 vsync |= PM2F_HSYNC_ACT_HIGH | PM2F_VSYNC_ACT_HIGH;
530
531 WAIT_FIFO(p, 3);
532 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
533
534 switch (p->type) {
535 case PM2_TYPE_PERMEDIA2:
536 tmp = PM2F_RD_PALETTE_WIDTH_8;
537 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
538 tmp |= 4; /* invert hsync */
539 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
540 tmp |= 8; /* invert vsync */
541 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
542 break;
543 case PM2_TYPE_PERMEDIA2V:
544 tmp = 0;
545 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
546 tmp |= 1; /* invert hsync */
547 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
548 tmp |= 4; /* invert vsync */
549 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
550 break;
551 }
552 }
553
554 /*
555 * pm2fb_check_var - Optional function. Validates a var passed in.
556 * @var: frame buffer variable screen structure
557 * @info: frame buffer structure that represents a single frame buffer
558 *
559 * Checks to see if the hardware supports the state requested by
560 * var passed in.
561 *
562 * Returns negative errno on error, or zero on success.
563 */
564 static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
565 {
566 u32 lpitch;
567
568 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
569 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
570 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
571 return -EINVAL;
572 }
573
574 if (var->xres != var->xres_virtual) {
575 DPRINTK("virtual x resolution != physical x resolution not supported\n");
576 return -EINVAL;
577 }
578
579 if (var->yres > var->yres_virtual) {
580 DPRINTK("virtual y resolution < physical y resolution not possible\n");
581 return -EINVAL;
582 }
583
584 if (var->xoffset) {
585 DPRINTK("xoffset not supported\n");
586 return -EINVAL;
587 }
588
589 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
590 DPRINTK("interlace not supported\n");
591 return -EINVAL;
592 }
593
594 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
595 lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
596
597 if (var->xres < 320 || var->xres > 1600) {
598 DPRINTK("width not supported: %u\n", var->xres);
599 return -EINVAL;
600 }
601
602 if (var->yres < 200 || var->yres > 1200) {
603 DPRINTK("height not supported: %u\n", var->yres);
604 return -EINVAL;
605 }
606
607 if (lpitch * var->yres_virtual > info->fix.smem_len) {
608 DPRINTK("no memory for screen (%ux%ux%u)\n",
609 var->xres, var->yres_virtual, var->bits_per_pixel);
610 return -EINVAL;
611 }
612
613 if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
614 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
615 return -EINVAL;
616 }
617
618 var->transp.offset = 0;
619 var->transp.length = 0;
620 switch(var->bits_per_pixel) {
621 case 8:
622 var->red.length = var->green.length = var->blue.length = 8;
623 break;
624 case 16:
625 var->red.offset = 11;
626 var->red.length = 5;
627 var->green.offset = 5;
628 var->green.length = 6;
629 var->blue.offset = 0;
630 var->blue.length = 5;
631 break;
632 case 32:
633 var->transp.offset = 24;
634 var->transp.length = 8;
635 var->red.offset = 16;
636 var->green.offset = 8;
637 var->blue.offset = 0;
638 var->red.length = var->green.length = var->blue.length = 8;
639 break;
640 case 24:
641 #ifdef __BIG_ENDIAN
642 var->red.offset = 0;
643 var->blue.offset = 16;
644 #else
645 var->red.offset = 16;
646 var->blue.offset = 0;
647 #endif
648 var->green.offset = 8;
649 var->red.length = var->green.length = var->blue.length = 8;
650 break;
651 }
652 var->height = var->width = -1;
653
654 var->accel_flags = 0; /* Can't mmap if this is on */
655
656 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
657 var->xres, var->yres, var->bits_per_pixel);
658 return 0;
659 }
660
661 /**
662 * pm2fb_set_par - Alters the hardware state.
663 * @info: frame buffer structure that represents a single frame buffer
664 *
665 * Using the fb_var_screeninfo in fb_info we set the resolution of the
666 * this particular framebuffer.
667 */
668 static int pm2fb_set_par(struct fb_info *info)
669 {
670 struct pm2fb_par *par = info->par;
671 u32 pixclock;
672 u32 width = (info->var.xres_virtual + 7) & ~7;
673 u32 height = info->var.yres_virtual;
674 u32 depth = (info->var.bits_per_pixel + 7) & ~7;
675 u32 hsstart, hsend, hbend, htotal;
676 u32 vsstart, vsend, vbend, vtotal;
677 u32 stride;
678 u32 base;
679 u32 video = 0;
680 u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
681 u32 txtmap = 0;
682 u32 pixsize = 0;
683 u32 clrformat = 0;
684 u32 misc = 1; /* 8-bit DAC */
685 u32 xres = (info->var.xres + 31) & ~31;
686 int data64;
687
688 reset_card(par);
689 reset_config(par);
690 clear_palette(par);
691 if (par->memclock)
692 set_memclock(par, par->memclock);
693
694 depth = (depth > 32) ? 32 : depth;
695 data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
696
697 pixclock = PICOS2KHZ(info->var.pixclock);
698 if (pixclock > PM2_MAX_PIXCLOCK) {
699 DPRINTK("pixclock too high (%uKHz)\n", pixclock);
700 return -EINVAL;
701 }
702
703 hsstart = to3264(info->var.right_margin, depth, data64);
704 hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
705 hbend = hsend + to3264(info->var.left_margin, depth, data64);
706 htotal = to3264(xres, depth, data64) + hbend - 1;
707 vsstart = (info->var.lower_margin)
708 ? info->var.lower_margin - 1
709 : 0; /* FIXME! */
710 vsend = info->var.lower_margin + info->var.vsync_len - 1;
711 vbend = info->var.lower_margin + info->var.vsync_len + info->var.upper_margin;
712 vtotal = info->var.yres + vbend - 1;
713 stride = to3264(width, depth, 1);
714 base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
715 if (data64)
716 video |= PM2F_DATA_64_ENABLE;
717
718 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
719 if (lowhsync) {
720 DPRINTK("ignoring +hsync, using -hsync.\n");
721 video |= PM2F_HSYNC_ACT_LOW;
722 } else
723 video |= PM2F_HSYNC_ACT_HIGH;
724 }
725 else
726 video |= PM2F_HSYNC_ACT_LOW;
727 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
728 if (lowvsync) {
729 DPRINTK("ignoring +vsync, using -vsync.\n");
730 video |= PM2F_VSYNC_ACT_LOW;
731 } else
732 video |= PM2F_VSYNC_ACT_HIGH;
733 }
734 else
735 video |= PM2F_VSYNC_ACT_LOW;
736 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
737 DPRINTK("interlaced not supported\n");
738 return -EINVAL;
739 }
740 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
741 video |= PM2F_LINE_DOUBLE;
742 if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
743 video |= PM2F_VIDEO_ENABLE;
744 par->video = video;
745
746 info->fix.visual =
747 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
748 info->fix.line_length = info->var.xres * depth / 8;
749 info->cmap.len = 256;
750
751 /*
752 * Settings calculated. Now write them out.
753 */
754 if (par->type == PM2_TYPE_PERMEDIA2V) {
755 WAIT_FIFO(par, 1);
756 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
757 }
758
759 set_aperture(par, depth);
760
761 mb();
762 WAIT_FIFO(par, 19);
763 switch (depth) {
764 case 8:
765 pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
766 clrformat = 0x2e;
767 break;
768 case 16:
769 pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
770 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
771 txtmap = PM2F_TEXTEL_SIZE_16;
772 pixsize = 1;
773 clrformat = 0x70;
774 misc |= 8;
775 break;
776 case 32:
777 pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
778 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
779 txtmap = PM2F_TEXTEL_SIZE_32;
780 pixsize = 2;
781 clrformat = 0x20;
782 misc |= 8;
783 break;
784 case 24:
785 pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
786 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
787 txtmap = PM2F_TEXTEL_SIZE_24;
788 pixsize = 4;
789 clrformat = 0x20;
790 misc |= 8;
791 break;
792 }
793 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
794 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
795 pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
796 pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
797 pm2_WR(par, PM2R_H_TOTAL, htotal);
798 pm2_WR(par, PM2R_HS_START, hsstart);
799 pm2_WR(par, PM2R_HS_END, hsend);
800 pm2_WR(par, PM2R_HG_END, hbend);
801 pm2_WR(par, PM2R_HB_END, hbend);
802 pm2_WR(par, PM2R_V_TOTAL, vtotal);
803 pm2_WR(par, PM2R_VS_START, vsstart);
804 pm2_WR(par, PM2R_VS_END, vsend);
805 pm2_WR(par, PM2R_VB_END, vbend);
806 pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
807 wmb();
808 pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
809 pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
810 pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
811 wmb();
812 pm2_WR(par, PM2R_SCREEN_BASE, base);
813 wmb();
814 set_video(par, video);
815 WAIT_FIFO(par, 10);
816 switch (par->type) {
817 case PM2_TYPE_PERMEDIA2:
818 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
819 pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
820 (depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
821 break;
822 case PM2_TYPE_PERMEDIA2V:
823 pm2v_RDAC_WR(par, PM2VI_RD_DAC_CONTROL, 0);
824 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
825 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
826 pm2v_RDAC_WR(par, PM2VI_RD_MISC_CONTROL, misc);
827 pm2v_RDAC_WR(par, PM2VI_RD_OVERLAY_KEY, 0);
828 break;
829 }
830 set_pixclock(par, pixclock);
831 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
832 info->var.xres, info->var.yres, info->var.bits_per_pixel);
833 return 0;
834 }
835
836 /**
837 * pm2fb_setcolreg - Sets a color register.
838 * @regno: boolean, 0 copy local, 1 get_user() function
839 * @red: frame buffer colormap structure
840 * @green: The green value which can be up to 16 bits wide
841 * @blue: The blue value which can be up to 16 bits wide.
842 * @transp: If supported the alpha value which can be up to 16 bits wide.
843 * @info: frame buffer info structure
844 *
845 * Set a single color register. The values supplied have a 16 bit
846 * magnitude which needs to be scaled in this function for the hardware.
847 * Pretty much a direct lift from tdfxfb.c.
848 *
849 * Returns negative errno on error, or zero on success.
850 */
851 static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
852 unsigned blue, unsigned transp,
853 struct fb_info *info)
854 {
855 struct pm2fb_par *par = info->par;
856
857 if (regno >= info->cmap.len) /* no. of hw registers */
858 return -EINVAL;
859 /*
860 * Program hardware... do anything you want with transp
861 */
862
863 /* grayscale works only partially under directcolor */
864 if (info->var.grayscale) {
865 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
866 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
867 }
868
869 /* Directcolor:
870 * var->{color}.offset contains start of bitfield
871 * var->{color}.length contains length of bitfield
872 * {hardwarespecific} contains width of DAC
873 * cmap[X] is programmed to
874 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
875 * RAMDAC[X] is programmed to (red, green, blue)
876 *
877 * Pseudocolor:
878 * uses offset = 0 && length = DAC register width.
879 * var->{color}.offset is 0
880 * var->{color}.length contains widht of DAC
881 * cmap is not used
882 * DAC[X] is programmed to (red, green, blue)
883 * Truecolor:
884 * does not use RAMDAC (usually has 3 of them).
885 * var->{color}.offset contains start of bitfield
886 * var->{color}.length contains length of bitfield
887 * cmap is programmed to
888 * (red << red.offset) | (green << green.offset) |
889 * (blue << blue.offset) | (transp << transp.offset)
890 * RAMDAC does not exist
891 */
892 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF -(val)) >> 16)
893 switch (info->fix.visual) {
894 case FB_VISUAL_TRUECOLOR:
895 case FB_VISUAL_PSEUDOCOLOR:
896 red = CNVT_TOHW(red, info->var.red.length);
897 green = CNVT_TOHW(green, info->var.green.length);
898 blue = CNVT_TOHW(blue, info->var.blue.length);
899 transp = CNVT_TOHW(transp, info->var.transp.length);
900 break;
901 case FB_VISUAL_DIRECTCOLOR:
902 /* example here assumes 8 bit DAC. Might be different
903 * for your hardware */
904 red = CNVT_TOHW(red, 8);
905 green = CNVT_TOHW(green, 8);
906 blue = CNVT_TOHW(blue, 8);
907 /* hey, there is bug in transp handling... */
908 transp = CNVT_TOHW(transp, 8);
909 break;
910 }
911 #undef CNVT_TOHW
912 /* Truecolor has hardware independent palette */
913 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
914 u32 v;
915
916 if (regno >= 16)
917 return -EINVAL;
918
919 v = (red << info->var.red.offset) |
920 (green << info->var.green.offset) |
921 (blue << info->var.blue.offset) |
922 (transp << info->var.transp.offset);
923
924 switch (info->var.bits_per_pixel) {
925 case 8:
926 break;
927 case 16:
928 case 24:
929 case 32:
930 par->palette[regno] = v;
931 break;
932 }
933 return 0;
934 }
935 else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
936 set_color(par, regno, red, green, blue);
937
938 return 0;
939 }
940
941 /**
942 * pm2fb_pan_display - Pans the display.
943 * @var: frame buffer variable screen structure
944 * @info: frame buffer structure that represents a single frame buffer
945 *
946 * Pan (or wrap, depending on the `vmode' field) the display using the
947 * `xoffset' and `yoffset' fields of the `var' structure.
948 * If the values don't fit, return -EINVAL.
949 *
950 * Returns negative errno on error, or zero on success.
951 *
952 */
953 static int pm2fb_pan_display(struct fb_var_screeninfo *var,
954 struct fb_info *info)
955 {
956 struct pm2fb_par *p = info->par;
957 u32 base;
958 u32 depth = (var->bits_per_pixel + 7) & ~7;
959 u32 xres = (var->xres + 31) & ~31;
960
961 depth = (depth > 32) ? 32 : depth;
962 base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
963 WAIT_FIFO(p, 1);
964 pm2_WR(p, PM2R_SCREEN_BASE, base);
965 return 0;
966 }
967
968 /**
969 * pm2fb_blank - Blanks the display.
970 * @blank_mode: the blank mode we want.
971 * @info: frame buffer structure that represents a single frame buffer
972 *
973 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
974 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
975 * video mode which doesn't support it. Implements VESA suspend
976 * and powerdown modes on hardware that supports disabling hsync/vsync:
977 * blank_mode == 2: suspend vsync
978 * blank_mode == 3: suspend hsync
979 * blank_mode == 4: powerdown
980 *
981 * Returns negative errno on error, or zero on success.
982 *
983 */
984 static int pm2fb_blank(int blank_mode, struct fb_info *info)
985 {
986 struct pm2fb_par *par = info->par;
987 u32 video = par->video;
988
989 DPRINTK("blank_mode %d\n", blank_mode);
990
991 switch (blank_mode) {
992 case FB_BLANK_UNBLANK:
993 /* Screen: On */
994 video |= PM2F_VIDEO_ENABLE;
995 break;
996 case FB_BLANK_NORMAL:
997 /* Screen: Off */
998 video &= ~PM2F_VIDEO_ENABLE;
999 break;
1000 case FB_BLANK_VSYNC_SUSPEND:
1001 /* VSync: Off */
1002 video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW);
1003 break;
1004 case FB_BLANK_HSYNC_SUSPEND:
1005 /* HSync: Off */
1006 video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW);
1007 break;
1008 case FB_BLANK_POWERDOWN:
1009 /* HSync: Off, VSync: Off */
1010 video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK| PM2F_BLANK_LOW);
1011 break;
1012 }
1013 set_video(par, video);
1014 return 0;
1015 }
1016
1017 static int pm2fb_sync(struct fb_info *info)
1018 {
1019 struct pm2fb_par *par = info->par;
1020
1021 WAIT_FIFO(par, 1);
1022 pm2_WR(par, PM2R_SYNC, 0);
1023 mb();
1024 do {
1025 while (pm2_RD(par, PM2R_OUT_FIFO_WORDS) == 0)
1026 udelay(10);
1027 rmb();
1028 } while (pm2_RD(par, PM2R_OUT_FIFO) != PM2TAG(PM2R_SYNC));
1029
1030 return 0;
1031 }
1032
1033 static void pm2fb_fillrect (struct fb_info *info,
1034 const struct fb_fillrect *region)
1035 {
1036 struct pm2fb_par *par = info->par;
1037 struct fb_fillrect modded;
1038 int vxres, vyres;
1039 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1040 ((u32*)info->pseudo_palette)[region->color] : region->color;
1041
1042 if (info->state != FBINFO_STATE_RUNNING)
1043 return;
1044 if ((info->flags & FBINFO_HWACCEL_DISABLED) ||
1045 region->rop != ROP_COPY ) {
1046 cfb_fillrect(info, region);
1047 return;
1048 }
1049
1050 vxres = info->var.xres_virtual;
1051 vyres = info->var.yres_virtual;
1052
1053 memcpy(&modded, region, sizeof(struct fb_fillrect));
1054
1055 if (!modded.width || !modded.height ||
1056 modded.dx >= vxres || modded.dy >= vyres)
1057 return;
1058
1059 if (modded.dx + modded.width > vxres)
1060 modded.width = vxres - modded.dx;
1061 if (modded.dy + modded.height > vyres)
1062 modded.height = vyres - modded.dy;
1063
1064 if (info->var.bits_per_pixel == 8)
1065 color |= color << 8;
1066 if (info->var.bits_per_pixel <= 16)
1067 color |= color << 16;
1068
1069 WAIT_FIFO(par, 3);
1070 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE);
1071 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx);
1072 pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width);
1073 if (info->var.bits_per_pixel != 24) {
1074 WAIT_FIFO(par, 2);
1075 pm2_WR(par, PM2R_FB_BLOCK_COLOR, color);
1076 wmb();
1077 pm2_WR(par, PM2R_RENDER,
1078 PM2F_RENDER_RECTANGLE | PM2F_RENDER_FASTFILL);
1079 } else {
1080 cfb_fillrect(info, region);
1081 }
1082 }
1083
1084 static void pm2fb_copyarea(struct fb_info *info,
1085 const struct fb_copyarea *area)
1086 {
1087 struct pm2fb_par *par = info->par;
1088 struct fb_copyarea modded;
1089 u32 vxres, vyres;
1090
1091 if (info->state != FBINFO_STATE_RUNNING)
1092 return;
1093 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1094 cfb_copyarea(info, area);
1095 return;
1096 }
1097
1098 memcpy(&modded, area, sizeof(struct fb_copyarea));
1099
1100 vxres = info->var.xres_virtual;
1101 vyres = info->var.yres_virtual;
1102
1103 if (!modded.width || !modded.height ||
1104 modded.sx >= vxres || modded.sy >= vyres ||
1105 modded.dx >= vxres || modded.dy >= vyres)
1106 return;
1107
1108 if (modded.sx + modded.width > vxres)
1109 modded.width = vxres - modded.sx;
1110 if (modded.dx + modded.width > vxres)
1111 modded.width = vxres - modded.dx;
1112 if (modded.sy + modded.height > vyres)
1113 modded.height = vyres - modded.sy;
1114 if (modded.dy + modded.height > vyres)
1115 modded.height = vyres - modded.dy;
1116
1117 WAIT_FIFO(par, 5);
1118 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE |
1119 PM2F_CONFIG_FB_READ_SOURCE_ENABLE);
1120 pm2_WR(par, PM2R_FB_SOURCE_DELTA,
1121 ((modded.sy-modded.dy) & 0xfff) << 16 |
1122 ((modded.sx-modded.dx) & 0xfff));
1123 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx);
1124 pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width);
1125 wmb();
1126 pm2_WR(par, PM2R_RENDER, PM2F_RENDER_RECTANGLE |
1127 (modded.dx<modded.sx ? PM2F_INCREASE_X : 0) |
1128 (modded.dy<modded.sy ? PM2F_INCREASE_Y : 0));
1129 }
1130
1131 static void pm2fb_imageblit(struct fb_info *info, const struct fb_image *image)
1132 {
1133 struct pm2fb_par *par = info->par;
1134 u32 height = image->height;
1135 u32 fgx, bgx;
1136 const u32 *src = (const u32*)image->data;
1137 u32 xres = (info->var.xres + 31) & ~31;
1138
1139 if (info->state != FBINFO_STATE_RUNNING)
1140 return;
1141 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) {
1142 cfb_imageblit(info, image);
1143 return;
1144 }
1145 switch (info->fix.visual) {
1146 case FB_VISUAL_PSEUDOCOLOR:
1147 fgx = image->fg_color;
1148 bgx = image->bg_color;
1149 break;
1150 case FB_VISUAL_TRUECOLOR:
1151 default:
1152 fgx = par->palette[image->fg_color];
1153 bgx = par->palette[image->bg_color];
1154 break;
1155 }
1156 if (info->var.bits_per_pixel == 8) {
1157 fgx |= fgx << 8;
1158 bgx |= bgx << 8;
1159 }
1160 if (info->var.bits_per_pixel <= 16) {
1161 fgx |= fgx << 16;
1162 bgx |= bgx << 16;
1163 }
1164
1165 WAIT_FIFO(par, 13);
1166 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
1167 pm2_WR(par, PM2R_SCISSOR_MIN_XY,
1168 ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
1169 pm2_WR(par, PM2R_SCISSOR_MAX_XY,
1170 (((image->dy + image->height) & 0x0fff) << 16) |
1171 ((image->dx + image->width) & 0x0fff));
1172 pm2_WR(par, PM2R_SCISSOR_MODE, 1);
1173 /* GXcopy & UNIT_ENABLE */
1174 pm2_WR(par, PM2R_LOGICAL_OP_MODE, (0x3 << 1) | 1);
1175 pm2_WR(par, PM2R_RECTANGLE_ORIGIN,
1176 ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
1177 pm2_WR(par, PM2R_RECTANGLE_SIZE,
1178 ((image->height & 0x0fff) << 16) |
1179 ((image->width) & 0x0fff));
1180 if (info->var.bits_per_pixel == 24) {
1181 pm2_WR(par, PM2R_COLOR_DDA_MODE, 1);
1182 /* clear area */
1183 pm2_WR(par, PM2R_CONSTANT_COLOR, bgx);
1184 pm2_WR(par, PM2R_RENDER,
1185 PM2F_RENDER_RECTANGLE |
1186 PM2F_INCREASE_X | PM2F_INCREASE_Y);
1187 /* BitMapPackEachScanline & invert bits and byte order*/
1188 /* force background */
1189 pm2_WR(par, PM2R_RASTERIZER_MODE, (1 << 9) | 1 | (3 << 7));
1190 pm2_WR(par, PM2R_CONSTANT_COLOR, fgx);
1191 pm2_WR(par, PM2R_RENDER,
1192 PM2F_RENDER_RECTANGLE |
1193 PM2F_INCREASE_X | PM2F_INCREASE_Y |
1194 PM2F_RENDER_SYNC_ON_BIT_MASK);
1195 } else {
1196 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1197 /* clear area */
1198 pm2_WR(par, PM2R_FB_BLOCK_COLOR, bgx);
1199 pm2_WR(par, PM2R_RENDER,
1200 PM2F_RENDER_RECTANGLE |
1201 PM2F_RENDER_FASTFILL |
1202 PM2F_INCREASE_X | PM2F_INCREASE_Y);
1203 /* invert bits and byte order*/
1204 pm2_WR(par, PM2R_RASTERIZER_MODE, 1 | (3 << 7));
1205 pm2_WR(par, PM2R_FB_BLOCK_COLOR, fgx);
1206 pm2_WR(par, PM2R_RENDER,
1207 PM2F_RENDER_RECTANGLE |
1208 PM2F_INCREASE_X | PM2F_INCREASE_Y |
1209 PM2F_RENDER_FASTFILL |
1210 PM2F_RENDER_SYNC_ON_BIT_MASK);
1211 }
1212
1213 while (height--) {
1214 int width = ((image->width + 7) >> 3)
1215 + info->pixmap.scan_align - 1;
1216 width >>= 2;
1217 WAIT_FIFO(par, width);
1218 while (width--) {
1219 pm2_WR(par, PM2R_BIT_MASK_PATTERN, *src);
1220 src++;
1221 }
1222 }
1223 WAIT_FIFO(par, 3);
1224 pm2_WR(par, PM2R_RASTERIZER_MODE, 0);
1225 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1226 pm2_WR(par, PM2R_SCISSOR_MODE, 0);
1227 }
1228
1229 /* ------------ Hardware Independent Functions ------------ */
1230
1231 /*
1232 * Frame buffer operations
1233 */
1234
1235 static struct fb_ops pm2fb_ops = {
1236 .owner = THIS_MODULE,
1237 .fb_check_var = pm2fb_check_var,
1238 .fb_set_par = pm2fb_set_par,
1239 .fb_setcolreg = pm2fb_setcolreg,
1240 .fb_blank = pm2fb_blank,
1241 .fb_pan_display = pm2fb_pan_display,
1242 .fb_fillrect = pm2fb_fillrect,
1243 .fb_copyarea = pm2fb_copyarea,
1244 .fb_imageblit = pm2fb_imageblit,
1245 .fb_sync = pm2fb_sync,
1246 };
1247
1248 /*
1249 * PCI stuff
1250 */
1251
1252
1253 /**
1254 * Device initialisation
1255 *
1256 * Initialise and allocate resource for PCI device.
1257 *
1258 * @param pdev PCI device.
1259 * @param id PCI device ID.
1260 */
1261 static int __devinit pm2fb_probe(struct pci_dev *pdev,
1262 const struct pci_device_id *id)
1263 {
1264 struct pm2fb_par *default_par;
1265 struct fb_info *info;
1266 int err, err_retval = -ENXIO;
1267
1268 err = pci_enable_device(pdev);
1269 if (err) {
1270 printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
1271 return err;
1272 }
1273
1274 info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev);
1275 if (!info)
1276 return -ENOMEM;
1277 default_par = info->par;
1278
1279 switch (pdev->device) {
1280 case PCI_DEVICE_ID_TI_TVP4020:
1281 strcpy(pm2fb_fix.id, "TVP4020");
1282 default_par->type = PM2_TYPE_PERMEDIA2;
1283 break;
1284 case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
1285 strcpy(pm2fb_fix.id, "Permedia2");
1286 default_par->type = PM2_TYPE_PERMEDIA2;
1287 break;
1288 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
1289 strcpy(pm2fb_fix.id, "Permedia2v");
1290 default_par->type = PM2_TYPE_PERMEDIA2V;
1291 break;
1292 }
1293
1294 pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
1295 pm2fb_fix.mmio_len = PM2_REGS_SIZE;
1296
1297 #if defined(__BIG_ENDIAN)
1298 /*
1299 * PM2 has a 64k register file, mapped twice in 128k. Lower
1300 * map is little-endian, upper map is big-endian.
1301 */
1302 pm2fb_fix.mmio_start += PM2_REGS_SIZE;
1303 DPRINTK("Adjusting register base for big-endian.\n");
1304 #endif
1305 DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
1306
1307 /* Registers - request region and map it. */
1308 if (!request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
1309 "pm2fb regbase")) {
1310 printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
1311 goto err_exit_neither;
1312 }
1313 default_par->v_regs =
1314 ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1315 if (!default_par->v_regs) {
1316 printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
1317 pm2fb_fix.id);
1318 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1319 goto err_exit_neither;
1320 }
1321
1322 /* Stash away memory register info for use when we reset the board */
1323 default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
1324 default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
1325 default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
1326 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1327 default_par->mem_control, default_par->boot_address,
1328 default_par->mem_config);
1329
1330 if (default_par->mem_control == 0 &&
1331 default_par->boot_address == 0x31 &&
1332 default_par->mem_config == 0x259fffff) {
1333 default_par->memclock = CVPPC_MEMCLOCK;
1334 default_par->mem_control = 0;
1335 default_par->boot_address = 0x20;
1336 default_par->mem_config = 0xe6002021;
1337 if (pdev->subsystem_vendor == 0x1048 &&
1338 pdev->subsystem_device == 0x0a31) {
1339 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1340 pdev->subsystem_vendor, pdev->subsystem_device);
1341 DPRINTK("We have not been initialized by VGA BIOS "
1342 "and are running on an Elsa Winner 2000 Office\n");
1343 DPRINTK("Initializing card timings manually...\n");
1344 default_par->memclock = 100000;
1345 }
1346 if (pdev->subsystem_vendor == 0x3d3d &&
1347 pdev->subsystem_device == 0x0100) {
1348 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1349 pdev->subsystem_vendor, pdev->subsystem_device);
1350 DPRINTK("We have not been initialized by VGA BIOS "
1351 "and are running on an 3dlabs reference board\n");
1352 DPRINTK("Initializing card timings manually...\n");
1353 default_par->memclock = 74894;
1354 }
1355 }
1356
1357 /* Now work out how big lfb is going to be. */
1358 switch(default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
1359 case PM2F_MEM_BANKS_1:
1360 pm2fb_fix.smem_len = 0x200000;
1361 break;
1362 case PM2F_MEM_BANKS_2:
1363 pm2fb_fix.smem_len = 0x400000;
1364 break;
1365 case PM2F_MEM_BANKS_3:
1366 pm2fb_fix.smem_len = 0x600000;
1367 break;
1368 case PM2F_MEM_BANKS_4:
1369 pm2fb_fix.smem_len = 0x800000;
1370 break;
1371 }
1372 pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
1373
1374 /* Linear frame buffer - request region and map it. */
1375 if (!request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
1376 "pm2fb smem")) {
1377 printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
1378 goto err_exit_mmio;
1379 }
1380 info->screen_base =
1381 ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1382 if (!info->screen_base) {
1383 printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
1384 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1385 goto err_exit_mmio;
1386 }
1387
1388 #ifdef CONFIG_MTRR
1389 default_par->mtrr_handle = -1;
1390 if (!nomtrr)
1391 default_par->mtrr_handle =
1392 mtrr_add(pm2fb_fix.smem_start,
1393 pm2fb_fix.smem_len,
1394 MTRR_TYPE_WRCOMB, 1);
1395 #endif
1396
1397 info->fbops = &pm2fb_ops;
1398 info->fix = pm2fb_fix;
1399 info->pseudo_palette = default_par->palette;
1400 info->flags = FBINFO_DEFAULT |
1401 FBINFO_HWACCEL_YPAN |
1402 FBINFO_HWACCEL_COPYAREA |
1403 FBINFO_HWACCEL_IMAGEBLIT |
1404 FBINFO_HWACCEL_FILLRECT;
1405
1406 info->pixmap.addr = kmalloc(PM2_PIXMAP_SIZE, GFP_KERNEL);
1407 if (!info->pixmap.addr) {
1408 err_retval = -ENOMEM;
1409 goto err_exit_pixmap;
1410 }
1411 info->pixmap.size = PM2_PIXMAP_SIZE;
1412 info->pixmap.buf_align = 4;
1413 info->pixmap.scan_align = 4;
1414 info->pixmap.access_align = 32;
1415 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1416
1417 if (noaccel) {
1418 printk(KERN_DEBUG "disabling acceleration\n");
1419 info->flags |= FBINFO_HWACCEL_DISABLED;
1420 info->pixmap.scan_align = 1;
1421 }
1422
1423 if (!mode)
1424 mode = "640x480@60";
1425
1426 err = fb_find_mode(&info->var, info, mode, NULL, 0, NULL, 8);
1427 if (!err || err == 4)
1428 info->var = pm2fb_var;
1429
1430 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
1431 goto err_exit_both;
1432
1433 if (register_framebuffer(info) < 0)
1434 goto err_exit_all;
1435
1436 printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n",
1437 info->node, info->fix.id, pm2fb_fix.smem_len / 1024);
1438
1439 /*
1440 * Our driver data
1441 */
1442 pci_set_drvdata(pdev, info);
1443
1444 return 0;
1445
1446 err_exit_all:
1447 fb_dealloc_cmap(&info->cmap);
1448 err_exit_both:
1449 kfree(info->pixmap.addr);
1450 err_exit_pixmap:
1451 iounmap(info->screen_base);
1452 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1453 err_exit_mmio:
1454 iounmap(default_par->v_regs);
1455 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1456 err_exit_neither:
1457 framebuffer_release(info);
1458 return err_retval;
1459 }
1460
1461 /**
1462 * Device removal.
1463 *
1464 * Release all device resources.
1465 *
1466 * @param pdev PCI device to clean up.
1467 */
1468 static void __devexit pm2fb_remove(struct pci_dev *pdev)
1469 {
1470 struct fb_info* info = pci_get_drvdata(pdev);
1471 struct fb_fix_screeninfo* fix = &info->fix;
1472 struct pm2fb_par *par = info->par;
1473
1474 unregister_framebuffer(info);
1475
1476 #ifdef CONFIG_MTRR
1477 if (par->mtrr_handle >= 0)
1478 mtrr_del(par->mtrr_handle, info->fix.smem_start,
1479 info->fix.smem_len);
1480 #endif /* CONFIG_MTRR */
1481 iounmap(info->screen_base);
1482 release_mem_region(fix->smem_start, fix->smem_len);
1483 iounmap(par->v_regs);
1484 release_mem_region(fix->mmio_start, fix->mmio_len);
1485
1486 pci_set_drvdata(pdev, NULL);
1487 if (info->pixmap.addr)
1488 kfree(info->pixmap.addr);
1489 kfree(info);
1490 }
1491
1492 static struct pci_device_id pm2fb_id_table[] = {
1493 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
1494 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1495 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
1496 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1497 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1498 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1499 { 0, }
1500 };
1501
1502 static struct pci_driver pm2fb_driver = {
1503 .name = "pm2fb",
1504 .id_table = pm2fb_id_table,
1505 .probe = pm2fb_probe,
1506 .remove = __devexit_p(pm2fb_remove),
1507 };
1508
1509 MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
1510
1511
1512 #ifndef MODULE
1513 /**
1514 * Parse user speficied options.
1515 *
1516 * This is, comma-separated options following `video=pm2fb:'.
1517 */
1518 static int __init pm2fb_setup(char *options)
1519 {
1520 char* this_opt;
1521
1522 if (!options || !*options)
1523 return 0;
1524
1525 while ((this_opt = strsep(&options, ",")) != NULL) {
1526 if (!*this_opt)
1527 continue;
1528 if (!strcmp(this_opt, "lowhsync")) {
1529 lowhsync = 1;
1530 } else if (!strcmp(this_opt, "lowvsync")) {
1531 lowvsync = 1;
1532 #ifdef CONFIG_MTRR
1533 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1534 nomtrr = 1;
1535 #endif
1536 } else if (!strncmp(this_opt, "noaccel", 7)) {
1537 noaccel = 1;
1538 } else {
1539 mode = this_opt;
1540 }
1541 }
1542 return 0;
1543 }
1544 #endif
1545
1546
1547 static int __init pm2fb_init(void)
1548 {
1549 #ifndef MODULE
1550 char *option = NULL;
1551
1552 if (fb_get_options("pm2fb", &option))
1553 return -ENODEV;
1554 pm2fb_setup(option);
1555 #endif
1556
1557 return pci_register_driver(&pm2fb_driver);
1558 }
1559
1560 module_init(pm2fb_init);
1561
1562 #ifdef MODULE
1563 /*
1564 * Cleanup
1565 */
1566
1567 static void __exit pm2fb_exit(void)
1568 {
1569 pci_unregister_driver(&pm2fb_driver);
1570 }
1571 #endif
1572
1573 #ifdef MODULE
1574 module_exit(pm2fb_exit);
1575
1576 module_param(mode, charp, 0);
1577 MODULE_PARM_DESC(mode, "Preferred video mode e.g. '648x480-8@60'");
1578 module_param(lowhsync, bool, 0);
1579 MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
1580 module_param(lowvsync, bool, 0);
1581 MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
1582 module_param(noaccel, bool, 0);
1583 MODULE_PARM_DESC(noaccel, "Disable acceleration");
1584 #ifdef CONFIG_MTRR
1585 module_param(nomtrr, bool, 0);
1586 MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
1587 #endif
1588
1589 MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1590 MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1591 MODULE_LICENSE("GPL");
1592 #endif
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