?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[ARM] 3302/1: make pci=firmware the default for ixp2000
[linux-2.6/openmoko-kernel/knife-kernel.git] / sound / oss / i810_audio.c
blobabc242abd5b111ba5dea82c2d51889a26a9a45b6
1 /*
2 * Intel i810 and friends ICH driver for Linux
3 * Alan Cox <alan@redhat.com>
4 *
5 * Built from:
6 * Low level code: Zach Brown (original nonworking i810 OSS driver)
7 * Jaroslav Kysela <perex@suse.cz> (working ALSA driver)
8 *
9 * Framework: Thomas Sailer <sailer@ife.ee.ethz.ch>
10 * Extended by: Zach Brown <zab@redhat.com>
11 * and others..
12 *
13 * Hardware Provided By:
14 * Analog Devices (A major AC97 codec maker)
15 * Intel Corp (you've probably heard of them already)
16 *
17 * AC97 clues and assistance provided by
18 * Analog Devices
19 * Zach 'Fufu' Brown
20 * Jeff Garzik
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License as published by
24 * the Free Software Foundation; either version 2 of the License, or
25 * (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
31 *
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
35 *
36 *
37 * Intel 810 theory of operation
38 *
39 * The chipset provides three DMA channels that talk to an AC97
40 * CODEC (AC97 is a digital/analog mixer standard). At its simplest
41 * you get 48Khz audio with basic volume and mixer controls. At the
42 * best you get rate adaption in the codec. We set the card up so
43 * that we never take completion interrupts but instead keep the card
44 * chasing its tail around a ring buffer. This is needed for mmap
45 * mode audio and happens to work rather well for non-mmap modes too.
46 *
47 * The board has one output channel for PCM audio (supported) and
48 * a stereo line in and mono microphone input. Again these are normally
49 * locked to 48Khz only. Right now recording is not finished.
50 *
51 * There is no midi support, no synth support. Use timidity. To get
52 * esd working you need to use esd -r 48000 as it won't probe 48KHz
53 * by default. mpg123 can't handle 48Khz only audio so use xmms.
54 *
55 * Fix The Sound On Dell
56 *
57 * Not everyone uses 48KHz. We know of no way to detect this reliably
58 * and certainly not to get the right data. If your i810 audio sounds
59 * stupid you may need to investigate other speeds. According to Analog
60 * they tend to use a 14.318MHz clock which gives you a base rate of
61 * 41194Hz.
62 *
63 * This is available via the 'ftsodell=1' option.
64 *
65 * If you need to force a specific rate set the clocking= option
66 *
67 * This driver is cursed. (Ben LaHaise)
68 *
69 * ICH 3 caveats
70 * Intel errata #7 for ICH3 IO. We need to disable SMI stuff
71 * when codec probing. [Not Yet Done]
72 *
73 * ICH 4 caveats
74 *
75 * The ICH4 has the feature, that the codec ID doesn't have to be
76 * congruent with the IO connection.
77 *
78 * Therefore, from driver version 0.23 on, there is a "codec ID" <->
79 * "IO register base offset" mapping (card->ac97_id_map) field.
80 *
81 * Juergen "George" Sawinski (jsaw)
82 */
83
84 #include <linux/module.h>
85 #include <linux/string.h>
86 #include <linux/ctype.h>
87 #include <linux/ioport.h>
88 #include <linux/sched.h>
89 #include <linux/delay.h>
90 #include <linux/sound.h>
91 #include <linux/slab.h>
92 #include <linux/soundcard.h>
93 #include <linux/pci.h>
94 #include <linux/interrupt.h>
95 #include <asm/io.h>
96 #include <asm/dma.h>
97 #include <linux/init.h>
98 #include <linux/poll.h>
99 #include <linux/spinlock.h>
100 #include <linux/smp_lock.h>
101 #include <linux/ac97_codec.h>
102 #include <linux/bitops.h>
103 #include <asm/uaccess.h>
104
105 #define DRIVER_VERSION "1.01"
106
107 #define MODULOP2(a, b) ((a) & ((b) - 1))
108 #define MASKP2(a, b) ((a) & ~((b) - 1))
109
110 static int ftsodell;
111 static int strict_clocking;
112 static unsigned int clocking;
113 static int spdif_locked;
114 static int ac97_quirk = AC97_TUNE_DEFAULT;
115
116 //#define DEBUG
117 //#define DEBUG2
118 //#define DEBUG_INTERRUPTS
119 //#define DEBUG_MMAP
120 //#define DEBUG_MMIO
121
122 #define ADC_RUNNING 1
123 #define DAC_RUNNING 2
124
125 #define I810_FMT_16BIT 1
126 #define I810_FMT_STEREO 2
127 #define I810_FMT_MASK 3
128
129 #define SPDIF_ON 0x0004
130 #define SURR_ON 0x0010
131 #define CENTER_LFE_ON 0x0020
132 #define VOL_MUTED 0x8000
133
134 /* the 810's array of pointers to data buffers */
135
136 struct sg_item {
137 #define BUSADDR_MASK 0xFFFFFFFE
138 u32 busaddr;
139 #define CON_IOC 0x80000000 /* interrupt on completion */
140 #define CON_BUFPAD 0x40000000 /* pad underrun with last sample, else 0 */
141 #define CON_BUFLEN_MASK 0x0000ffff /* buffer length in samples */
142 u32 control;
143 };
144
145 /* an instance of the i810 channel */
146 #define SG_LEN 32
147 struct i810_channel
148 {
149 /* these sg guys should probably be allocated
150 separately as nocache. Must be 8 byte aligned */
151 struct sg_item sg[SG_LEN]; /* 32*8 */
152 u32 offset; /* 4 */
153 u32 port; /* 4 */
154 u32 used;
155 u32 num;
156 };
157
158 /*
159 * we have 3 separate dma engines. pcm in, pcm out, and mic.
160 * each dma engine has controlling registers. These goofy
161 * names are from the datasheet, but make it easy to write
162 * code while leafing through it.
163 *
164 * ICH4 has 6 dma engines, pcm in, pcm out, mic, pcm in 2,
165 * mic in 2, s/pdif. Of special interest is the fact that
166 * the upper 3 DMA engines on the ICH4 *must* be accessed
167 * via mmio access instead of pio access.
168 */
169
170 #define ENUM_ENGINE(PRE,DIG) \
171 enum { \
172 PRE##_BASE = 0x##DIG##0, /* Base Address */ \
173 PRE##_BDBAR = 0x##DIG##0, /* Buffer Descriptor list Base Address */ \
174 PRE##_CIV = 0x##DIG##4, /* Current Index Value */ \
175 PRE##_LVI = 0x##DIG##5, /* Last Valid Index */ \
176 PRE##_SR = 0x##DIG##6, /* Status Register */ \
177 PRE##_PICB = 0x##DIG##8, /* Position In Current Buffer */ \
178 PRE##_PIV = 0x##DIG##a, /* Prefetched Index Value */ \
179 PRE##_CR = 0x##DIG##b /* Control Register */ \
180 }
181
182 ENUM_ENGINE(OFF,0); /* Offsets */
183 ENUM_ENGINE(PI,0); /* PCM In */
184 ENUM_ENGINE(PO,1); /* PCM Out */
185 ENUM_ENGINE(MC,2); /* Mic In */
186
187 enum {
188 GLOB_CNT = 0x2c, /* Global Control */
189 GLOB_STA = 0x30, /* Global Status */
190 CAS = 0x34 /* Codec Write Semaphore Register */
191 };
192
193 ENUM_ENGINE(MC2,4); /* Mic In 2 */
194 ENUM_ENGINE(PI2,5); /* PCM In 2 */
195 ENUM_ENGINE(SP,6); /* S/PDIF */
196
197 enum {
198 SDM = 0x80 /* SDATA_IN Map Register */
199 };
200
201 /* interrupts for a dma engine */
202 #define DMA_INT_FIFO (1<<4) /* fifo under/over flow */
203 #define DMA_INT_COMPLETE (1<<3) /* buffer read/write complete and ioc set */
204 #define DMA_INT_LVI (1<<2) /* last valid done */
205 #define DMA_INT_CELV (1<<1) /* last valid is current */
206 #define DMA_INT_DCH (1) /* DMA Controller Halted (happens on LVI interrupts) */
207 #define DMA_INT_MASK (DMA_INT_FIFO|DMA_INT_COMPLETE|DMA_INT_LVI)
208
209 /* interrupts for the whole chip */
210 #define INT_SEC (1<<11)
211 #define INT_PRI (1<<10)
212 #define INT_MC (1<<7)
213 #define INT_PO (1<<6)
214 #define INT_PI (1<<5)
215 #define INT_MO (1<<2)
216 #define INT_NI (1<<1)
217 #define INT_GPI (1<<0)
218 #define INT_MASK (INT_SEC|INT_PRI|INT_MC|INT_PO|INT_PI|INT_MO|INT_NI|INT_GPI)
219
220 /* magic numbers to protect our data structures */
221 #define I810_CARD_MAGIC 0x5072696E /* "Prin" */
222 #define I810_STATE_MAGIC 0x63657373 /* "cess" */
223 #define I810_DMA_MASK 0xffffffff /* DMA buffer mask for pci_alloc_consist */
224 #define NR_HW_CH 3
225
226 /* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */
227 #define NR_AC97 4
228
229 /* Please note that an 8bit mono stream is not valid on this card, you must have a 16bit */
230 /* stream at a minimum for this card to be happy */
231 static const unsigned sample_size[] = { 1, 2, 2, 4 };
232 /* Samples are 16bit values, so we are shifting to a word, not to a byte, hence shift */
233 /* values are one less than might be expected */
234 static const unsigned sample_shift[] = { -1, 0, 0, 1 };
235
236 enum {
237 ICH82801AA = 0,
238 ICH82901AB,
239 INTEL440MX,
240 INTELICH2,
241 INTELICH3,
242 INTELICH4,
243 INTELICH5,
244 SI7012,
245 NVIDIA_NFORCE,
246 AMD768,
247 AMD8111
248 };
249
250 static char * card_names[] = {
251 "Intel ICH 82801AA",
252 "Intel ICH 82901AB",
253 "Intel 440MX",
254 "Intel ICH2",
255 "Intel ICH3",
256 "Intel ICH4",
257 "Intel ICH5",
258 "SiS 7012",
259 "NVIDIA nForce Audio",
260 "AMD 768",
261 "AMD-8111 IOHub"
262 };
263
264 /* These are capabilities (and bugs) the chipsets _can_ have */
265 static struct {
266 int16_t nr_ac97;
267 #define CAP_MMIO 0x0001
268 #define CAP_20BIT_AUDIO_SUPPORT 0x0002
269 u_int16_t flags;
270 } card_cap[] = {
271 { 1, 0x0000 }, /* ICH82801AA */
272 { 1, 0x0000 }, /* ICH82901AB */
273 { 1, 0x0000 }, /* INTEL440MX */
274 { 1, 0x0000 }, /* INTELICH2 */
275 { 2, 0x0000 }, /* INTELICH3 */
276 { 3, 0x0003 }, /* INTELICH4 */
277 { 3, 0x0003 }, /* INTELICH5 */
278 /*@FIXME to be verified*/ { 2, 0x0000 }, /* SI7012 */
279 /*@FIXME to be verified*/ { 2, 0x0000 }, /* NVIDIA_NFORCE */
280 /*@FIXME to be verified*/ { 2, 0x0000 }, /* AMD768 */
281 /*@FIXME to be verified*/ { 3, 0x0001 }, /* AMD8111 */
282 };
283
284 static struct pci_device_id i810_pci_tbl [] = {
285 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_5,
286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82801AA},
287 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_5,
288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ICH82901AB},
289 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_440MX,
290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTEL440MX},
291 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_4,
292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH2},
293 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_5,
294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH3},
295 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_5,
296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
297 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_5,
298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH5},
299 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_7012,
300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SI7012},
301 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO,
302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
303 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO,
304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
305 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO,
306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
307 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7445,
308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, AMD768},
309 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_AUDIO,
310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, AMD8111},
311 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_5,
312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
313 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_18,
314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, INTELICH4},
315 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_AUDIO,
316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NVIDIA_NFORCE},
317 {0,}
318 };
319
320 MODULE_DEVICE_TABLE (pci, i810_pci_tbl);
321
322 #ifdef CONFIG_PM
323 #define PM_SUSPENDED(card) (card->pm_suspended)
324 #else
325 #define PM_SUSPENDED(card) (0)
326 #endif
327
328 /* "software" or virtual channel, an instance of opened /dev/dsp */
329 struct i810_state {
330 unsigned int magic;
331 struct i810_card *card; /* Card info */
332
333 /* single open lock mechanism, only used for recording */
334 struct semaphore open_sem;
335 wait_queue_head_t open_wait;
336
337 /* file mode */
338 mode_t open_mode;
339
340 /* virtual channel number */
341 int virt;
342
343 #ifdef CONFIG_PM
344 unsigned int pm_saved_dac_rate,pm_saved_adc_rate;
345 #endif
346 struct dmabuf {
347 /* wave sample stuff */
348 unsigned int rate;
349 unsigned char fmt, enable, trigger;
350
351 /* hardware channel */
352 struct i810_channel *read_channel;
353 struct i810_channel *write_channel;
354
355 /* OSS buffer management stuff */
356 void *rawbuf;
357 dma_addr_t dma_handle;
358 unsigned buforder;
359 unsigned numfrag;
360 unsigned fragshift;
361
362 /* our buffer acts like a circular ring */
363 unsigned hwptr; /* where dma last started, updated by update_ptr */
364 unsigned swptr; /* where driver last clear/filled, updated by read/write */
365 int count; /* bytes to be consumed or been generated by dma machine */
366 unsigned total_bytes; /* total bytes dmaed by hardware */
367
368 unsigned error; /* number of over/underruns */
369 wait_queue_head_t wait; /* put process on wait queue when no more space in buffer */
370
371 /* redundant, but makes calculations easier */
372 /* what the hardware uses */
373 unsigned dmasize;
374 unsigned fragsize;
375 unsigned fragsamples;
376
377 /* what we tell the user to expect */
378 unsigned userfrags;
379 unsigned userfragsize;
380
381 /* OSS stuff */
382 unsigned mapped:1;
383 unsigned ready:1;
384 unsigned update_flag;
385 unsigned ossfragsize;
386 unsigned ossmaxfrags;
387 unsigned subdivision;
388 } dmabuf;
389 };
390
391
392 struct i810_card {
393 unsigned int magic;
394
395 /* We keep i810 cards in a linked list */
396 struct i810_card *next;
397
398 /* The i810 has a certain amount of cross channel interaction
399 so we use a single per card lock */
400 spinlock_t lock;
401
402 /* Control AC97 access serialization */
403 spinlock_t ac97_lock;
404
405 /* PCI device stuff */
406 struct pci_dev * pci_dev;
407 u16 pci_id;
408 u16 pci_id_internal; /* used to access card_cap[] */
409 #ifdef CONFIG_PM
410 u16 pm_suspended;
411 int pm_saved_mixer_settings[SOUND_MIXER_NRDEVICES][NR_AC97];
412 #endif
413 /* soundcore stuff */
414 int dev_audio;
415
416 /* structures for abstraction of hardware facilities, codecs, banks and channels*/
417 u16 ac97_id_map[NR_AC97];
418 struct ac97_codec *ac97_codec[NR_AC97];
419 struct i810_state *states[NR_HW_CH];
420 struct i810_channel *channel; /* 1:1 to states[] but diff. lifetime */
421 dma_addr_t chandma;
422
423 u16 ac97_features;
424 u16 ac97_status;
425 u16 channels;
426
427 /* hardware resources */
428 unsigned long ac97base;
429 unsigned long iobase;
430 u32 irq;
431
432 unsigned long ac97base_mmio_phys;
433 unsigned long iobase_mmio_phys;
434 u_int8_t __iomem *ac97base_mmio;
435 u_int8_t __iomem *iobase_mmio;
436
437 int use_mmio;
438
439 /* Function support */
440 struct i810_channel *(*alloc_pcm_channel)(struct i810_card *);
441 struct i810_channel *(*alloc_rec_pcm_channel)(struct i810_card *);
442 struct i810_channel *(*alloc_rec_mic_channel)(struct i810_card *);
443 void (*free_pcm_channel)(struct i810_card *, int chan);
444
445 /* We have a *very* long init time possibly, so use this to block */
446 /* attempts to open our devices before we are ready (stops oops'es) */
447 int initializing;
448 };
449
450 /* extract register offset from codec struct */
451 #define IO_REG_OFF(codec) (((struct i810_card *) codec->private_data)->ac97_id_map[codec->id])
452
453 #define I810_IOREAD(size, type, card, off) \
454 ({ \
455 type val; \
456 if (card->use_mmio) \
457 val=read##size(card->iobase_mmio+off); \
458 else \
459 val=in##size(card->iobase+off); \
460 val; \
461 })
462
463 #define I810_IOREADL(card, off) I810_IOREAD(l, u32, card, off)
464 #define I810_IOREADW(card, off) I810_IOREAD(w, u16, card, off)
465 #define I810_IOREADB(card, off) I810_IOREAD(b, u8, card, off)
466
467 #define I810_IOWRITE(size, val, card, off) \
468 ({ \
469 if (card->use_mmio) \
470 write##size(val, card->iobase_mmio+off); \
471 else \
472 out##size(val, card->iobase+off); \
473 })
474
475 #define I810_IOWRITEL(val, card, off) I810_IOWRITE(l, val, card, off)
476 #define I810_IOWRITEW(val, card, off) I810_IOWRITE(w, val, card, off)
477 #define I810_IOWRITEB(val, card, off) I810_IOWRITE(b, val, card, off)
478
479 #define GET_CIV(card, port) MODULOP2(I810_IOREADB((card), (port) + OFF_CIV), SG_LEN)
480 #define GET_LVI(card, port) MODULOP2(I810_IOREADB((card), (port) + OFF_LVI), SG_LEN)
481
482 /* set LVI from CIV */
483 #define CIV_TO_LVI(card, port, off) \
484 I810_IOWRITEB(MODULOP2(GET_CIV((card), (port)) + (off), SG_LEN), (card), (port) + OFF_LVI)
485
486 static struct ac97_quirk ac97_quirks[] __devinitdata = {
487 {
488 .vendor = 0x0e11,
489 .device = 0x00b8,
490 .name = "Compaq Evo D510C",
491 .type = AC97_TUNE_HP_ONLY
492 },
493 {
494 .vendor = 0x1028,
495 .device = 0x00d8,
496 .name = "Dell Precision 530", /* AD1885 */
497 .type = AC97_TUNE_HP_ONLY
498 },
499 {
500 .vendor = 0x1028,
501 .device = 0x0126,
502 .name = "Dell Optiplex GX260", /* AD1981A */
503 .type = AC97_TUNE_HP_ONLY
504 },
505 {
506 .vendor = 0x1028,
507 .device = 0x012d,
508 .name = "Dell Precision 450", /* AD1981B*/
509 .type = AC97_TUNE_HP_ONLY
510 },
511 { /* FIXME: which codec? */
512 .vendor = 0x103c,
513 .device = 0x00c3,
514 .name = "Hewlett-Packard onboard",
515 .type = AC97_TUNE_HP_ONLY
516 },
517 {
518 .vendor = 0x103c,
519 .device = 0x12f1,
520 .name = "HP xw8200", /* AD1981B*/
521 .type = AC97_TUNE_HP_ONLY
522 },
523 {
524 .vendor = 0x103c,
525 .device = 0x3008,
526 .name = "HP xw4200", /* AD1981B*/
527 .type = AC97_TUNE_HP_ONLY
528 },
529 {
530 .vendor = 0x10f1,
531 .device = 0x2665,
532 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
533 .type = AC97_TUNE_HP_ONLY
534 },
535 {
536 .vendor = 0x10f1,
537 .device = 0x2885,
538 .name = "AMD64 Mobo", /* ALC650 */
539 .type = AC97_TUNE_HP_ONLY
540 },
541 {
542 .vendor = 0x110a,
543 .device = 0x0056,
544 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
545 .type = AC97_TUNE_HP_ONLY
546 },
547 {
548 .vendor = 0x11d4,
549 .device = 0x5375,
550 .name = "ADI AD1985 (discrete)",
551 .type = AC97_TUNE_HP_ONLY
552 },
553 {
554 .vendor = 0x1462,
555 .device = 0x5470,
556 .name = "MSI P4 ATX 645 Ultra",
557 .type = AC97_TUNE_HP_ONLY
558 },
559 {
560 .vendor = 0x1734,
561 .device = 0x0088,
562 .name = "Fujitsu-Siemens D1522", /* AD1981 */
563 .type = AC97_TUNE_HP_ONLY
564 },
565 {
566 .vendor = 0x8086,
567 .device = 0x4856,
568 .name = "Intel D845WN (82801BA)",
569 .type = AC97_TUNE_SWAP_HP
570 },
571 {
572 .vendor = 0x8086,
573 .device = 0x4d44,
574 .name = "Intel D850EMV2", /* AD1885 */
575 .type = AC97_TUNE_HP_ONLY
576 },
577 {
578 .vendor = 0x8086,
579 .device = 0x4d56,
580 .name = "Intel ICH/AD1885",
581 .type = AC97_TUNE_HP_ONLY
582 },
583 {
584 .vendor = 0x1028,
585 .device = 0x012d,
586 .name = "Dell Precision 450", /* AD1981B*/
587 .type = AC97_TUNE_HP_ONLY
588 },
589 {
590 .vendor = 0x103c,
591 .device = 0x3008,
592 .name = "HP xw4200", /* AD1981B*/
593 .type = AC97_TUNE_HP_ONLY
594 },
595 {
596 .vendor = 0x103c,
597 .device = 0x12f1,
598 .name = "HP xw8200", /* AD1981B*/
599 .type = AC97_TUNE_HP_ONLY
600 },
601 { } /* terminator */
602 };
603
604 static struct i810_card *devs = NULL;
605
606 static int i810_open_mixdev(struct inode *inode, struct file *file);
607 static int i810_ioctl_mixdev(struct inode *inode, struct file *file,
608 unsigned int cmd, unsigned long arg);
609 static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg);
610 static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data);
611 static u16 i810_ac97_get_mmio(struct ac97_codec *dev, u8 reg);
612 static void i810_ac97_set_mmio(struct ac97_codec *dev, u8 reg, u16 data);
613 static u16 i810_ac97_get_io(struct ac97_codec *dev, u8 reg);
614 static void i810_ac97_set_io(struct ac97_codec *dev, u8 reg, u16 data);
615
616 static struct i810_channel *i810_alloc_pcm_channel(struct i810_card *card)
617 {
618 if(card->channel[1].used==1)
619 return NULL;
620 card->channel[1].used=1;
621 return &card->channel[1];
622 }
623
624 static struct i810_channel *i810_alloc_rec_pcm_channel(struct i810_card *card)
625 {
626 if(card->channel[0].used==1)
627 return NULL;
628 card->channel[0].used=1;
629 return &card->channel[0];
630 }
631
632 static struct i810_channel *i810_alloc_rec_mic_channel(struct i810_card *card)
633 {
634 if(card->channel[2].used==1)
635 return NULL;
636 card->channel[2].used=1;
637 return &card->channel[2];
638 }
639
640 static void i810_free_pcm_channel(struct i810_card *card, int channel)
641 {
642 card->channel[channel].used=0;
643 }
644
645 static int i810_valid_spdif_rate ( struct ac97_codec *codec, int rate )
646 {
647 unsigned long id = 0L;
648
649 id = (i810_ac97_get(codec, AC97_VENDOR_ID1) << 16);
650 id |= i810_ac97_get(codec, AC97_VENDOR_ID2) & 0xffff;
651 #ifdef DEBUG
652 printk ( "i810_audio: codec = %s, codec_id = 0x%08lx\n", codec->name, id);
653 #endif
654 switch ( id ) {
655 case 0x41445361: /* AD1886 */
656 if (rate == 48000) {
657 return 1;
658 }
659 break;
660 default: /* all other codecs, until we know otherwiae */
661 if (rate == 48000 || rate == 44100 || rate == 32000) {
662 return 1;
663 }
664 break;
665 }
666 return (0);
667 }
668
669 /* i810_set_spdif_output
670 *
671 * Configure the S/PDIF output transmitter. When we turn on
672 * S/PDIF, we turn off the analog output. This may not be
673 * the right thing to do.
674 *
675 * Assumptions:
676 * The DSP sample rate must already be set to a supported
677 * S/PDIF rate (32kHz, 44.1kHz, or 48kHz) or we abort.
678 */
679 static int i810_set_spdif_output(struct i810_state *state, int slots, int rate)
680 {
681 int vol;
682 int aud_reg;
683 int r = 0;
684 struct ac97_codec *codec = state->card->ac97_codec[0];
685
686 if(!codec->codec_ops->digital) {
687 state->card->ac97_status &= ~SPDIF_ON;
688 } else {
689 if ( slots == -1 ) { /* Turn off S/PDIF */
690 codec->codec_ops->digital(codec, 0, 0, 0);
691 /* If the volume wasn't muted before we turned on S/PDIF, unmute it */
692 if ( !(state->card->ac97_status & VOL_MUTED) ) {
693 aud_reg = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO);
694 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (aud_reg & ~VOL_MUTED));
695 }
696 state->card->ac97_status &= ~(VOL_MUTED | SPDIF_ON);
697 return 0;
698 }
699
700 vol = i810_ac97_get(codec, AC97_MASTER_VOL_STEREO);
701 state->card->ac97_status = vol & VOL_MUTED;
702
703 r = codec->codec_ops->digital(codec, slots, rate, 0);
704
705 if(r)
706 state->card->ac97_status |= SPDIF_ON;
707 else
708 state->card->ac97_status &= ~SPDIF_ON;
709
710 /* Mute the analog output */
711 /* Should this only mute the PCM volume??? */
712 i810_ac97_set(codec, AC97_MASTER_VOL_STEREO, (vol | VOL_MUTED));
713 }
714 return r;
715 }
716
717 /* i810_set_dac_channels
718 *
719 * Configure the codec's multi-channel DACs
720 *
721 * The logic is backwards. Setting the bit to 1 turns off the DAC.
722 *
723 * What about the ICH? We currently configure it using the
724 * SNDCTL_DSP_CHANNELS ioctl. If we're turnning on the DAC,
725 * does that imply that we want the ICH set to support
726 * these channels?
727 *
728 * TODO:
729 * vailidate that the codec really supports these DACs
730 * before turning them on.
731 */
732 static void i810_set_dac_channels(struct i810_state *state, int channel)
733 {
734 int aud_reg;
735 struct ac97_codec *codec = state->card->ac97_codec[0];
736
737 /* No codec, no setup */
738
739 if(codec == NULL)
740 return;
741
742 aud_reg = i810_ac97_get(codec, AC97_EXTENDED_STATUS);
743 aud_reg |= AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK;
744 state->card->ac97_status &= ~(SURR_ON | CENTER_LFE_ON);
745
746 switch ( channel ) {
747 case 2: /* always enabled */
748 break;
749 case 4:
750 aud_reg &= ~AC97_EA_PRJ;
751 state->card->ac97_status |= SURR_ON;
752 break;
753 case 6:
754 aud_reg &= ~(AC97_EA_PRJ | AC97_EA_PRI | AC97_EA_PRK);
755 state->card->ac97_status |= SURR_ON | CENTER_LFE_ON;
756 break;
757 default:
758 break;
759 }
760 i810_ac97_set(codec, AC97_EXTENDED_STATUS, aud_reg);
761
762 }
763
764
765 /* set playback sample rate */
766 static unsigned int i810_set_dac_rate(struct i810_state * state, unsigned int rate)
767 {
768 struct dmabuf *dmabuf = &state->dmabuf;
769 u32 new_rate;
770 struct ac97_codec *codec=state->card->ac97_codec[0];
771
772 if(!(state->card->ac97_features&0x0001))
773 {
774 dmabuf->rate = clocking;
775 #ifdef DEBUG
776 printk("Asked for %d Hz, but ac97_features says we only do %dHz. Sorry!\n",
777 rate,clocking);
778 #endif
779 return clocking;
780 }
781
782 if (rate > 48000)
783 rate = 48000;
784 if (rate < 8000)
785 rate = 8000;
786 dmabuf->rate = rate;
787
788 /*
789 * Adjust for misclocked crap
790 */
791 rate = ( rate * clocking)/48000;
792 if(strict_clocking && rate < 8000) {
793 rate = 8000;
794 dmabuf->rate = (rate * 48000)/clocking;
795 }
796
797 new_rate=ac97_set_dac_rate(codec, rate);
798 if(new_rate != rate) {
799 dmabuf->rate = (new_rate * 48000)/clocking;
800 }
801 #ifdef DEBUG
802 printk("i810_audio: called i810_set_dac_rate : asked for %d, got %d\n", rate, dmabuf->rate);
803 #endif
804 rate = new_rate;
805 return dmabuf->rate;
806 }
807
808 /* set recording sample rate */
809 static unsigned int i810_set_adc_rate(struct i810_state * state, unsigned int rate)
810 {
811 struct dmabuf *dmabuf = &state->dmabuf;
812 u32 new_rate;
813 struct ac97_codec *codec=state->card->ac97_codec[0];
814
815 if(!(state->card->ac97_features&0x0001))
816 {
817 dmabuf->rate = clocking;
818 return clocking;
819 }
820
821 if (rate > 48000)
822 rate = 48000;
823 if (rate < 8000)
824 rate = 8000;
825 dmabuf->rate = rate;
826
827 /*
828 * Adjust for misclocked crap
829 */
830
831 rate = ( rate * clocking)/48000;
832 if(strict_clocking && rate < 8000) {
833 rate = 8000;
834 dmabuf->rate = (rate * 48000)/clocking;
835 }
836
837 new_rate = ac97_set_adc_rate(codec, rate);
838
839 if(new_rate != rate) {
840 dmabuf->rate = (new_rate * 48000)/clocking;
841 rate = new_rate;
842 }
843 #ifdef DEBUG
844 printk("i810_audio: called i810_set_adc_rate : rate = %d/%d\n", dmabuf->rate, rate);
845 #endif
846 return dmabuf->rate;
847 }
848
849 /* get current playback/recording dma buffer pointer (byte offset from LBA),
850 called with spinlock held! */
851
852 static inline unsigned i810_get_dma_addr(struct i810_state *state, int rec)
853 {
854 struct dmabuf *dmabuf = &state->dmabuf;
855 unsigned int civ, offset, port, port_picb, bytes = 2;
856
857 if (!dmabuf->enable)
858 return 0;
859
860 if (rec)
861 port = dmabuf->read_channel->port;
862 else
863 port = dmabuf->write_channel->port;
864
865 if(state->card->pci_id == PCI_DEVICE_ID_SI_7012) {
866 port_picb = port + OFF_SR;
867 bytes = 1;
868 } else
869 port_picb = port + OFF_PICB;
870
871 do {
872 civ = GET_CIV(state->card, port);
873 offset = I810_IOREADW(state->card, port_picb);
874 /* Must have a delay here! */
875 if(offset == 0)
876 udelay(1);
877 /* Reread both registers and make sure that that total
878 * offset from the first reading to the second is 0.
879 * There is an issue with SiS hardware where it will count
880 * picb down to 0, then update civ to the next value,
881 * then set the new picb to fragsize bytes. We can catch
882 * it between the civ update and the picb update, making
883 * it look as though we are 1 fragsize ahead of where we
884 * are. The next to we get the address though, it will
885 * be back in the right place, and we will suddenly think
886 * we just went forward dmasize - fragsize bytes, causing
887 * totally stupid *huge* dma overrun messages. We are
888 * assuming that the 1us delay is more than long enough
889 * that we won't have to worry about the chip still being
890 * out of sync with reality ;-)
891 */
892 } while (civ != GET_CIV(state->card, port) || offset != I810_IOREADW(state->card, port_picb));
893
894 return (((civ + 1) * dmabuf->fragsize - (bytes * offset))
895 % dmabuf->dmasize);
896 }
897
898 /* Stop recording (lock held) */
899 static inline void __stop_adc(struct i810_state *state)
900 {
901 struct dmabuf *dmabuf = &state->dmabuf;
902 struct i810_card *card = state->card;
903
904 dmabuf->enable &= ~ADC_RUNNING;
905 I810_IOWRITEB(0, card, PI_CR);
906 // wait for the card to acknowledge shutdown
907 while( I810_IOREADB(card, PI_CR) != 0 ) ;
908 // now clear any latent interrupt bits (like the halt bit)
909 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
910 I810_IOWRITEB( I810_IOREADB(card, PI_PICB), card, PI_PICB );
911 else
912 I810_IOWRITEB( I810_IOREADB(card, PI_SR), card, PI_SR );
913 I810_IOWRITEL( I810_IOREADL(card, GLOB_STA) & INT_PI, card, GLOB_STA);
914 }
915
916 static void stop_adc(struct i810_state *state)
917 {
918 struct i810_card *card = state->card;
919 unsigned long flags;
920
921 spin_lock_irqsave(&card->lock, flags);
922 __stop_adc(state);
923 spin_unlock_irqrestore(&card->lock, flags);
924 }
925
926 static inline void __start_adc(struct i810_state *state)
927 {
928 struct dmabuf *dmabuf = &state->dmabuf;
929
930 if (dmabuf->count < dmabuf->dmasize && dmabuf->ready && !dmabuf->enable &&
931 (dmabuf->trigger & PCM_ENABLE_INPUT)) {
932 dmabuf->enable |= ADC_RUNNING;
933 // Interrupt enable, LVI enable, DMA enable
934 I810_IOWRITEB(0x10 | 0x04 | 0x01, state->card, PI_CR);
935 }
936 }
937
938 static void start_adc(struct i810_state *state)
939 {
940 struct i810_card *card = state->card;
941 unsigned long flags;
942
943 spin_lock_irqsave(&card->lock, flags);
944 __start_adc(state);
945 spin_unlock_irqrestore(&card->lock, flags);
946 }
947
948 /* stop playback (lock held) */
949 static inline void __stop_dac(struct i810_state *state)
950 {
951 struct dmabuf *dmabuf = &state->dmabuf;
952 struct i810_card *card = state->card;
953
954 dmabuf->enable &= ~DAC_RUNNING;
955 I810_IOWRITEB(0, card, PO_CR);
956 // wait for the card to acknowledge shutdown
957 while( I810_IOREADB(card, PO_CR) != 0 ) ;
958 // now clear any latent interrupt bits (like the halt bit)
959 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
960 I810_IOWRITEB( I810_IOREADB(card, PO_PICB), card, PO_PICB );
961 else
962 I810_IOWRITEB( I810_IOREADB(card, PO_SR), card, PO_SR );
963 I810_IOWRITEL( I810_IOREADL(card, GLOB_STA) & INT_PO, card, GLOB_STA);
964 }
965
966 static void stop_dac(struct i810_state *state)
967 {
968 struct i810_card *card = state->card;
969 unsigned long flags;
970
971 spin_lock_irqsave(&card->lock, flags);
972 __stop_dac(state);
973 spin_unlock_irqrestore(&card->lock, flags);
974 }
975
976 static inline void __start_dac(struct i810_state *state)
977 {
978 struct dmabuf *dmabuf = &state->dmabuf;
979
980 if (dmabuf->count > 0 && dmabuf->ready && !dmabuf->enable &&
981 (dmabuf->trigger & PCM_ENABLE_OUTPUT)) {
982 dmabuf->enable |= DAC_RUNNING;
983 // Interrupt enable, LVI enable, DMA enable
984 I810_IOWRITEB(0x10 | 0x04 | 0x01, state->card, PO_CR);
985 }
986 }
987 static void start_dac(struct i810_state *state)
988 {
989 struct i810_card *card = state->card;
990 unsigned long flags;
991
992 spin_lock_irqsave(&card->lock, flags);
993 __start_dac(state);
994 spin_unlock_irqrestore(&card->lock, flags);
995 }
996
997 #define DMABUF_DEFAULTORDER (16-PAGE_SHIFT)
998 #define DMABUF_MINORDER 1
999
1000 /* allocate DMA buffer, playback and recording buffer should be allocated separately */
1001 static int alloc_dmabuf(struct i810_state *state)
1002 {
1003 struct dmabuf *dmabuf = &state->dmabuf;
1004 void *rawbuf= NULL;
1005 int order, size;
1006 struct page *page, *pend;
1007
1008 /* If we don't have any oss frag params, then use our default ones */
1009 if(dmabuf->ossmaxfrags == 0)
1010 dmabuf->ossmaxfrags = 4;
1011 if(dmabuf->ossfragsize == 0)
1012 dmabuf->ossfragsize = (PAGE_SIZE<<DMABUF_DEFAULTORDER)/dmabuf->ossmaxfrags;
1013 size = dmabuf->ossfragsize * dmabuf->ossmaxfrags;
1014
1015 if(dmabuf->rawbuf && (PAGE_SIZE << dmabuf->buforder) == size)
1016 return 0;
1017 /* alloc enough to satisfy the oss params */
1018 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--) {
1019 if ( (PAGE_SIZE<<order) > size )
1020 continue;
1021 if ((rawbuf = pci_alloc_consistent(state->card->pci_dev,
1022 PAGE_SIZE << order,
1023 &dmabuf->dma_handle)))
1024 break;
1025 }
1026 if (!rawbuf)
1027 return -ENOMEM;
1028
1029
1030 #ifdef DEBUG
1031 printk("i810_audio: allocated %ld (order = %d) bytes at %p\n",
1032 PAGE_SIZE << order, order, rawbuf);
1033 #endif
1034
1035 dmabuf->ready = dmabuf->mapped = 0;
1036 dmabuf->rawbuf = rawbuf;
1037 dmabuf->buforder = order;
1038
1039 /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
1040 pend = virt_to_page(rawbuf + (PAGE_SIZE << order) - 1);
1041 for (page = virt_to_page(rawbuf); page <= pend; page++)
1042 SetPageReserved(page);
1043
1044 return 0;
1045 }
1046
1047 /* free DMA buffer */
1048 static void dealloc_dmabuf(struct i810_state *state)
1049 {
1050 struct dmabuf *dmabuf = &state->dmabuf;
1051 struct page *page, *pend;
1052
1053 if (dmabuf->rawbuf) {
1054 /* undo marking the pages as reserved */
1055 pend = virt_to_page(dmabuf->rawbuf + (PAGE_SIZE << dmabuf->buforder) - 1);
1056 for (page = virt_to_page(dmabuf->rawbuf); page <= pend; page++)
1057 ClearPageReserved(page);
1058 pci_free_consistent(state->card->pci_dev, PAGE_SIZE << dmabuf->buforder,
1059 dmabuf->rawbuf, dmabuf->dma_handle);
1060 }
1061 dmabuf->rawbuf = NULL;
1062 dmabuf->mapped = dmabuf->ready = 0;
1063 }
1064
1065 static int prog_dmabuf(struct i810_state *state, unsigned rec)
1066 {
1067 struct dmabuf *dmabuf = &state->dmabuf;
1068 struct i810_channel *c;
1069 struct sg_item *sg;
1070 unsigned long flags;
1071 int ret;
1072 unsigned fragint;
1073 int i;
1074
1075 spin_lock_irqsave(&state->card->lock, flags);
1076 if(dmabuf->enable & DAC_RUNNING)
1077 __stop_dac(state);
1078 if(dmabuf->enable & ADC_RUNNING)
1079 __stop_adc(state);
1080 dmabuf->total_bytes = 0;
1081 dmabuf->count = dmabuf->error = 0;
1082 dmabuf->swptr = dmabuf->hwptr = 0;
1083 spin_unlock_irqrestore(&state->card->lock, flags);
1084
1085 /* allocate DMA buffer, let alloc_dmabuf determine if we are already
1086 * allocated well enough or if we should replace the current buffer
1087 * (assuming one is already allocated, if it isn't, then allocate it).
1088 */
1089 if ((ret = alloc_dmabuf(state)))
1090 return ret;
1091
1092 /* FIXME: figure out all this OSS fragment stuff */
1093 /* I did, it now does what it should according to the OSS API. DL */
1094 /* We may not have realloced our dmabuf, but the fragment size to
1095 * fragment number ratio may have changed, so go ahead and reprogram
1096 * things
1097 */
1098 dmabuf->dmasize = PAGE_SIZE << dmabuf->buforder;
1099 dmabuf->numfrag = SG_LEN;
1100 dmabuf->fragsize = dmabuf->dmasize/dmabuf->numfrag;
1101 dmabuf->fragsamples = dmabuf->fragsize >> 1;
1102 dmabuf->fragshift = ffs(dmabuf->fragsize) - 1;
1103 dmabuf->userfragsize = dmabuf->ossfragsize;
1104 dmabuf->userfrags = dmabuf->dmasize/dmabuf->ossfragsize;
1105
1106 memset(dmabuf->rawbuf, 0, dmabuf->dmasize);
1107
1108 if(dmabuf->ossmaxfrags == 4) {
1109 fragint = 8;
1110 } else if (dmabuf->ossmaxfrags == 8) {
1111 fragint = 4;
1112 } else if (dmabuf->ossmaxfrags == 16) {
1113 fragint = 2;
1114 } else {
1115 fragint = 1;
1116 }
1117 /*
1118 * Now set up the ring
1119 */
1120 if(dmabuf->read_channel)
1121 c = dmabuf->read_channel;
1122 else
1123 c = dmabuf->write_channel;
1124 while(c != NULL) {
1125 sg=&c->sg[0];
1126 /*
1127 * Load up 32 sg entries and take an interrupt at half
1128 * way (we might want more interrupts later..)
1129 */
1130
1131 for(i=0;i<dmabuf->numfrag;i++)
1132 {
1133 sg->busaddr=(u32)dmabuf->dma_handle+dmabuf->fragsize*i;
1134 // the card will always be doing 16bit stereo
1135 sg->control=dmabuf->fragsamples;
1136 if(state->card->pci_id == PCI_DEVICE_ID_SI_7012)
1137 sg->control <<= 1;
1138 sg->control|=CON_BUFPAD;
1139 // set us up to get IOC interrupts as often as needed to
1140 // satisfy numfrag requirements, no more
1141 if( ((i+1) % fragint) == 0) {
1142 sg->control|=CON_IOC;
1143 }
1144 sg++;
1145 }
1146 spin_lock_irqsave(&state->card->lock, flags);
1147 I810_IOWRITEB(2, state->card, c->port+OFF_CR); /* reset DMA machine */
1148 while( I810_IOREADB(state->card, c->port+OFF_CR) & 0x02 ) ;
1149 I810_IOWRITEL((u32)state->card->chandma +
1150 c->num*sizeof(struct i810_channel),
1151 state->card, c->port+OFF_BDBAR);
1152 CIV_TO_LVI(state->card, c->port, 0);
1153
1154 spin_unlock_irqrestore(&state->card->lock, flags);
1155
1156 if(c != dmabuf->write_channel)
1157 c = dmabuf->write_channel;
1158 else
1159 c = NULL;
1160 }
1161
1162 /* set the ready flag for the dma buffer */
1163 dmabuf->ready = 1;
1164
1165 #ifdef DEBUG
1166 printk("i810_audio: prog_dmabuf, sample rate = %d, format = %d,\n\tnumfrag = %d, "
1167 "fragsize = %d dmasize = %d\n",
1168 dmabuf->rate, dmabuf->fmt, dmabuf->numfrag,
1169 dmabuf->fragsize, dmabuf->dmasize);
1170 #endif
1171
1172 return 0;
1173 }
1174
1175 static void __i810_update_lvi(struct i810_state *state, int rec)
1176 {
1177 struct dmabuf *dmabuf = &state->dmabuf;
1178 int x, port;
1179 int trigger;
1180 int count, fragsize;
1181 void (*start)(struct i810_state *);
1182
1183 count = dmabuf->count;
1184 if (rec) {
1185 port = dmabuf->read_channel->port;
1186 trigger = PCM_ENABLE_INPUT;
1187 start = __start_adc;
1188 count = dmabuf->dmasize - count;
1189 } else {
1190 port = dmabuf->write_channel->port;
1191 trigger = PCM_ENABLE_OUTPUT;
1192 start = __start_dac;
1193 }
1194
1195 /* Do not process partial fragments. */
1196 fragsize = dmabuf->fragsize;
1197 if (count < fragsize)
1198 return;
1199
1200 /* if we are currently stopped, then our CIV is actually set to our
1201 * *last* sg segment and we are ready to wrap to the next. However,
1202 * if we set our LVI to the last sg segment, then it won't wrap to
1203 * the next sg segment, it won't even get a start. So, instead, when
1204 * we are stopped, we set both the LVI value and also we increment
1205 * the CIV value to the next sg segment to be played so that when
1206 * we call start, things will operate properly. Since the CIV can't
1207 * be written to directly for this purpose, we set the LVI to CIV + 1
1208 * temporarily. Once the engine has started we set the LVI to its
1209 * final value.
1210 */
1211 if (!dmabuf->enable && dmabuf->ready) {
1212 if (!(dmabuf->trigger & trigger))
1213 return;
1214
1215 CIV_TO_LVI(state->card, port, 1);
1216
1217 start(state);
1218 while (!(I810_IOREADB(state->card, port + OFF_CR) & ((1<<4) | (1<<2))))
1219 ;
1220 }
1221
1222 /* MASKP2(swptr, fragsize) - 1 is the tail of our transfer */
1223 x = MODULOP2(MASKP2(dmabuf->swptr, fragsize) - 1, dmabuf->dmasize);
1224 x >>= dmabuf->fragshift;
1225 I810_IOWRITEB(x, state->card, port + OFF_LVI);
1226 }
1227
1228 static void i810_update_lvi(struct i810_state *state, int rec)
1229 {
1230 struct dmabuf *dmabuf = &state->dmabuf;
1231 unsigned long flags;
1232
1233 if(!dmabuf->ready)
1234 return;
1235 spin_lock_irqsave(&state->card->lock, flags);
1236 __i810_update_lvi(state, rec);
1237 spin_unlock_irqrestore(&state->card->lock, flags);
1238 }
1239
1240 /* update buffer manangement pointers, especially, dmabuf->count and dmabuf->hwptr */
1241 static void i810_update_ptr(struct i810_state *state)
1242 {
1243 struct dmabuf *dmabuf = &state->dmabuf;
1244 unsigned hwptr;
1245 unsigned fragmask, dmamask;
1246 int diff;
1247
1248 fragmask = MASKP2(~0, dmabuf->fragsize);
1249 dmamask = MODULOP2(~0, dmabuf->dmasize);
1250
1251 /* error handling and process wake up for ADC */
1252 if (dmabuf->enable == ADC_RUNNING) {
1253 /* update hardware pointer */
1254 hwptr = i810_get_dma_addr(state, 1) & fragmask;
1255 diff = (hwptr - dmabuf->hwptr) & dmamask;
1256 #if defined(DEBUG_INTERRUPTS) || defined(DEBUG_MMAP)
1257 printk("ADC HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff);
1258 #endif
1259 dmabuf->hwptr = hwptr;
1260 dmabuf->total_bytes += diff;
1261 dmabuf->count += diff;
1262 if (dmabuf->count > dmabuf->dmasize) {
1263 /* buffer underrun or buffer overrun */
1264 /* this is normal for the end of a read */
1265 /* only give an error if we went past the */
1266 /* last valid sg entry */
1267 if (GET_CIV(state->card, PI_BASE) !=
1268 GET_LVI(state->card, PI_BASE)) {
1269 printk(KERN_WARNING "i810_audio: DMA overrun on read\n");
1270 dmabuf->error++;
1271 }
1272 }
1273 if (diff)
1274 wake_up(&dmabuf->wait);
1275 }
1276 /* error handling and process wake up for DAC */
1277 if (dmabuf->enable == DAC_RUNNING) {
1278 /* update hardware pointer */
1279 hwptr = i810_get_dma_addr(state, 0) & fragmask;
1280 diff = (hwptr - dmabuf->hwptr) & dmamask;
1281 #if defined(DEBUG_INTERRUPTS) || defined(DEBUG_MMAP)
1282 printk("DAC HWP %d,%d,%d\n", hwptr, dmabuf->hwptr, diff);
1283 #endif
1284 dmabuf->hwptr = hwptr;
1285 dmabuf->total_bytes += diff;
1286 dmabuf->count -= diff;
1287 if (dmabuf->count < 0) {
1288 /* buffer underrun or buffer overrun */
1289 /* this is normal for the end of a write */
1290 /* only give an error if we went past the */
1291 /* last valid sg entry */
1292 if (GET_CIV(state->card, PO_BASE) !=
1293 GET_LVI(state->card, PO_BASE)) {
1294 printk(KERN_WARNING "i810_audio: DMA overrun on write\n");
1295 printk("i810_audio: CIV %d, LVI %d, hwptr %x, "
1296 "count %d\n",
1297 GET_CIV(state->card, PO_BASE),
1298 GET_LVI(state->card, PO_BASE),
1299 dmabuf->hwptr, dmabuf->count);
1300 dmabuf->error++;
1301 }
1302 }
1303 if (diff)
1304 wake_up(&dmabuf->wait);
1305 }
1306 }
1307
1308 static inline int i810_get_free_write_space(struct i810_state *state)
1309 {
1310 struct dmabuf *dmabuf = &state->dmabuf;
1311 int free;
1312
1313 i810_update_ptr(state);
1314 // catch underruns during playback
1315 if (dmabuf->count < 0) {
1316 dmabuf->count = 0;
1317 dmabuf->swptr = dmabuf->hwptr;
1318 }
1319 free = dmabuf->dmasize - dmabuf->count;
1320 if(free < 0)
1321 return(0);
1322 return(free);
1323 }
1324
1325 static inline int i810_get_available_read_data(struct i810_state *state)
1326 {
1327 struct dmabuf *dmabuf = &state->dmabuf;
1328 int avail;
1329
1330 i810_update_ptr(state);
1331 // catch overruns during record
1332 if (dmabuf->count > dmabuf->dmasize) {
1333 dmabuf->count = dmabuf->dmasize;
1334 dmabuf->swptr = dmabuf->hwptr;
1335 }
1336 avail = dmabuf->count;
1337 if(avail < 0)
1338 return(0);
1339 return(avail);
1340 }
1341
1342 static inline void fill_partial_frag(struct dmabuf *dmabuf)
1343 {
1344 unsigned fragsize;
1345 unsigned swptr, len;
1346
1347 fragsize = dmabuf->fragsize;
1348 swptr = dmabuf->swptr;
1349 len = fragsize - MODULOP2(dmabuf->swptr, fragsize);
1350 if (len == fragsize)
1351 return;
1352
1353 memset(dmabuf->rawbuf + swptr, '\0', len);
1354 dmabuf->swptr = MODULOP2(swptr + len, dmabuf->dmasize);
1355 dmabuf->count += len;
1356 }
1357
1358 static int drain_dac(struct i810_state *state, int signals_allowed)
1359 {
1360 DECLARE_WAITQUEUE(wait, current);
1361 struct dmabuf *dmabuf = &state->dmabuf;
1362 unsigned long flags;
1363 unsigned long tmo;
1364 int count;
1365
1366 if (!dmabuf->ready)
1367 return 0;
1368 if(dmabuf->mapped) {
1369 stop_dac(state);
1370 return 0;
1371 }
1372
1373 spin_lock_irqsave(&state->card->lock, flags);
1374
1375 fill_partial_frag(dmabuf);
1376
1377 /*
1378 * This will make sure that our LVI is correct, that our
1379 * pointer is updated, and that the DAC is running. We
1380 * have to force the setting of dmabuf->trigger to avoid
1381 * any possible deadlocks.
1382 */
1383 dmabuf->trigger = PCM_ENABLE_OUTPUT;
1384 __i810_update_lvi(state, 0);
1385
1386 spin_unlock_irqrestore(&state->card->lock, flags);
1387
1388 add_wait_queue(&dmabuf->wait, &wait);
1389 for (;;) {
1390
1391 spin_lock_irqsave(&state->card->lock, flags);
1392 i810_update_ptr(state);
1393 count = dmabuf->count;
1394
1395 /* It seems that we have to set the current state to
1396 * TASK_INTERRUPTIBLE every time to make the process
1397 * really go to sleep. This also has to be *after* the
1398 * update_ptr() call because update_ptr is likely to
1399 * do a wake_up() which will unset this before we ever
1400 * try to sleep, resuling in a tight loop in this code
1401 * instead of actually sleeping and waiting for an
1402 * interrupt to wake us up!
1403 */
1404 __set_current_state(signals_allowed ?
1405 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1406 spin_unlock_irqrestore(&state->card->lock, flags);
1407
1408 if (count <= 0)
1409 break;
1410
1411 if (signal_pending(current) && signals_allowed) {
1412 break;
1413 }
1414
1415 /*
1416 * set the timeout to significantly longer than it *should*
1417 * take for the DAC to drain the DMA buffer
1418 */
1419 tmo = (count * HZ) / (dmabuf->rate);
1420 if (!schedule_timeout(tmo >= 2 ? tmo : 2)){
1421 printk(KERN_ERR "i810_audio: drain_dac, dma timeout?\n");
1422 count = 0;
1423 break;
1424 }
1425 }
1426 set_current_state(TASK_RUNNING);
1427 remove_wait_queue(&dmabuf->wait, &wait);
1428 if(count > 0 && signal_pending(current) && signals_allowed)
1429 return -ERESTARTSYS;
1430 stop_dac(state);
1431 return 0;
1432 }
1433
1434 static void i810_channel_interrupt(struct i810_card *card)
1435 {
1436 int i, count;
1437
1438 #ifdef DEBUG_INTERRUPTS
1439 printk("CHANNEL ");
1440 #endif
1441 for(i=0;i<NR_HW_CH;i++)
1442 {
1443 struct i810_state *state = card->states[i];
1444 struct i810_channel *c;
1445 struct dmabuf *dmabuf;
1446 unsigned long port;
1447 u16 status;
1448
1449 if(!state)
1450 continue;
1451 if(!state->dmabuf.ready)
1452 continue;
1453 dmabuf = &state->dmabuf;
1454 if(dmabuf->enable & DAC_RUNNING) {
1455 c=dmabuf->write_channel;
1456 } else if(dmabuf->enable & ADC_RUNNING) {
1457 c=dmabuf->read_channel;
1458 } else /* This can occur going from R/W to close */
1459 continue;
1460
1461 port = c->port;
1462
1463 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
1464 status = I810_IOREADW(card, port + OFF_PICB);
1465 else
1466 status = I810_IOREADW(card, port + OFF_SR);
1467
1468 #ifdef DEBUG_INTERRUPTS
1469 printk("NUM %d PORT %X IRQ ( ST%d ", c->num, c->port, status);
1470 #endif
1471 if(status & DMA_INT_COMPLETE)
1472 {
1473 /* only wake_up() waiters if this interrupt signals
1474 * us being beyond a userfragsize of data open or
1475 * available, and i810_update_ptr() does that for
1476 * us
1477 */
1478 i810_update_ptr(state);
1479 #ifdef DEBUG_INTERRUPTS
1480 printk("COMP %d ", dmabuf->hwptr /
1481 dmabuf->fragsize);
1482 #endif
1483 }
1484 if(status & (DMA_INT_LVI | DMA_INT_DCH))
1485 {
1486 /* wake_up() unconditionally on LVI and DCH */
1487 i810_update_ptr(state);
1488 wake_up(&dmabuf->wait);
1489 #ifdef DEBUG_INTERRUPTS
1490 if(status & DMA_INT_LVI)
1491 printk("LVI ");
1492 if(status & DMA_INT_DCH)
1493 printk("DCH -");
1494 #endif
1495 count = dmabuf->count;
1496 if(dmabuf->enable & ADC_RUNNING)
1497 count = dmabuf->dmasize - count;
1498 if (count >= (int)dmabuf->fragsize) {
1499 I810_IOWRITEB(I810_IOREADB(card, port+OFF_CR) | 1, card, port+OFF_CR);
1500 #ifdef DEBUG_INTERRUPTS
1501 printk(" CONTINUE ");
1502 #endif
1503 } else {
1504 if (dmabuf->enable & DAC_RUNNING)
1505 __stop_dac(state);
1506 if (dmabuf->enable & ADC_RUNNING)
1507 __stop_adc(state);
1508 dmabuf->enable = 0;
1509 #ifdef DEBUG_INTERRUPTS
1510 printk(" STOP ");
1511 #endif
1512 }
1513 }
1514 if(card->pci_id == PCI_DEVICE_ID_SI_7012)
1515 I810_IOWRITEW(status & DMA_INT_MASK, card, port + OFF_PICB);
1516 else
1517 I810_IOWRITEW(status & DMA_INT_MASK, card, port + OFF_SR);
1518 }
1519 #ifdef DEBUG_INTERRUPTS
1520 printk(")\n");
1521 #endif
1522 }
1523
1524 static irqreturn_t i810_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1525 {
1526 struct i810_card *card = (struct i810_card *)dev_id;
1527 u32 status;
1528
1529 spin_lock(&card->lock);
1530
1531 status = I810_IOREADL(card, GLOB_STA);
1532
1533 if(!(status & INT_MASK))
1534 {
1535 spin_unlock(&card->lock);
1536 return IRQ_NONE; /* not for us */
1537 }
1538
1539 if(status & (INT_PO|INT_PI|INT_MC))
1540 i810_channel_interrupt(card);
1541
1542 /* clear 'em */
1543 I810_IOWRITEL(status & INT_MASK, card, GLOB_STA);
1544 spin_unlock(&card->lock);
1545 return IRQ_HANDLED;
1546 }
1547
1548 /* in this loop, dmabuf.count signifies the amount of data that is
1549 waiting to be copied to the user's buffer. It is filled by the dma
1550 machine and drained by this loop. */
1551
1552 static ssize_t i810_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1553 {
1554 struct i810_state *state = (struct i810_state *)file->private_data;
1555 struct i810_card *card=state ? state->card : NULL;
1556 struct dmabuf *dmabuf = &state->dmabuf;
1557 ssize_t ret;
1558 unsigned long flags;
1559 unsigned int swptr;
1560 int cnt;
1561 int pending;
1562 DECLARE_WAITQUEUE(waita, current);
1563
1564 #ifdef DEBUG2
1565 printk("i810_audio: i810_read called, count = %d\n", count);
1566 #endif
1567
1568 if (dmabuf->mapped)
1569 return -ENXIO;
1570 if (dmabuf->enable & DAC_RUNNING)
1571 return -ENODEV;
1572 if (!dmabuf->read_channel) {
1573 dmabuf->ready = 0;
1574 dmabuf->read_channel = card->alloc_rec_pcm_channel(card);
1575 if (!dmabuf->read_channel) {
1576 return -EBUSY;
1577 }
1578 }
1579 if (!dmabuf->ready && (ret = prog_dmabuf(state, 1)))
1580 return ret;
1581 if (!access_ok(VERIFY_WRITE, buffer, count))
1582 return -EFAULT;
1583 ret = 0;
1584
1585 pending = 0;
1586
1587 add_wait_queue(&dmabuf->wait, &waita);
1588 while (count > 0) {
1589 set_current_state(TASK_INTERRUPTIBLE);
1590 spin_lock_irqsave(&card->lock, flags);
1591 if (PM_SUSPENDED(card)) {
1592 spin_unlock_irqrestore(&card->lock, flags);
1593 schedule();
1594 if (signal_pending(current)) {
1595 if (!ret) ret = -EAGAIN;
1596 break;
1597 }
1598 continue;
1599 }
1600 cnt = i810_get_available_read_data(state);
1601 swptr = dmabuf->swptr;
1602 // this is to make the copy_to_user simpler below
1603 if(cnt > (dmabuf->dmasize - swptr))
1604 cnt = dmabuf->dmasize - swptr;
1605 spin_unlock_irqrestore(&card->lock, flags);
1606
1607 if (cnt > count)
1608 cnt = count;
1609 if (cnt <= 0) {
1610 unsigned long tmo;
1611 /*
1612 * Don't let us deadlock. The ADC won't start if
1613 * dmabuf->trigger isn't set. A call to SETTRIGGER
1614 * could have turned it off after we set it to on
1615 * previously.
1616 */
1617 dmabuf->trigger = PCM_ENABLE_INPUT;
1618 /*
1619 * This does three things. Updates LVI to be correct,
1620 * makes sure the ADC is running, and updates the
1621 * hwptr.
1622 */
1623 i810_update_lvi(state,1);
1624 if (file->f_flags & O_NONBLOCK) {
1625 if (!ret) ret = -EAGAIN;
1626 goto done;
1627 }
1628 /* Set the timeout to how long it would take to fill
1629 * two of our buffers. If we haven't been woke up
1630 * by then, then we know something is wrong.
1631 */
1632 tmo = (dmabuf->dmasize * HZ * 2) / (dmabuf->rate * 4);
1633 /* There are two situations when sleep_on_timeout returns, one is when
1634 the interrupt is serviced correctly and the process is waked up by
1635 ISR ON TIME. Another is when timeout is expired, which means that
1636 either interrupt is NOT serviced correctly (pending interrupt) or it
1637 is TOO LATE for the process to be scheduled to run (scheduler latency)
1638 which results in a (potential) buffer overrun. And worse, there is
1639 NOTHING we can do to prevent it. */
1640 if (!schedule_timeout(tmo >= 2 ? tmo : 2)) {
1641 #ifdef DEBUG
1642 printk(KERN_ERR "i810_audio: recording schedule timeout, "
1643 "dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1644 dmabuf->dmasize, dmabuf->fragsize, dmabuf->count,
1645 dmabuf->hwptr, dmabuf->swptr);
1646 #endif
1647 /* a buffer overrun, we delay the recovery until next time the
1648 while loop begin and we REALLY have space to record */
1649 }
1650 if (signal_pending(current)) {
1651 ret = ret ? ret : -ERESTARTSYS;
1652 goto done;
1653 }
1654 continue;
1655 }
1656
1657 if (copy_to_user(buffer, dmabuf->rawbuf + swptr, cnt)) {
1658 if (!ret) ret = -EFAULT;
1659 goto done;
1660 }
1661
1662 swptr = MODULOP2(swptr + cnt, dmabuf->dmasize);
1663
1664 spin_lock_irqsave(&card->lock, flags);
1665
1666 if (PM_SUSPENDED(card)) {
1667 spin_unlock_irqrestore(&card->lock, flags);
1668 continue;
1669 }
1670 dmabuf->swptr = swptr;
1671 pending = dmabuf->count -= cnt;
1672 spin_unlock_irqrestore(&card->lock, flags);
1673
1674 count -= cnt;
1675 buffer += cnt;
1676 ret += cnt;
1677 }
1678 done:
1679 pending = dmabuf->dmasize - pending;
1680 if (dmabuf->enable || pending >= dmabuf->userfragsize)
1681 i810_update_lvi(state, 1);
1682 set_current_state(TASK_RUNNING);
1683 remove_wait_queue(&dmabuf->wait, &waita);
1684
1685 return ret;
1686 }
1687
1688 /* in this loop, dmabuf.count signifies the amount of data that is waiting to be dma to
1689 the soundcard. it is drained by the dma machine and filled by this loop. */
1690 static ssize_t i810_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1691 {
1692 struct i810_state *state = (struct i810_state *)file->private_data;
1693 struct i810_card *card=state ? state->card : NULL;
1694 struct dmabuf *dmabuf = &state->dmabuf;
1695 ssize_t ret;
1696 unsigned long flags;
1697 unsigned int swptr = 0;
1698 int pending;
1699 int cnt;
1700 DECLARE_WAITQUEUE(waita, current);
1701
1702 #ifdef DEBUG2
1703 printk("i810_audio: i810_write called, count = %d\n", count);
1704 #endif
1705
1706 if (dmabuf->mapped)
1707 return -ENXIO;
1708 if (dmabuf->enable & ADC_RUNNING)
1709 return -ENODEV;
1710 if (!dmabuf->write_channel) {
1711 dmabuf->ready = 0;
1712 dmabuf->write_channel = card->alloc_pcm_channel(card);
1713 if(!dmabuf->write_channel)
1714 return -EBUSY;
1715 }
1716 if (!dmabuf->ready && (ret = prog_dmabuf(state, 0)))
1717 return ret;
1718 if (!access_ok(VERIFY_READ, buffer, count))
1719 return -EFAULT;
1720 ret = 0;
1721
1722 pending = 0;
1723
1724 add_wait_queue(&dmabuf->wait, &waita);
1725 while (count > 0) {
1726 set_current_state(TASK_INTERRUPTIBLE);
1727 spin_lock_irqsave(&state->card->lock, flags);
1728 if (PM_SUSPENDED(card)) {
1729 spin_unlock_irqrestore(&card->lock, flags);
1730 schedule();
1731 if (signal_pending(current)) {
1732 if (!ret) ret = -EAGAIN;
1733 break;
1734 }
1735 continue;
1736 }
1737
1738 cnt = i810_get_free_write_space(state);
1739 swptr = dmabuf->swptr;
1740 /* Bound the maximum size to how much we can copy to the
1741 * dma buffer before we hit the end. If we have more to
1742 * copy then it will get done in a second pass of this
1743 * loop starting from the beginning of the buffer.
1744 */
1745 if(cnt > (dmabuf->dmasize - swptr))
1746 cnt = dmabuf->dmasize - swptr;
1747 spin_unlock_irqrestore(&state->card->lock, flags);
1748
1749 #ifdef DEBUG2
1750 printk(KERN_INFO "i810_audio: i810_write: %d bytes available space\n", cnt);
1751 #endif
1752 if (cnt > count)
1753 cnt = count;
1754 if (cnt <= 0) {
1755 unsigned long tmo;
1756 // There is data waiting to be played
1757 /*
1758 * Force the trigger setting since we would
1759 * deadlock with it set any other way
1760 */
1761 dmabuf->trigger = PCM_ENABLE_OUTPUT;
1762 i810_update_lvi(state,0);
1763 if (file->f_flags & O_NONBLOCK) {
1764 if (!ret) ret = -EAGAIN;
1765 goto ret;
1766 }
1767 /* Not strictly correct but works */
1768 tmo = (dmabuf->dmasize * HZ * 2) / (dmabuf->rate * 4);
1769 /* There are two situations when sleep_on_timeout returns, one is when
1770 the interrupt is serviced correctly and the process is waked up by
1771 ISR ON TIME. Another is when timeout is expired, which means that
1772 either interrupt is NOT serviced correctly (pending interrupt) or it
1773 is TOO LATE for the process to be scheduled to run (scheduler latency)
1774 which results in a (potential) buffer underrun. And worse, there is
1775 NOTHING we can do to prevent it. */
1776 if (!schedule_timeout(tmo >= 2 ? tmo : 2)) {
1777 #ifdef DEBUG
1778 printk(KERN_ERR "i810_audio: playback schedule timeout, "
1779 "dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1780 dmabuf->dmasize, dmabuf->fragsize, dmabuf->count,
1781 dmabuf->hwptr, dmabuf->swptr);
1782 #endif
1783 /* a buffer underrun, we delay the recovery until next time the
1784 while loop begin and we REALLY have data to play */
1785 //return ret;
1786 }
1787 if (signal_pending(current)) {
1788 if (!ret) ret = -ERESTARTSYS;
1789 goto ret;
1790 }
1791 continue;
1792 }
1793 if (copy_from_user(dmabuf->rawbuf+swptr,buffer,cnt)) {
1794 if (!ret) ret = -EFAULT;
1795 goto ret;
1796 }
1797
1798 swptr = MODULOP2(swptr + cnt, dmabuf->dmasize);
1799
1800 spin_lock_irqsave(&state->card->lock, flags);
1801 if (PM_SUSPENDED(card)) {
1802 spin_unlock_irqrestore(&card->lock, flags);
1803 continue;
1804 }
1805
1806 dmabuf->swptr = swptr;
1807 pending = dmabuf->count += cnt;
1808
1809 count -= cnt;
1810 buffer += cnt;
1811 ret += cnt;
1812 spin_unlock_irqrestore(&state->card->lock, flags);
1813 }
1814 ret:
1815 if (dmabuf->enable || pending >= dmabuf->userfragsize)
1816 i810_update_lvi(state, 0);
1817 set_current_state(TASK_RUNNING);
1818 remove_wait_queue(&dmabuf->wait, &waita);
1819
1820 return ret;
1821 }
1822
1823 /* No kernel lock - we have our own spinlock */
1824 static unsigned int i810_poll(struct file *file, struct poll_table_struct *wait)
1825 {
1826 struct i810_state *state = (struct i810_state *)file->private_data;
1827 struct dmabuf *dmabuf = &state->dmabuf;
1828 unsigned long flags;
1829 unsigned int mask = 0;
1830
1831 if(!dmabuf->ready)
1832 return 0;
1833 poll_wait(file, &dmabuf->wait, wait);
1834 spin_lock_irqsave(&state->card->lock, flags);
1835 if (dmabuf->enable & ADC_RUNNING ||
1836 dmabuf->trigger & PCM_ENABLE_INPUT) {
1837 if (i810_get_available_read_data(state) >=
1838 (signed)dmabuf->userfragsize)
1839 mask |= POLLIN | POLLRDNORM;
1840 }
1841 if (dmabuf->enable & DAC_RUNNING ||
1842 dmabuf->trigger & PCM_ENABLE_OUTPUT) {
1843 if (i810_get_free_write_space(state) >=
1844 (signed)dmabuf->userfragsize)
1845 mask |= POLLOUT | POLLWRNORM;
1846 }
1847 spin_unlock_irqrestore(&state->card->lock, flags);
1848 return mask;
1849 }
1850
1851 static int i810_mmap(struct file *file, struct vm_area_struct *vma)
1852 {
1853 struct i810_state *state = (struct i810_state *)file->private_data;
1854 struct dmabuf *dmabuf = &state->dmabuf;
1855 int ret = -EINVAL;
1856 unsigned long size;
1857
1858 lock_kernel();
1859 if (vma->vm_flags & VM_WRITE) {
1860 if (!dmabuf->write_channel &&
1861 (dmabuf->write_channel =
1862 state->card->alloc_pcm_channel(state->card)) == NULL) {
1863 ret = -EBUSY;
1864 goto out;
1865 }
1866 }
1867 if (vma->vm_flags & VM_READ) {
1868 if (!dmabuf->read_channel &&
1869 (dmabuf->read_channel =
1870 state->card->alloc_rec_pcm_channel(state->card)) == NULL) {
1871 ret = -EBUSY;
1872 goto out;
1873 }
1874 }
1875 if ((ret = prog_dmabuf(state, 0)) != 0)
1876 goto out;
1877
1878 ret = -EINVAL;
1879 if (vma->vm_pgoff != 0)
1880 goto out;
1881 size = vma->vm_end - vma->vm_start;
1882 if (size > (PAGE_SIZE << dmabuf->buforder))
1883 goto out;
1884 ret = -EAGAIN;
1885 if (remap_pfn_range(vma, vma->vm_start,
1886 virt_to_phys(dmabuf->rawbuf) >> PAGE_SHIFT,
1887 size, vma->vm_page_prot))
1888 goto out;
1889 dmabuf->mapped = 1;
1890 dmabuf->trigger = 0;
1891 ret = 0;
1892 #ifdef DEBUG_MMAP
1893 printk("i810_audio: mmap'ed %ld bytes of data space\n", size);
1894 #endif
1895 out:
1896 unlock_kernel();
1897 return ret;
1898 }
1899
1900 static int i810_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1901 {
1902 struct i810_state *state = (struct i810_state *)file->private_data;
1903 struct i810_channel *c = NULL;
1904 struct dmabuf *dmabuf = &state->dmabuf;
1905 unsigned long flags;
1906 audio_buf_info abinfo;
1907 count_info cinfo;
1908 unsigned int i_glob_cnt;
1909 int val = 0, ret;
1910 struct ac97_codec *codec = state->card->ac97_codec[0];
1911 void __user *argp = (void __user *)arg;
1912 int __user *p = argp;
1913
1914 #ifdef DEBUG
1915 printk("i810_audio: i810_ioctl, arg=0x%x, cmd=", arg ? *p : 0);
1916 #endif
1917
1918 switch (cmd)
1919 {
1920 case OSS_GETVERSION:
1921 #ifdef DEBUG
1922 printk("OSS_GETVERSION\n");
1923 #endif
1924 return put_user(SOUND_VERSION, p);
1925
1926 case SNDCTL_DSP_RESET:
1927 #ifdef DEBUG
1928 printk("SNDCTL_DSP_RESET\n");
1929 #endif
1930 spin_lock_irqsave(&state->card->lock, flags);
1931 if (dmabuf->enable == DAC_RUNNING) {
1932 c = dmabuf->write_channel;
1933 __stop_dac(state);
1934 }
1935 if (dmabuf->enable == ADC_RUNNING) {
1936 c = dmabuf->read_channel;
1937 __stop_adc(state);
1938 }
1939 if (c != NULL) {
1940 I810_IOWRITEB(2, state->card, c->port+OFF_CR); /* reset DMA machine */
1941 while ( I810_IOREADB(state->card, c->port+OFF_CR) & 2 )
1942 cpu_relax();
1943 I810_IOWRITEL((u32)state->card->chandma +
1944 c->num*sizeof(struct i810_channel),
1945 state->card, c->port+OFF_BDBAR);
1946 CIV_TO_LVI(state->card, c->port, 0);
1947 }
1948
1949 spin_unlock_irqrestore(&state->card->lock, flags);
1950 synchronize_irq(state->card->pci_dev->irq);
1951 dmabuf->ready = 0;
1952 dmabuf->swptr = dmabuf->hwptr = 0;
1953 dmabuf->count = dmabuf->total_bytes = 0;
1954 return 0;
1955
1956 case SNDCTL_DSP_SYNC:
1957 #ifdef DEBUG
1958 printk("SNDCTL_DSP_SYNC\n");
1959 #endif
1960 if (dmabuf->enable != DAC_RUNNING || file->f_flags & O_NONBLOCK)
1961 return 0;
1962 if((val = drain_dac(state, 1)))
1963 return val;
1964 dmabuf->total_bytes = 0;
1965 return 0;
1966
1967 case SNDCTL_DSP_SPEED: /* set smaple rate */
1968 #ifdef DEBUG
1969 printk("SNDCTL_DSP_SPEED\n");
1970 #endif
1971 if (get_user(val, p))
1972 return -EFAULT;
1973 if (val >= 0) {
1974 if (file->f_mode & FMODE_WRITE) {
1975 if ( (state->card->ac97_status & SPDIF_ON) ) { /* S/PDIF Enabled */
1976 /* AD1886 only supports 48000, need to check that */
1977 if ( i810_valid_spdif_rate ( codec, val ) ) {
1978 /* Set DAC rate */
1979 i810_set_spdif_output ( state, -1, 0 );
1980 stop_dac(state);
1981 dmabuf->ready = 0;
1982 spin_lock_irqsave(&state->card->lock, flags);
1983 i810_set_dac_rate(state, val);
1984 spin_unlock_irqrestore(&state->card->lock, flags);
1985 /* Set S/PDIF transmitter rate. */
1986 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, val );
1987 if ( ! (state->card->ac97_status & SPDIF_ON) ) {
1988 val = dmabuf->rate;
1989 }
1990 } else { /* Not a valid rate for S/PDIF, ignore it */
1991 val = dmabuf->rate;
1992 }
1993 } else {
1994 stop_dac(state);
1995 dmabuf->ready = 0;
1996 spin_lock_irqsave(&state->card->lock, flags);
1997 i810_set_dac_rate(state, val);
1998 spin_unlock_irqrestore(&state->card->lock, flags);
1999 }
2000 }
2001 if (file->f_mode & FMODE_READ) {
2002 stop_adc(state);
2003 dmabuf->ready = 0;
2004 spin_lock_irqsave(&state->card->lock, flags);
2005 i810_set_adc_rate(state, val);
2006 spin_unlock_irqrestore(&state->card->lock, flags);
2007 }
2008 }
2009 return put_user(dmabuf->rate, p);
2010
2011 case SNDCTL_DSP_STEREO: /* set stereo or mono channel */
2012 #ifdef DEBUG
2013 printk("SNDCTL_DSP_STEREO\n");
2014 #endif
2015 if (dmabuf->enable & DAC_RUNNING) {
2016 stop_dac(state);
2017 }
2018 if (dmabuf->enable & ADC_RUNNING) {
2019 stop_adc(state);
2020 }
2021 return put_user(1, p);
2022
2023 case SNDCTL_DSP_GETBLKSIZE:
2024 if (file->f_mode & FMODE_WRITE) {
2025 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)))
2026 return val;
2027 }
2028 if (file->f_mode & FMODE_READ) {
2029 if (!dmabuf->ready && (val = prog_dmabuf(state, 1)))
2030 return val;
2031 }
2032 #ifdef DEBUG
2033 printk("SNDCTL_DSP_GETBLKSIZE %d\n", dmabuf->userfragsize);
2034 #endif
2035 return put_user(dmabuf->userfragsize, p);
2036
2037 case SNDCTL_DSP_GETFMTS: /* Returns a mask of supported sample format*/
2038 #ifdef DEBUG
2039 printk("SNDCTL_DSP_GETFMTS\n");
2040 #endif
2041 return put_user(AFMT_S16_LE, p);
2042
2043 case SNDCTL_DSP_SETFMT: /* Select sample format */
2044 #ifdef DEBUG
2045 printk("SNDCTL_DSP_SETFMT\n");
2046 #endif
2047 return put_user(AFMT_S16_LE, p);
2048
2049 case SNDCTL_DSP_CHANNELS:
2050 #ifdef DEBUG
2051 printk("SNDCTL_DSP_CHANNELS\n");
2052 #endif
2053 if (get_user(val, p))
2054 return -EFAULT;
2055
2056 if (val > 0) {
2057 if (dmabuf->enable & DAC_RUNNING) {
2058 stop_dac(state);
2059 }
2060 if (dmabuf->enable & ADC_RUNNING) {
2061 stop_adc(state);
2062 }
2063 } else {
2064 return put_user(state->card->channels, p);
2065 }
2066
2067 /* ICH and ICH0 only support 2 channels */
2068 if ( state->card->pci_id == PCI_DEVICE_ID_INTEL_82801AA_5
2069 || state->card->pci_id == PCI_DEVICE_ID_INTEL_82801AB_5)
2070 return put_user(2, p);
2071
2072 /* Multi-channel support was added with ICH2. Bits in */
2073 /* Global Status and Global Control register are now */
2074 /* used to indicate this. */
2075
2076 i_glob_cnt = I810_IOREADL(state->card, GLOB_CNT);
2077
2078 /* Current # of channels enabled */
2079 if ( i_glob_cnt & 0x0100000 )
2080 ret = 4;
2081 else if ( i_glob_cnt & 0x0200000 )
2082 ret = 6;
2083 else
2084 ret = 2;
2085
2086 switch ( val ) {
2087 case 2: /* 2 channels is always supported */
2088 I810_IOWRITEL(i_glob_cnt & 0xffcfffff,
2089 state->card, GLOB_CNT);
2090 /* Do we need to change mixer settings???? */
2091 break;
2092 case 4: /* Supported on some chipsets, better check first */
2093 if ( state->card->channels >= 4 ) {
2094 I810_IOWRITEL((i_glob_cnt & 0xffcfffff) | 0x100000,
2095 state->card, GLOB_CNT);
2096 /* Do we need to change mixer settings??? */
2097 } else {
2098 val = ret;
2099 }
2100 break;
2101 case 6: /* Supported on some chipsets, better check first */
2102 if ( state->card->channels >= 6 ) {
2103 I810_IOWRITEL((i_glob_cnt & 0xffcfffff) | 0x200000,
2104 state->card, GLOB_CNT);
2105 /* Do we need to change mixer settings??? */
2106 } else {
2107 val = ret;
2108 }
2109 break;
2110 default: /* nothing else is ever supported by the chipset */
2111 val = ret;
2112 break;
2113 }
2114
2115 return put_user(val, p);
2116
2117 case SNDCTL_DSP_POST: /* the user has sent all data and is notifying us */
2118 /* we update the swptr to the end of the last sg segment then return */
2119 #ifdef DEBUG
2120 printk("SNDCTL_DSP_POST\n");
2121 #endif
2122 if(!dmabuf->ready || (dmabuf->enable != DAC_RUNNING))
2123 return 0;
2124 if((dmabuf->swptr % dmabuf->fragsize) != 0) {
2125 val = dmabuf->fragsize - (dmabuf->swptr % dmabuf->fragsize);
2126 dmabuf->swptr += val;
2127 dmabuf->count += val;
2128 }
2129 return 0;
2130
2131 case SNDCTL_DSP_SUBDIVIDE:
2132 if (dmabuf->subdivision)
2133 return -EINVAL;
2134 if (get_user(val, p))
2135 return -EFAULT;
2136 if (val != 1 && val != 2 && val != 4)
2137 return -EINVAL;
2138 #ifdef DEBUG
2139 printk("SNDCTL_DSP_SUBDIVIDE %d\n", val);
2140 #endif
2141 dmabuf->subdivision = val;
2142 dmabuf->ready = 0;
2143 return 0;
2144
2145 case SNDCTL_DSP_SETFRAGMENT:
2146 if (get_user(val, p))
2147 return -EFAULT;
2148
2149 dmabuf->ossfragsize = 1<<(val & 0xffff);
2150 dmabuf->ossmaxfrags = (val >> 16) & 0xffff;
2151 if (!dmabuf->ossfragsize || !dmabuf->ossmaxfrags)
2152 return -EINVAL;
2153 /*
2154 * Bound the frag size into our allowed range of 256 - 4096
2155 */
2156 if (dmabuf->ossfragsize < 256)
2157 dmabuf->ossfragsize = 256;
2158 else if (dmabuf->ossfragsize > 4096)
2159 dmabuf->ossfragsize = 4096;
2160 /*
2161 * The numfrags could be something reasonable, or it could
2162 * be 0xffff meaning "Give me as much as possible". So,
2163 * we check the numfrags * fragsize doesn't exceed our
2164 * 64k buffer limit, nor is it less than our 8k minimum.
2165 * If it fails either one of these checks, then adjust the
2166 * number of fragments, not the size of them. It's OK if
2167 * our number of fragments doesn't equal 32 or anything
2168 * like our hardware based number now since we are using
2169 * a different frag count for the hardware. Before we get
2170 * into this though, bound the maxfrags to avoid overflow
2171 * issues. A reasonable bound would be 64k / 256 since our
2172 * maximum buffer size is 64k and our minimum frag size is
2173 * 256. On the other end, our minimum buffer size is 8k and
2174 * our maximum frag size is 4k, so the lower bound should
2175 * be 2.
2176 */
2177
2178 if(dmabuf->ossmaxfrags > 256)
2179 dmabuf->ossmaxfrags = 256;
2180 else if (dmabuf->ossmaxfrags < 2)
2181 dmabuf->ossmaxfrags = 2;
2182
2183 val = dmabuf->ossfragsize * dmabuf->ossmaxfrags;
2184 while (val < 8192) {
2185 val <<= 1;
2186 dmabuf->ossmaxfrags <<= 1;
2187 }
2188 while (val > 65536) {
2189 val >>= 1;
2190 dmabuf->ossmaxfrags >>= 1;
2191 }
2192 dmabuf->ready = 0;
2193 #ifdef DEBUG
2194 printk("SNDCTL_DSP_SETFRAGMENT 0x%x, %d, %d\n", val,
2195 dmabuf->ossfragsize, dmabuf->ossmaxfrags);
2196 #endif
2197
2198 return 0;
2199
2200 case SNDCTL_DSP_GETOSPACE:
2201 if (!(file->f_mode & FMODE_WRITE))
2202 return -EINVAL;
2203 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2204 return val;
2205 spin_lock_irqsave(&state->card->lock, flags);
2206 i810_update_ptr(state);
2207 abinfo.fragsize = dmabuf->userfragsize;
2208 abinfo.fragstotal = dmabuf->userfrags;
2209 if (dmabuf->mapped)
2210 abinfo.bytes = dmabuf->dmasize;
2211 else
2212 abinfo.bytes = i810_get_free_write_space(state);
2213 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize;
2214 spin_unlock_irqrestore(&state->card->lock, flags);
2215 #if defined(DEBUG) || defined(DEBUG_MMAP)
2216 printk("SNDCTL_DSP_GETOSPACE %d, %d, %d, %d\n", abinfo.bytes,
2217 abinfo.fragsize, abinfo.fragments, abinfo.fragstotal);
2218 #endif
2219 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2220
2221 case SNDCTL_DSP_GETOPTR:
2222 if (!(file->f_mode & FMODE_WRITE))
2223 return -EINVAL;
2224 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2225 return val;
2226 spin_lock_irqsave(&state->card->lock, flags);
2227 val = i810_get_free_write_space(state);
2228 cinfo.bytes = dmabuf->total_bytes;
2229 cinfo.ptr = dmabuf->hwptr;
2230 cinfo.blocks = val/dmabuf->userfragsize;
2231 if (dmabuf->mapped && (dmabuf->trigger & PCM_ENABLE_OUTPUT)) {
2232 dmabuf->count += val;
2233 dmabuf->swptr = (dmabuf->swptr + val) % dmabuf->dmasize;
2234 __i810_update_lvi(state, 0);
2235 }
2236 spin_unlock_irqrestore(&state->card->lock, flags);
2237 #if defined(DEBUG) || defined(DEBUG_MMAP)
2238 printk("SNDCTL_DSP_GETOPTR %d, %d, %d, %d\n", cinfo.bytes,
2239 cinfo.blocks, cinfo.ptr, dmabuf->count);
2240 #endif
2241 return copy_to_user(argp, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2242
2243 case SNDCTL_DSP_GETISPACE:
2244 if (!(file->f_mode & FMODE_READ))
2245 return -EINVAL;
2246 if (!dmabuf->ready && (val = prog_dmabuf(state, 1)) != 0)
2247 return val;
2248 spin_lock_irqsave(&state->card->lock, flags);
2249 abinfo.bytes = i810_get_available_read_data(state);
2250 abinfo.fragsize = dmabuf->userfragsize;
2251 abinfo.fragstotal = dmabuf->userfrags;
2252 abinfo.fragments = abinfo.bytes / dmabuf->userfragsize;
2253 spin_unlock_irqrestore(&state->card->lock, flags);
2254 #if defined(DEBUG) || defined(DEBUG_MMAP)
2255 printk("SNDCTL_DSP_GETISPACE %d, %d, %d, %d\n", abinfo.bytes,
2256 abinfo.fragsize, abinfo.fragments, abinfo.fragstotal);
2257 #endif
2258 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2259
2260 case SNDCTL_DSP_GETIPTR:
2261 if (!(file->f_mode & FMODE_READ))
2262 return -EINVAL;
2263 if (!dmabuf->ready && (val = prog_dmabuf(state, 0)) != 0)
2264 return val;
2265 spin_lock_irqsave(&state->card->lock, flags);
2266 val = i810_get_available_read_data(state);
2267 cinfo.bytes = dmabuf->total_bytes;
2268 cinfo.blocks = val/dmabuf->userfragsize;
2269 cinfo.ptr = dmabuf->hwptr;
2270 if (dmabuf->mapped && (dmabuf->trigger & PCM_ENABLE_INPUT)) {
2271 dmabuf->count -= val;
2272 dmabuf->swptr = (dmabuf->swptr + val) % dmabuf->dmasize;
2273 __i810_update_lvi(state, 1);
2274 }
2275 spin_unlock_irqrestore(&state->card->lock, flags);
2276 #if defined(DEBUG) || defined(DEBUG_MMAP)
2277 printk("SNDCTL_DSP_GETIPTR %d, %d, %d, %d\n", cinfo.bytes,
2278 cinfo.blocks, cinfo.ptr, dmabuf->count);
2279 #endif
2280 return copy_to_user(argp, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2281
2282 case SNDCTL_DSP_NONBLOCK:
2283 #ifdef DEBUG
2284 printk("SNDCTL_DSP_NONBLOCK\n");
2285 #endif
2286 file->f_flags |= O_NONBLOCK;
2287 return 0;
2288
2289 case SNDCTL_DSP_GETCAPS:
2290 #ifdef DEBUG
2291 printk("SNDCTL_DSP_GETCAPS\n");
2292 #endif
2293 return put_user(DSP_CAP_REALTIME|DSP_CAP_TRIGGER|DSP_CAP_MMAP|DSP_CAP_BIND,
2294 p);
2295
2296 case SNDCTL_DSP_GETTRIGGER:
2297 val = 0;
2298 #ifdef DEBUG
2299 printk("SNDCTL_DSP_GETTRIGGER 0x%x\n", dmabuf->trigger);
2300 #endif
2301 return put_user(dmabuf->trigger, p);
2302
2303 case SNDCTL_DSP_SETTRIGGER:
2304 if (get_user(val, p))
2305 return -EFAULT;
2306 #if defined(DEBUG) || defined(DEBUG_MMAP)
2307 printk("SNDCTL_DSP_SETTRIGGER 0x%x\n", val);
2308 #endif
2309 /* silently ignore invalid PCM_ENABLE_xxx bits,
2310 * like the other drivers do
2311 */
2312 if (!(file->f_mode & FMODE_READ ))
2313 val &= ~PCM_ENABLE_INPUT;
2314 if (!(file->f_mode & FMODE_WRITE ))
2315 val &= ~PCM_ENABLE_OUTPUT;
2316 if((file->f_mode & FMODE_READ) && !(val & PCM_ENABLE_INPUT) && dmabuf->enable == ADC_RUNNING) {
2317 stop_adc(state);
2318 }
2319 if((file->f_mode & FMODE_WRITE) && !(val & PCM_ENABLE_OUTPUT) && dmabuf->enable == DAC_RUNNING) {
2320 stop_dac(state);
2321 }
2322 dmabuf->trigger = val;
2323 if((val & PCM_ENABLE_OUTPUT) && !(dmabuf->enable & DAC_RUNNING)) {
2324 if (!dmabuf->write_channel) {
2325 dmabuf->ready = 0;
2326 dmabuf->write_channel = state->card->alloc_pcm_channel(state->card);
2327 if (!dmabuf->write_channel)
2328 return -EBUSY;
2329 }
2330 if (!dmabuf->ready && (ret = prog_dmabuf(state, 0)))
2331 return ret;
2332 if (dmabuf->mapped) {
2333 spin_lock_irqsave(&state->card->lock, flags);
2334 i810_update_ptr(state);
2335 dmabuf->count = 0;
2336 dmabuf->swptr = dmabuf->hwptr;
2337 dmabuf->count = i810_get_free_write_space(state);
2338 dmabuf->swptr = (dmabuf->swptr + dmabuf->count) % dmabuf->dmasize;
2339 spin_unlock_irqrestore(&state->card->lock, flags);
2340 }
2341 i810_update_lvi(state, 0);
2342 start_dac(state);
2343 }
2344 if((val & PCM_ENABLE_INPUT) && !(dmabuf->enable & ADC_RUNNING)) {
2345 if (!dmabuf->read_channel) {
2346 dmabuf->ready = 0;
2347 dmabuf->read_channel = state->card->alloc_rec_pcm_channel(state->card);
2348 if (!dmabuf->read_channel)
2349 return -EBUSY;
2350 }
2351 if (!dmabuf->ready && (ret = prog_dmabuf(state, 1)))
2352 return ret;
2353 if (dmabuf->mapped) {
2354 spin_lock_irqsave(&state->card->lock, flags);
2355 i810_update_ptr(state);
2356 dmabuf->swptr = dmabuf->hwptr;
2357 dmabuf->count = 0;
2358 spin_unlock_irqrestore(&state->card->lock, flags);
2359 }
2360 i810_update_lvi(state, 1);
2361 start_adc(state);
2362 }
2363 return 0;
2364
2365 case SNDCTL_DSP_SETDUPLEX:
2366 #ifdef DEBUG
2367 printk("SNDCTL_DSP_SETDUPLEX\n");
2368 #endif
2369 return -EINVAL;
2370
2371 case SNDCTL_DSP_GETODELAY:
2372 if (!(file->f_mode & FMODE_WRITE))
2373 return -EINVAL;
2374 spin_lock_irqsave(&state->card->lock, flags);
2375 i810_update_ptr(state);
2376 val = dmabuf->count;
2377 spin_unlock_irqrestore(&state->card->lock, flags);
2378 #ifdef DEBUG
2379 printk("SNDCTL_DSP_GETODELAY %d\n", dmabuf->count);
2380 #endif
2381 return put_user(val, p);
2382
2383 case SOUND_PCM_READ_RATE:
2384 #ifdef DEBUG
2385 printk("SOUND_PCM_READ_RATE %d\n", dmabuf->rate);
2386 #endif
2387 return put_user(dmabuf->rate, p);
2388
2389 case SOUND_PCM_READ_CHANNELS:
2390 #ifdef DEBUG
2391 printk("SOUND_PCM_READ_CHANNELS\n");
2392 #endif
2393 return put_user(2, p);
2394
2395 case SOUND_PCM_READ_BITS:
2396 #ifdef DEBUG
2397 printk("SOUND_PCM_READ_BITS\n");
2398 #endif
2399 return put_user(AFMT_S16_LE, p);
2400
2401 case SNDCTL_DSP_SETSPDIF: /* Set S/PDIF Control register */
2402 #ifdef DEBUG
2403 printk("SNDCTL_DSP_SETSPDIF\n");
2404 #endif
2405 if (get_user(val, p))
2406 return -EFAULT;
2407
2408 /* Check to make sure the codec supports S/PDIF transmitter */
2409
2410 if((state->card->ac97_features & 4)) {
2411 /* mask out the transmitter speed bits so the user can't set them */
2412 val &= ~0x3000;
2413
2414 /* Add the current transmitter speed bits to the passed value */
2415 ret = i810_ac97_get(codec, AC97_SPDIF_CONTROL);
2416 val |= (ret & 0x3000);
2417
2418 i810_ac97_set(codec, AC97_SPDIF_CONTROL, val);
2419 if(i810_ac97_get(codec, AC97_SPDIF_CONTROL) != val ) {
2420 printk(KERN_ERR "i810_audio: Unable to set S/PDIF configuration to 0x%04x.\n", val);
2421 return -EFAULT;
2422 }
2423 }
2424 #ifdef DEBUG
2425 else
2426 printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
2427 #endif
2428 return put_user(val, p);
2429
2430 case SNDCTL_DSP_GETSPDIF: /* Get S/PDIF Control register */
2431 #ifdef DEBUG
2432 printk("SNDCTL_DSP_GETSPDIF\n");
2433 #endif
2434 if (get_user(val, p))
2435 return -EFAULT;
2436
2437 /* Check to make sure the codec supports S/PDIF transmitter */
2438
2439 if(!(state->card->ac97_features & 4)) {
2440 #ifdef DEBUG
2441 printk(KERN_WARNING "i810_audio: S/PDIF transmitter not avalible.\n");
2442 #endif
2443 val = 0;
2444 } else {
2445 val = i810_ac97_get(codec, AC97_SPDIF_CONTROL);
2446 }
2447 //return put_user((val & 0xcfff), p);
2448 return put_user(val, p);
2449
2450 case SNDCTL_DSP_GETCHANNELMASK:
2451 #ifdef DEBUG
2452 printk("SNDCTL_DSP_GETCHANNELMASK\n");
2453 #endif
2454 if (get_user(val, p))
2455 return -EFAULT;
2456
2457 /* Based on AC'97 DAC support, not ICH hardware */
2458 val = DSP_BIND_FRONT;
2459 if ( state->card->ac97_features & 0x0004 )
2460 val |= DSP_BIND_SPDIF;
2461
2462 if ( state->card->ac97_features & 0x0080 )
2463 val |= DSP_BIND_SURR;
2464 if ( state->card->ac97_features & 0x0140 )
2465 val |= DSP_BIND_CENTER_LFE;
2466
2467 return put_user(val, p);
2468
2469 case SNDCTL_DSP_BIND_CHANNEL:
2470 #ifdef DEBUG
2471 printk("SNDCTL_DSP_BIND_CHANNEL\n");
2472 #endif
2473 if (get_user(val, p))
2474 return -EFAULT;
2475 if ( val == DSP_BIND_QUERY ) {
2476 val = DSP_BIND_FRONT; /* Always report this as being enabled */
2477 if ( state->card->ac97_status & SPDIF_ON )
2478 val |= DSP_BIND_SPDIF;
2479 else {
2480 if ( state->card->ac97_status & SURR_ON )
2481 val |= DSP_BIND_SURR;
2482 if ( state->card->ac97_status & CENTER_LFE_ON )
2483 val |= DSP_BIND_CENTER_LFE;
2484 }
2485 } else { /* Not a query, set it */
2486 if (!(file->f_mode & FMODE_WRITE))
2487 return -EINVAL;
2488 if ( dmabuf->enable == DAC_RUNNING ) {
2489 stop_dac(state);
2490 }
2491 if ( val & DSP_BIND_SPDIF ) { /* Turn on SPDIF */
2492 /* Ok, this should probably define what slots
2493 * to use. For now, we'll only set it to the
2494 * defaults:
2495 *
2496 * non multichannel codec maps to slots 3&4
2497 * 2 channel codec maps to slots 7&8
2498 * 4 channel codec maps to slots 6&9
2499 * 6 channel codec maps to slots 10&11
2500 *
2501 * there should be some way for the app to
2502 * select the slot assignment.
2503 */
2504
2505 i810_set_spdif_output ( state, AC97_EA_SPSA_3_4, dmabuf->rate );
2506 if ( !(state->card->ac97_status & SPDIF_ON) )
2507 val &= ~DSP_BIND_SPDIF;
2508 } else {
2509 int mask;
2510 int channels;
2511
2512 /* Turn off S/PDIF if it was on */
2513 if ( state->card->ac97_status & SPDIF_ON )
2514 i810_set_spdif_output ( state, -1, 0 );
2515
2516 mask = val & (DSP_BIND_FRONT | DSP_BIND_SURR | DSP_BIND_CENTER_LFE);
2517 switch (mask) {
2518 case DSP_BIND_FRONT:
2519 channels = 2;
2520 break;
2521 case DSP_BIND_FRONT|DSP_BIND_SURR:
2522 channels = 4;
2523 break;
2524 case DSP_BIND_FRONT|DSP_BIND_SURR|DSP_BIND_CENTER_LFE:
2525 channels = 6;
2526 break;
2527 default:
2528 val = DSP_BIND_FRONT;
2529 channels = 2;
2530 break;
2531 }
2532 i810_set_dac_channels ( state, channels );
2533
2534 /* check that they really got turned on */
2535 if (!(state->card->ac97_status & SURR_ON))
2536 val &= ~DSP_BIND_SURR;
2537 if (!(state->card->ac97_status & CENTER_LFE_ON))
2538 val &= ~DSP_BIND_CENTER_LFE;
2539 }
2540 }
2541 return put_user(val, p);
2542
2543 case SNDCTL_DSP_MAPINBUF:
2544 case SNDCTL_DSP_MAPOUTBUF:
2545 case SNDCTL_DSP_SETSYNCRO:
2546 case SOUND_PCM_WRITE_FILTER:
2547 case SOUND_PCM_READ_FILTER:
2548 #ifdef DEBUG
2549 printk("SNDCTL_* -EINVAL\n");
2550 #endif
2551 return -EINVAL;
2552 }
2553 return -EINVAL;
2554 }
2555
2556 static int i810_open(struct inode *inode, struct file *file)
2557 {
2558 int i = 0;
2559 struct i810_card *card = devs;
2560 struct i810_state *state = NULL;
2561 struct dmabuf *dmabuf = NULL;
2562
2563 /* find an avaiable virtual channel (instance of /dev/dsp) */
2564 while (card != NULL) {
2565 /*
2566 * If we are initializing and then fail, card could go
2567 * away unuexpectedly while we are in the for() loop.
2568 * So, check for card on each iteration before we check
2569 * for card->initializing to avoid a possible oops.
2570 * This usually only matters for times when the driver is
2571 * autoloaded by kmod.
2572 */
2573 for (i = 0; i < 50 && card && card->initializing; i++) {
2574 set_current_state(TASK_UNINTERRUPTIBLE);
2575 schedule_timeout(HZ/20);
2576 }
2577 for (i = 0; i < NR_HW_CH && card && !card->initializing; i++) {
2578 if (card->states[i] == NULL) {
2579 state = card->states[i] = (struct i810_state *)
2580 kmalloc(sizeof(struct i810_state), GFP_KERNEL);
2581 if (state == NULL)
2582 return -ENOMEM;
2583 memset(state, 0, sizeof(struct i810_state));
2584 dmabuf = &state->dmabuf;
2585 goto found_virt;
2586 }
2587 }
2588 card = card->next;
2589 }
2590 /* no more virtual channel avaiable */
2591 if (!state)
2592 return -ENODEV;
2593
2594 found_virt:
2595 /* initialize the virtual channel */
2596 state->virt = i;
2597 state->card = card;
2598 state->magic = I810_STATE_MAGIC;
2599 init_waitqueue_head(&dmabuf->wait);
2600 init_MUTEX(&state->open_sem);
2601 file->private_data = state;
2602 dmabuf->trigger = 0;
2603
2604 /* allocate hardware channels */
2605 if(file->f_mode & FMODE_READ) {
2606 if((dmabuf->read_channel = card->alloc_rec_pcm_channel(card)) == NULL) {
2607 kfree (card->states[i]);
2608 card->states[i] = NULL;
2609 return -EBUSY;
2610 }
2611 dmabuf->trigger |= PCM_ENABLE_INPUT;
2612 i810_set_adc_rate(state, 8000);
2613 }
2614 if(file->f_mode & FMODE_WRITE) {
2615 if((dmabuf->write_channel = card->alloc_pcm_channel(card)) == NULL) {
2616 /* make sure we free the record channel allocated above */
2617 if(file->f_mode & FMODE_READ)
2618 card->free_pcm_channel(card,dmabuf->read_channel->num);
2619 kfree (card->states[i]);
2620 card->states[i] = NULL;
2621 return -EBUSY;
2622 }
2623 /* Initialize to 8kHz? What if we don't support 8kHz? */
2624 /* Let's change this to check for S/PDIF stuff */
2625
2626 dmabuf->trigger |= PCM_ENABLE_OUTPUT;
2627 if ( spdif_locked ) {
2628 i810_set_dac_rate(state, spdif_locked);
2629 i810_set_spdif_output(state, AC97_EA_SPSA_3_4, spdif_locked);
2630 } else {
2631 i810_set_dac_rate(state, 8000);
2632 /* Put the ACLink in 2 channel mode by default */
2633 i = I810_IOREADL(card, GLOB_CNT);
2634 I810_IOWRITEL(i & 0xffcfffff, card, GLOB_CNT);
2635 }
2636 }
2637
2638 /* set default sample format. According to OSS Programmer's Guide /dev/dsp
2639 should be default to unsigned 8-bits, mono, with sample rate 8kHz and
2640 /dev/dspW will accept 16-bits sample, but we don't support those so we
2641 set it immediately to stereo and 16bit, which is all we do support */
2642 dmabuf->fmt |= I810_FMT_16BIT | I810_FMT_STEREO;
2643 dmabuf->ossfragsize = 0;
2644 dmabuf->ossmaxfrags = 0;
2645 dmabuf->subdivision = 0;
2646
2647 state->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2648
2649 return nonseekable_open(inode, file);
2650 }
2651
2652 static int i810_release(struct inode *inode, struct file *file)
2653 {
2654 struct i810_state *state = (struct i810_state *)file->private_data;
2655 struct i810_card *card = state->card;
2656 struct dmabuf *dmabuf = &state->dmabuf;
2657 unsigned long flags;
2658
2659 lock_kernel();
2660
2661 /* stop DMA state machine and free DMA buffers/channels */
2662 if(dmabuf->trigger & PCM_ENABLE_OUTPUT) {
2663 drain_dac(state, 0);
2664 }
2665 if(dmabuf->trigger & PCM_ENABLE_INPUT) {
2666 stop_adc(state);
2667 }
2668 spin_lock_irqsave(&card->lock, flags);
2669 dealloc_dmabuf(state);
2670 if (file->f_mode & FMODE_WRITE) {
2671 state->card->free_pcm_channel(state->card, dmabuf->write_channel->num);
2672 }
2673 if (file->f_mode & FMODE_READ) {
2674 state->card->free_pcm_channel(state->card, dmabuf->read_channel->num);
2675 }
2676
2677 state->card->states[state->virt] = NULL;
2678 kfree(state);
2679 spin_unlock_irqrestore(&card->lock, flags);
2680 unlock_kernel();
2681
2682 return 0;
2683 }
2684
2685 static /*const*/ struct file_operations i810_audio_fops = {
2686 .owner = THIS_MODULE,
2687 .llseek = no_llseek,
2688 .read = i810_read,
2689 .write = i810_write,
2690 .poll = i810_poll,
2691 .ioctl = i810_ioctl,
2692 .mmap = i810_mmap,
2693 .open = i810_open,
2694 .release = i810_release,
2695 };
2696
2697 /* Write AC97 codec registers */
2698
2699 static u16 i810_ac97_get_mmio(struct ac97_codec *dev, u8 reg)
2700 {
2701 struct i810_card *card = dev->private_data;
2702 int count = 100;
2703 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2704
2705 while(count-- && (readb(card->iobase_mmio + CAS) & 1))
2706 udelay(1);
2707
2708 #ifdef DEBUG_MMIO
2709 {
2710 u16 ans = readw(card->ac97base_mmio + reg_set);
2711 printk(KERN_DEBUG "i810_audio: ac97_get_mmio(%d) -> 0x%04X\n", ((int) reg_set) & 0xffff, (u32) ans);
2712 return ans;
2713 }
2714 #else
2715 return readw(card->ac97base_mmio + reg_set);
2716 #endif
2717 }
2718
2719 static u16 i810_ac97_get_io(struct ac97_codec *dev, u8 reg)
2720 {
2721 struct i810_card *card = dev->private_data;
2722 int count = 100;
2723 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2724
2725 while(count-- && (I810_IOREADB(card, CAS) & 1))
2726 udelay(1);
2727
2728 return inw(card->ac97base + reg_set);
2729 }
2730
2731 static void i810_ac97_set_mmio(struct ac97_codec *dev, u8 reg, u16 data)
2732 {
2733 struct i810_card *card = dev->private_data;
2734 int count = 100;
2735 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2736
2737 while(count-- && (readb(card->iobase_mmio + CAS) & 1))
2738 udelay(1);
2739
2740 writew(data, card->ac97base_mmio + reg_set);
2741
2742 #ifdef DEBUG_MMIO
2743 printk(KERN_DEBUG "i810_audio: ac97_set_mmio(0x%04X, %d)\n", (u32) data, ((int) reg_set) & 0xffff);
2744 #endif
2745 }
2746
2747 static void i810_ac97_set_io(struct ac97_codec *dev, u8 reg, u16 data)
2748 {
2749 struct i810_card *card = dev->private_data;
2750 int count = 100;
2751 u16 reg_set = IO_REG_OFF(dev) | (reg&0x7f);
2752
2753 while(count-- && (I810_IOREADB(card, CAS) & 1))
2754 udelay(1);
2755
2756 outw(data, card->ac97base + reg_set);
2757 }
2758
2759 static u16 i810_ac97_get(struct ac97_codec *dev, u8 reg)
2760 {
2761 struct i810_card *card = dev->private_data;
2762 u16 ret;
2763
2764 spin_lock(&card->ac97_lock);
2765 if (card->use_mmio) {
2766 ret = i810_ac97_get_mmio(dev, reg);
2767 }
2768 else {
2769 ret = i810_ac97_get_io(dev, reg);
2770 }
2771 spin_unlock(&card->ac97_lock);
2772
2773 return ret;
2774 }
2775
2776 static void i810_ac97_set(struct ac97_codec *dev, u8 reg, u16 data)
2777 {
2778 struct i810_card *card = dev->private_data;
2779
2780 spin_lock(&card->ac97_lock);
2781 if (card->use_mmio) {
2782 i810_ac97_set_mmio(dev, reg, data);
2783 }
2784 else {
2785 i810_ac97_set_io(dev, reg, data);
2786 }
2787 spin_unlock(&card->ac97_lock);
2788 }
2789
2790
2791 /* OSS /dev/mixer file operation methods */
2792
2793 static int i810_open_mixdev(struct inode *inode, struct file *file)
2794 {
2795 int i;
2796 int minor = iminor(inode);
2797 struct i810_card *card = devs;
2798
2799 for (card = devs; card != NULL; card = card->next) {
2800 /*
2801 * If we are initializing and then fail, card could go
2802 * away unuexpectedly while we are in the for() loop.
2803 * So, check for card on each iteration before we check
2804 * for card->initializing to avoid a possible oops.
2805 * This usually only matters for times when the driver is
2806 * autoloaded by kmod.
2807 */
2808 for (i = 0; i < 50 && card && card->initializing; i++) {
2809 set_current_state(TASK_UNINTERRUPTIBLE);
2810 schedule_timeout(HZ/20);
2811 }
2812 for (i = 0; i < NR_AC97 && card && !card->initializing; i++)
2813 if (card->ac97_codec[i] != NULL &&
2814 card->ac97_codec[i]->dev_mixer == minor) {
2815 file->private_data = card->ac97_codec[i];
2816 return nonseekable_open(inode, file);
2817 }
2818 }
2819 return -ENODEV;
2820 }
2821
2822 static int i810_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd,
2823 unsigned long arg)
2824 {
2825 struct ac97_codec *codec = (struct ac97_codec *)file->private_data;
2826
2827 return codec->mixer_ioctl(codec, cmd, arg);
2828 }
2829
2830 static /*const*/ struct file_operations i810_mixer_fops = {
2831 .owner = THIS_MODULE,
2832 .llseek = no_llseek,
2833 .ioctl = i810_ioctl_mixdev,
2834 .open = i810_open_mixdev,
2835 };
2836
2837 /* AC97 codec initialisation. These small functions exist so we don't
2838 duplicate code between module init and apm resume */
2839
2840 static inline int i810_ac97_exists(struct i810_card *card, int ac97_number)
2841 {
2842 u32 reg = I810_IOREADL(card, GLOB_STA);
2843 switch (ac97_number) {
2844 case 0:
2845 return reg & (1<<8);
2846 case 1:
2847 return reg & (1<<9);
2848 case 2:
2849 return reg & (1<<28);
2850 }
2851 return 0;
2852 }
2853
2854 static inline int i810_ac97_enable_variable_rate(struct ac97_codec *codec)
2855 {
2856 i810_ac97_set(codec, AC97_EXTENDED_STATUS, 9);
2857 i810_ac97_set(codec,AC97_EXTENDED_STATUS,
2858 i810_ac97_get(codec, AC97_EXTENDED_STATUS)|0xE800);
2859
2860 return (i810_ac97_get(codec, AC97_EXTENDED_STATUS)&1);
2861 }
2862
2863
2864 static int i810_ac97_probe_and_powerup(struct i810_card *card,struct ac97_codec *codec)
2865 {
2866 /* Returns 0 on failure */
2867 int i;
2868
2869 if (ac97_probe_codec(codec) == 0) return 0;
2870
2871 /* power it all up */
2872 i810_ac97_set(codec, AC97_POWER_CONTROL,
2873 i810_ac97_get(codec, AC97_POWER_CONTROL) & ~0x7f00);
2874
2875 /* wait for analog ready */
2876 for (i=100; i && ((i810_ac97_get(codec, AC97_POWER_CONTROL) & 0xf) != 0xf); i--)
2877 {
2878 set_current_state(TASK_UNINTERRUPTIBLE);
2879 schedule_timeout(HZ/20);
2880 }
2881 return i;
2882 }
2883
2884 static int is_new_ich(u16 pci_id)
2885 {
2886 switch (pci_id) {
2887 case PCI_DEVICE_ID_INTEL_82801DB_5:
2888 case PCI_DEVICE_ID_INTEL_82801EB_5:
2889 case PCI_DEVICE_ID_INTEL_ESB_5:
2890 case PCI_DEVICE_ID_INTEL_ICH6_18:
2891 return 1;
2892 default:
2893 break;
2894 }
2895
2896 return 0;
2897 }
2898
2899 static inline int ich_use_mmio(struct i810_card *card)
2900 {
2901 return is_new_ich(card->pci_id) && card->use_mmio;
2902 }
2903
2904 /**
2905 * i810_ac97_power_up_bus - bring up AC97 link
2906 * @card : ICH audio device to power up
2907 *
2908 * Bring up the ACLink AC97 codec bus
2909 */
2910
2911 static int i810_ac97_power_up_bus(struct i810_card *card)
2912 {
2913 u32 reg = I810_IOREADL(card, GLOB_CNT);
2914 int i;
2915 int primary_codec_id = 0;
2916
2917 if((reg&2)==0) /* Cold required */
2918 reg|=2;
2919 else
2920 reg|=4; /* Warm */
2921
2922 reg&=~8; /* ACLink on */
2923
2924 /* At this point we deassert AC_RESET # */
2925 I810_IOWRITEL(reg , card, GLOB_CNT);
2926
2927 /* We must now allow time for the Codec initialisation.
2928 600mS is the specified time */
2929
2930 for(i=0;i<10;i++)
2931 {
2932 if((I810_IOREADL(card, GLOB_CNT)&4)==0)
2933 break;
2934
2935 set_current_state(TASK_UNINTERRUPTIBLE);
2936 schedule_timeout(HZ/20);
2937 }
2938 if(i==10)
2939 {
2940 printk(KERN_ERR "i810_audio: AC'97 reset failed.\n");
2941 return 0;
2942 }
2943
2944 set_current_state(TASK_UNINTERRUPTIBLE);
2945 schedule_timeout(HZ/2);
2946
2947 /*
2948 * See if the primary codec comes ready. This must happen
2949 * before we start doing DMA stuff
2950 */
2951 /* see i810_ac97_init for the next 10 lines (jsaw) */
2952 if (card->use_mmio)
2953 readw(card->ac97base_mmio);
2954 else
2955 inw(card->ac97base);
2956 if (ich_use_mmio(card)) {
2957 primary_codec_id = (int) readl(card->iobase_mmio + SDM) & 0x3;
2958 printk(KERN_INFO "i810_audio: Primary codec has ID %d\n",
2959 primary_codec_id);
2960 }
2961
2962 if(! i810_ac97_exists(card, primary_codec_id))
2963 {
2964 printk(KERN_INFO "i810_audio: Codec not ready.. wait.. ");
2965 set_current_state(TASK_UNINTERRUPTIBLE);
2966 schedule_timeout(HZ); /* actually 600mS by the spec */
2967
2968 if(i810_ac97_exists(card, primary_codec_id))
2969 printk("OK\n");
2970 else
2971 printk("no response.\n");
2972 }
2973 if (card->use_mmio)
2974 readw(card->ac97base_mmio);
2975 else
2976 inw(card->ac97base);
2977 return 1;
2978 }
2979
2980 static int __devinit i810_ac97_init(struct i810_card *card)
2981 {
2982 int num_ac97 = 0;
2983 int ac97_id;
2984 int total_channels = 0;
2985 int nr_ac97_max = card_cap[card->pci_id_internal].nr_ac97;
2986 struct ac97_codec *codec;
2987 u16 eid;
2988 u32 reg;
2989
2990 if(!i810_ac97_power_up_bus(card)) return 0;
2991
2992 /* Number of channels supported */
2993 /* What about the codec? Just because the ICH supports */
2994 /* multiple channels doesn't mean the codec does. */
2995 /* we'll have to modify this in the codec section below */
2996 /* to reflect what the codec has. */
2997 /* ICH and ICH0 only support 2 channels so don't bother */
2998 /* to check.... */
2999
3000 card->channels = 2;
3001 reg = I810_IOREADL(card, GLOB_STA);
3002 if ( reg & 0x0200000 )
3003 card->channels = 6;
3004 else if ( reg & 0x0100000 )
3005 card->channels = 4;
3006 printk(KERN_INFO "i810_audio: Audio Controller supports %d channels.\n", card->channels);
3007 printk(KERN_INFO "i810_audio: Defaulting to base 2 channel mode.\n");
3008 reg = I810_IOREADL(card, GLOB_CNT);
3009 I810_IOWRITEL(reg & 0xffcfffff, card, GLOB_CNT);
3010
3011 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++)
3012 card->ac97_codec[num_ac97] = NULL;
3013
3014 /*@FIXME I don't know, if I'm playing to safe here... (jsaw) */
3015 if ((nr_ac97_max > 2) && !card->use_mmio) nr_ac97_max = 2;
3016
3017 for (num_ac97 = 0; num_ac97 < nr_ac97_max; num_ac97++) {
3018 /* codec reset */
3019 printk(KERN_INFO "i810_audio: Resetting connection %d\n", num_ac97);
3020 if (card->use_mmio)
3021 readw(card->ac97base_mmio + 0x80*num_ac97);
3022 else
3023 inw(card->ac97base + 0x80*num_ac97);
3024
3025 /* If we have the SDATA_IN Map Register, as on ICH4, we
3026 do not loop thru all possible codec IDs but thru all
3027 possible IO channels. Bit 0:1 of SDM then holds the
3028 last codec ID spoken to.
3029 */
3030 if (ich_use_mmio(card)) {
3031 ac97_id = (int) readl(card->iobase_mmio + SDM) & 0x3;
3032 printk(KERN_INFO "i810_audio: Connection %d with codec id %d\n",
3033 num_ac97, ac97_id);
3034 }
3035 else {
3036 ac97_id = num_ac97;
3037 }
3038
3039 /* The ICH programmer's reference says you should */
3040 /* check the ready status before probing. So we chk */
3041 /* What do we do if it's not ready? Wait and try */
3042 /* again, or abort? */
3043 if (!i810_ac97_exists(card, ac97_id)) {
3044 if(num_ac97 == 0)
3045 printk(KERN_ERR "i810_audio: Primary codec not ready.\n");
3046 }
3047
3048 if ((codec = ac97_alloc_codec()) == NULL)
3049 return -ENOMEM;
3050
3051 /* initialize some basic codec information, other fields will be filled
3052 in ac97_probe_codec */
3053 codec->private_data = card;
3054 codec->id = ac97_id;
3055 card->ac97_id_map[ac97_id] = num_ac97 * 0x80;
3056
3057 if (card->use_mmio) {
3058 codec->codec_read = i810_ac97_get_mmio;
3059 codec->codec_write = i810_ac97_set_mmio;
3060 }
3061 else {
3062 codec->codec_read = i810_ac97_get_io;
3063 codec->codec_write = i810_ac97_set_io;
3064 }
3065
3066 if(!i810_ac97_probe_and_powerup(card,codec)) {
3067 printk(KERN_ERR "i810_audio: timed out waiting for codec %d analog ready.\n", ac97_id);
3068 ac97_release_codec(codec);
3069 break; /* it didn't work */
3070 }
3071 /* Store state information about S/PDIF transmitter */
3072 card->ac97_status = 0;
3073
3074 /* Don't attempt to get eid until powerup is complete */
3075 eid = i810_ac97_get(codec, AC97_EXTENDED_ID);
3076
3077 if(eid==0xFFFF)
3078 {
3079 printk(KERN_WARNING "i810_audio: no codec attached ?\n");
3080 ac97_release_codec(codec);
3081 break;
3082 }
3083
3084 /* Check for an AC97 1.0 soft modem (ID1) */
3085
3086 if(codec->modem)
3087 {
3088 printk(KERN_WARNING "i810_audio: codec %d is a softmodem - skipping.\n", ac97_id);
3089 ac97_release_codec(codec);
3090 continue;
3091 }
3092
3093 card->ac97_features = eid;
3094
3095 /* Now check the codec for useful features to make up for
3096 the dumbness of the 810 hardware engine */
3097
3098 if(!(eid&0x0001))
3099 printk(KERN_WARNING "i810_audio: only 48Khz playback available.\n");
3100 else
3101 {
3102 if(!i810_ac97_enable_variable_rate(codec)) {
3103 printk(KERN_WARNING "i810_audio: Codec refused to allow VRA, using 48Khz only.\n");
3104 card->ac97_features&=~1;
3105 }
3106 }
3107
3108 /* Turn on the amplifier */
3109
3110 codec->codec_write(codec, AC97_POWER_CONTROL,
3111 codec->codec_read(codec, AC97_POWER_CONTROL) & ~0x8000);
3112
3113 /* Determine how many channels the codec(s) support */
3114 /* - The primary codec always supports 2 */
3115 /* - If the codec supports AMAP, surround DACs will */
3116 /* automaticlly get assigned to slots. */
3117 /* * Check for surround DACs and increment if */
3118 /* found. */
3119 /* - Else check if the codec is revision 2.2 */
3120 /* * If surround DACs exist, assign them to slots */
3121 /* and increment channel count. */
3122
3123 /* All of this only applies to ICH2 and above. ICH */
3124 /* and ICH0 only support 2 channels. ICH2 will only */
3125 /* support multiple codecs in a "split audio" config. */
3126 /* as described above. */
3127
3128 /* TODO: Remove all the debugging messages! */
3129
3130 if((eid & 0xc000) == 0) /* primary codec */
3131 total_channels += 2;
3132
3133 if(eid & 0x200) { /* GOOD, AMAP support */
3134 if (eid & 0x0080) /* L/R Surround channels */
3135 total_channels += 2;
3136 if (eid & 0x0140) /* LFE and Center channels */
3137 total_channels += 2;
3138 printk("i810_audio: AC'97 codec %d supports AMAP, total channels = %d\n", ac97_id, total_channels);
3139 } else if (eid & 0x0400) { /* this only works on 2.2 compliant codecs */
3140 eid &= 0xffcf;
3141 if((eid & 0xc000) != 0) {
3142 switch ( total_channels ) {
3143 case 2:
3144 /* Set dsa1, dsa0 to 01 */
3145 eid |= 0x0010;
3146 break;
3147 case 4:
3148 /* Set dsa1, dsa0 to 10 */
3149 eid |= 0x0020;
3150 break;
3151 case 6:
3152 /* Set dsa1, dsa0 to 11 */
3153 eid |= 0x0030;
3154 break;
3155 }
3156 total_channels += 2;
3157 }
3158 i810_ac97_set(codec, AC97_EXTENDED_ID, eid);
3159 eid = i810_ac97_get(codec, AC97_EXTENDED_ID);
3160 printk("i810_audio: AC'97 codec %d, new EID value = 0x%04x\n", ac97_id, eid);
3161 if (eid & 0x0080) /* L/R Surround channels */
3162 total_channels += 2;
3163 if (eid & 0x0140) /* LFE and Center channels */
3164 total_channels += 2;
3165 printk("i810_audio: AC'97 codec %d, DAC map configured, total channels = %d\n", ac97_id, total_channels);
3166 } else {
3167 printk("i810_audio: AC'97 codec %d Unable to map surround DAC's (or DAC's not present), total channels = %d\n", ac97_id, total_channels);
3168 }
3169
3170 if ((codec->dev_mixer = register_sound_mixer(&i810_mixer_fops, -1)) < 0) {
3171 printk(KERN_ERR "i810_audio: couldn't register mixer!\n");
3172 ac97_release_codec(codec);
3173 break;
3174 }
3175
3176 card->ac97_codec[num_ac97] = codec;
3177 }
3178
3179 /* tune up the primary codec */
3180 ac97_tune_hardware(card->pci_dev, ac97_quirks, ac97_quirk);
3181
3182 /* pick the minimum of channels supported by ICHx or codec(s) */
3183 card->channels = (card->channels > total_channels)?total_channels:card->channels;
3184
3185 return num_ac97;
3186 }
3187
3188 static void __devinit i810_configure_clocking (void)
3189 {
3190 struct i810_card *card;
3191 struct i810_state *state;
3192 struct dmabuf *dmabuf;
3193 unsigned int i, offset, new_offset;
3194 unsigned long flags;
3195
3196 card = devs;
3197 /* We could try to set the clocking for multiple cards, but can you even have
3198 * more than one i810 in a machine? Besides, clocking is global, so unless
3199 * someone actually thinks more than one i810 in a machine is possible and
3200 * decides to rewrite that little bit, setting the rate for more than one card
3201 * is a waste of time.
3202 */
3203 if(card != NULL) {
3204 state = card->states[0] = (struct i810_state *)
3205 kmalloc(sizeof(struct i810_state), GFP_KERNEL);
3206 if (state == NULL)
3207 return;
3208 memset(state, 0, sizeof(struct i810_state));
3209 dmabuf = &state->dmabuf;
3210
3211 dmabuf->write_channel = card->alloc_pcm_channel(card);
3212 state->virt = 0;
3213 state->card = card;
3214 state->magic = I810_STATE_MAGIC;
3215 init_waitqueue_head(&dmabuf->wait);
3216 init_MUTEX(&state->open_sem);
3217 dmabuf->fmt = I810_FMT_STEREO | I810_FMT_16BIT;
3218 dmabuf->trigger = PCM_ENABLE_OUTPUT;
3219 i810_set_spdif_output(state, -1, 0);
3220 i810_set_dac_channels(state, 2);
3221 i810_set_dac_rate(state, 48000);
3222 if(prog_dmabuf(state, 0) != 0) {
3223 goto config_out_nodmabuf;
3224 }
3225 if(dmabuf->dmasize < 16384) {
3226 goto config_out;
3227 }
3228 dmabuf->count = dmabuf->dmasize;
3229 CIV_TO_LVI(card, dmabuf->write_channel->port, -1);
3230 local_irq_save(flags);
3231 start_dac(state);
3232 offset = i810_get_dma_addr(state, 0);
3233 mdelay(50);
3234 new_offset = i810_get_dma_addr(state, 0);
3235 stop_dac(state);
3236 local_irq_restore(flags);
3237 i = new_offset - offset;
3238 #ifdef DEBUG_INTERRUPTS
3239 printk("i810_audio: %d bytes in 50 milliseconds\n", i);
3240 #endif
3241 if(i == 0)
3242 goto config_out;
3243 i = i / 4 * 20;
3244 if (i > 48500 || i < 47500) {
3245 clocking = clocking * clocking / i;
3246 printk("i810_audio: setting clocking to %d\n", clocking);
3247 }
3248 config_out:
3249 dealloc_dmabuf(state);
3250 config_out_nodmabuf:
3251 state->card->free_pcm_channel(state->card,state->dmabuf.write_channel->num);
3252 kfree(state);
3253 card->states[0] = NULL;
3254 }
3255 }
3256
3257 /* install the driver, we do not allocate hardware channel nor DMA buffer now, they are defered
3258 until "ACCESS" time (in prog_dmabuf called by open/read/write/ioctl/mmap) */
3259
3260 static int __devinit i810_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_id)
3261 {
3262 struct i810_card *card;
3263
3264 if (pci_enable_device(pci_dev))
3265 return -EIO;
3266
3267 if (pci_set_dma_mask(pci_dev, I810_DMA_MASK)) {
3268 printk(KERN_ERR "i810_audio: architecture does not support"
3269 " 32bit PCI busmaster DMA\n");
3270 return -ENODEV;
3271 }
3272
3273 if ((card = kmalloc(sizeof(struct i810_card), GFP_KERNEL)) == NULL) {
3274 printk(KERN_ERR "i810_audio: out of memory\n");
3275 return -ENOMEM;
3276 }
3277 memset(card, 0, sizeof(*card));
3278
3279 card->initializing = 1;
3280 card->pci_dev = pci_dev;
3281 card->pci_id = pci_id->device;
3282 card->ac97base = pci_resource_start (pci_dev, 0);
3283 card->iobase = pci_resource_start (pci_dev, 1);
3284
3285 if (!(card->ac97base) || !(card->iobase)) {
3286 card->ac97base = 0;
3287 card->iobase = 0;
3288 }
3289
3290 /* if chipset could have mmio capability, check it */
3291 if (card_cap[pci_id->driver_data].flags & CAP_MMIO) {
3292 card->ac97base_mmio_phys = pci_resource_start (pci_dev, 2);
3293 card->iobase_mmio_phys = pci_resource_start (pci_dev, 3);
3294
3295 if ((card->ac97base_mmio_phys) && (card->iobase_mmio_phys)) {
3296 card->use_mmio = 1;
3297 }
3298 else {
3299 card->ac97base_mmio_phys = 0;
3300 card->iobase_mmio_phys = 0;
3301 }
3302 }
3303
3304 if (!(card->use_mmio) && (!(card->iobase) || !(card->ac97base))) {
3305 printk(KERN_ERR "i810_audio: No I/O resources available.\n");
3306 goto out_mem;
3307 }
3308
3309 card->irq = pci_dev->irq;
3310 card->next = devs;
3311 card->magic = I810_CARD_MAGIC;
3312 #ifdef CONFIG_PM
3313 card->pm_suspended=0;
3314 #endif
3315 spin_lock_init(&card->lock);
3316 spin_lock_init(&card->ac97_lock);
3317 devs = card;
3318
3319 pci_set_master(pci_dev);
3320
3321 printk(KERN_INFO "i810: %s found at IO 0x%04lx and 0x%04lx, "
3322 "MEM 0x%04lx and 0x%04lx, IRQ %d\n",
3323 card_names[pci_id->driver_data],
3324 card->iobase, card->ac97base,
3325 card->ac97base_mmio_phys, card->iobase_mmio_phys,
3326 card->irq);
3327
3328 card->alloc_pcm_channel = i810_alloc_pcm_channel;
3329 card->alloc_rec_pcm_channel = i810_alloc_rec_pcm_channel;
3330 card->alloc_rec_mic_channel = i810_alloc_rec_mic_channel;
3331 card->free_pcm_channel = i810_free_pcm_channel;
3332
3333 if ((card->channel = pci_alloc_consistent(pci_dev,
3334 sizeof(struct i810_channel)*NR_HW_CH, &card->chandma)) == NULL) {
3335 printk(KERN_ERR "i810: cannot allocate channel DMA memory\n");
3336 goto out_mem;
3337 }
3338
3339 { /* We may dispose of this altogether some time soon, so... */
3340 struct i810_channel *cp = card->channel;
3341
3342 cp[0].offset = 0;
3343 cp[0].port = 0x00;
3344 cp[0].num = 0;
3345 cp[1].offset = 0;
3346 cp[1].port = 0x10;
3347 cp[1].num = 1;
3348 cp[2].offset = 0;
3349 cp[2].port = 0x20;
3350 cp[2].num = 2;
3351 }
3352
3353 /* claim our iospace and irq */
3354 if (!request_region(card->iobase, 64, card_names[pci_id->driver_data])) {
3355 printk(KERN_ERR "i810_audio: unable to allocate region %lx\n", card->iobase);
3356 goto out_region1;
3357 }
3358 if (!request_region(card->ac97base, 256, card_names[pci_id->driver_data])) {
3359 printk(KERN_ERR "i810_audio: unable to allocate region %lx\n", card->ac97base);
3360 goto out_region2;
3361 }
3362
3363 if (card->use_mmio) {
3364 if (request_mem_region(card->ac97base_mmio_phys, 512, "ich_audio MMBAR")) {
3365 if ((card->ac97base_mmio = ioremap(card->ac97base_mmio_phys, 512))) { /*@FIXME can ioremap fail? don't know (jsaw) */
3366 if (request_mem_region(card->iobase_mmio_phys, 256, "ich_audio MBBAR")) {
3367 if ((card->iobase_mmio = ioremap(card->iobase_mmio_phys, 256))) {
3368 printk(KERN_INFO "i810: %s mmio at 0x%04lx and 0x%04lx\n",
3369 card_names[pci_id->driver_data],
3370 (unsigned long) card->ac97base_mmio,
3371 (unsigned long) card->iobase_mmio);
3372 }
3373 else {
3374 iounmap(card->ac97base_mmio);
3375 release_mem_region(card->ac97base_mmio_phys, 512);
3376 release_mem_region(card->iobase_mmio_phys, 512);
3377 card->use_mmio = 0;
3378 }
3379 }
3380 else {
3381 iounmap(card->ac97base_mmio);
3382 release_mem_region(card->ac97base_mmio_phys, 512);
3383 card->use_mmio = 0;
3384 }
3385 }
3386 }
3387 else {
3388 card->use_mmio = 0;
3389 }
3390 }
3391
3392 /* initialize AC97 codec and register /dev/mixer */
3393 if (i810_ac97_init(card) <= 0)
3394 goto out_iospace;
3395 pci_set_drvdata(pci_dev, card);
3396
3397 if(clocking == 0) {
3398 clocking = 48000;
3399 i810_configure_clocking();
3400 }
3401
3402 /* register /dev/dsp */
3403 if ((card->dev_audio = register_sound_dsp(&i810_audio_fops, -1)) < 0) {
3404 int i;
3405 printk(KERN_ERR "i810_audio: couldn't register DSP device!\n");
3406 for (i = 0; i < NR_AC97; i++)
3407 if (card->ac97_codec[i] != NULL) {
3408 unregister_sound_mixer(card->ac97_codec[i]->dev_mixer);
3409 ac97_release_codec(card->ac97_codec[i]);
3410 }
3411 goto out_iospace;
3412 }
3413
3414 if (request_irq(card->irq, &i810_interrupt, SA_SHIRQ,
3415 card_names[pci_id->driver_data], card)) {
3416 printk(KERN_ERR "i810_audio: unable to allocate irq %d\n", card->irq);
3417 goto out_iospace;
3418 }
3419
3420
3421 card->initializing = 0;
3422 return 0;
3423
3424 out_iospace:
3425 if (card->use_mmio) {
3426 iounmap(card->ac97base_mmio);
3427 iounmap(card->iobase_mmio);
3428 release_mem_region(card->ac97base_mmio_phys, 512);
3429 release_mem_region(card->iobase_mmio_phys, 256);
3430 }
3431 release_region(card->ac97base, 256);
3432 out_region2:
3433 release_region(card->iobase, 64);
3434 out_region1:
3435 pci_free_consistent(pci_dev, sizeof(struct i810_channel)*NR_HW_CH,
3436 card->channel, card->chandma);
3437 out_mem:
3438 kfree(card);
3439 return -ENODEV;
3440 }
3441
3442 static void __devexit i810_remove(struct pci_dev *pci_dev)
3443 {
3444 int i;
3445 struct i810_card *card = pci_get_drvdata(pci_dev);
3446 /* free hardware resources */
3447 free_irq(card->irq, devs);
3448 release_region(card->iobase, 64);
3449 release_region(card->ac97base, 256);
3450 pci_free_consistent(pci_dev, sizeof(struct i810_channel)*NR_HW_CH,
3451 card->channel, card->chandma);
3452 if (card->use_mmio) {
3453 iounmap(card->ac97base_mmio);
3454 iounmap(card->iobase_mmio);
3455 release_mem_region(card->ac97base_mmio_phys, 512);
3456 release_mem_region(card->iobase_mmio_phys, 256);
3457 }
3458
3459 /* unregister audio devices */
3460 for (i = 0; i < NR_AC97; i++)
3461 if (card->ac97_codec[i] != NULL) {
3462 unregister_sound_mixer(card->ac97_codec[i]->dev_mixer);
3463 ac97_release_codec(card->ac97_codec[i]);
3464 card->ac97_codec[i] = NULL;
3465 }
3466 unregister_sound_dsp(card->dev_audio);
3467 kfree(card);
3468 }
3469
3470 #ifdef CONFIG_PM
3471 static int i810_pm_suspend(struct pci_dev *dev, pm_message_t pm_state)
3472 {
3473 struct i810_card *card = pci_get_drvdata(dev);
3474 struct i810_state *state;
3475 unsigned long flags;
3476 struct dmabuf *dmabuf;
3477 int i,num_ac97;
3478 #ifdef DEBUG
3479 printk("i810_audio: i810_pm_suspend called\n");
3480 #endif
3481 if(!card) return 0;
3482 spin_lock_irqsave(&card->lock, flags);
3483 card->pm_suspended=1;
3484 for(i=0;i<NR_HW_CH;i++) {
3485 state = card->states[i];
3486 if(!state) continue;
3487 /* this happens only if there are open files */
3488 dmabuf = &state->dmabuf;
3489 if(dmabuf->enable & DAC_RUNNING ||
3490 (dmabuf->count && (dmabuf->trigger & PCM_ENABLE_OUTPUT))) {
3491 state->pm_saved_dac_rate=dmabuf->rate;
3492 stop_dac(state);
3493 } else {
3494 state->pm_saved_dac_rate=0;
3495 }
3496 if(dmabuf->enable & ADC_RUNNING) {
3497 state->pm_saved_adc_rate=dmabuf->rate;
3498 stop_adc(state);
3499 } else {
3500 state->pm_saved_adc_rate=0;
3501 }
3502 dmabuf->ready = 0;
3503 dmabuf->swptr = dmabuf->hwptr = 0;
3504 dmabuf->count = dmabuf->total_bytes = 0;
3505 }
3506
3507 spin_unlock_irqrestore(&card->lock, flags);
3508
3509 /* save mixer settings */
3510 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) {
3511 struct ac97_codec *codec = card->ac97_codec[num_ac97];
3512 if(!codec) continue;
3513 for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) {
3514 if((supported_mixer(codec,i)) &&
3515 (codec->read_mixer)) {
3516 card->pm_saved_mixer_settings[i][num_ac97]=
3517 codec->read_mixer(codec,i);
3518 }
3519 }
3520 }
3521 pci_save_state(dev); /* XXX do we need this? */
3522 pci_disable_device(dev); /* disable busmastering */
3523 pci_set_power_state(dev,3); /* Zzz. */
3524
3525 return 0;
3526 }
3527
3528
3529 static int i810_pm_resume(struct pci_dev *dev)
3530 {
3531 int num_ac97,i=0;
3532 struct i810_card *card=pci_get_drvdata(dev);
3533 pci_enable_device(dev);
3534 pci_restore_state (dev);
3535
3536 /* observation of a toshiba portege 3440ct suggests that the
3537 hardware has to be more or less completely reinitialized from
3538 scratch after an apm suspend. Works For Me. -dan */
3539
3540 i810_ac97_power_up_bus(card);
3541
3542 for (num_ac97 = 0; num_ac97 < NR_AC97; num_ac97++) {
3543 struct ac97_codec *codec = card->ac97_codec[num_ac97];
3544 /* check they haven't stolen the hardware while we were
3545 away */
3546 if(!codec || !i810_ac97_exists(card,num_ac97)) {
3547 if(num_ac97) continue;
3548 else BUG();
3549 }
3550 if(!i810_ac97_probe_and_powerup(card,codec)) BUG();
3551
3552 if((card->ac97_features&0x0001)) {
3553 /* at probe time we found we could do variable
3554 rates, but APM suspend has made it forget
3555 its magical powers */
3556 if(!i810_ac97_enable_variable_rate(codec)) BUG();
3557 }
3558 /* we lost our mixer settings, so restore them */
3559 for(i=0;i< SOUND_MIXER_NRDEVICES ;i++) {
3560 if(supported_mixer(codec,i)){
3561 int val=card->
3562 pm_saved_mixer_settings[i][num_ac97];
3563 codec->mixer_state[i]=val;
3564 codec->write_mixer(codec,i,
3565 (val & 0xff) ,
3566 ((val >> 8) & 0xff) );
3567 }
3568 }
3569 }
3570
3571 /* we need to restore the sample rate from whatever it was */
3572 for(i=0;i<NR_HW_CH;i++) {
3573 struct i810_state * state=card->states[i];
3574 if(state) {
3575 if(state->pm_saved_adc_rate)
3576 i810_set_adc_rate(state,state->pm_saved_adc_rate);
3577 if(state->pm_saved_dac_rate)
3578 i810_set_dac_rate(state,state->pm_saved_dac_rate);
3579 }
3580 }
3581
3582
3583 card->pm_suspended = 0;
3584
3585 /* any processes that were reading/writing during the suspend
3586 probably ended up here */
3587 for(i=0;i<NR_HW_CH;i++) {
3588 struct i810_state *state = card->states[i];
3589 if(state) wake_up(&state->dmabuf.wait);
3590 }
3591
3592 return 0;
3593 }
3594 #endif /* CONFIG_PM */
3595
3596 MODULE_AUTHOR("The Linux kernel team");
3597 MODULE_DESCRIPTION("Intel 810 audio support");
3598 MODULE_LICENSE("GPL");
3599 module_param(ftsodell, int, 0444);
3600 module_param(clocking, uint, 0444);
3601 module_param(strict_clocking, int, 0444);
3602 module_param(spdif_locked, int, 0444);
3603
3604 #define I810_MODULE_NAME "i810_audio"
3605
3606 static struct pci_driver i810_pci_driver = {
3607 .name = I810_MODULE_NAME,
3608 .id_table = i810_pci_tbl,
3609 .probe = i810_probe,
3610 .remove = __devexit_p(i810_remove),
3611 #ifdef CONFIG_PM
3612 .suspend = i810_pm_suspend,
3613 .resume = i810_pm_resume,
3614 #endif /* CONFIG_PM */
3615 };
3616
3617
3618 static int __init i810_init_module (void)
3619 {
3620 int retval;
3621
3622 printk(KERN_INFO "Intel 810 + AC97 Audio, version "
3623 DRIVER_VERSION ", " __TIME__ " " __DATE__ "\n");
3624
3625 retval = pci_register_driver(&i810_pci_driver);
3626 if (retval)
3627 return retval;
3628
3629 if(ftsodell != 0) {
3630 printk("i810_audio: ftsodell is now a deprecated option.\n");
3631 }
3632 if(spdif_locked > 0 ) {
3633 if(spdif_locked == 32000 || spdif_locked == 44100 || spdif_locked == 48000) {
3634 printk("i810_audio: Enabling S/PDIF at sample rate %dHz.\n", spdif_locked);
3635 } else {
3636 printk("i810_audio: S/PDIF can only be locked to 32000, 44100, or 48000Hz.\n");
3637 spdif_locked = 0;
3638 }
3639 }
3640
3641 return 0;
3642 }
3643
3644 static void __exit i810_cleanup_module (void)
3645 {
3646 pci_unregister_driver(&i810_pci_driver);
3647 }
3648
3649 module_init(i810_init_module);
3650 module_exit(i810_cleanup_module);
3651
3652 /*
3653 Local Variables:
3654 c-basic-offset: 8
3655 End:
3656 */
Community contributions to the Openmoko Kernel