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[PATCH] ata_piix: fix ghost device probing by honoring PCS present bits
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / scsi / ata_piix.c
blob01b3530cf6dfa1a7e039a024c5ff0b2686344daa
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "2.00"
97
98 enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
103
104 PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108
109 /* combined mode. if set, PATA is channel 0.
110 * if clear, PATA is channel 1.
111 */
112 PIIX_PORT_ENABLED = (1 << 0),
113 PIIX_PORT_PRESENT = (1 << 4),
114
115 PIIX_80C_PRI = (1 << 5) | (1 << 4),
116 PIIX_80C_SEC = (1 << 7) | (1 << 6),
117
118 /* controller IDs */
119 piix4_pata = 0,
120 ich5_pata = 1,
121 ich5_sata = 2,
122 esb_sata = 3,
123 ich6_sata = 4,
124 ich6_sata_ahci = 5,
125 ich6m_sata_ahci = 6,
126 ich8_sata_ahci = 7,
127
128 /* constants for mapping table */
129 P0 = 0, /* port 0 */
130 P1 = 1, /* port 1 */
131 P2 = 2, /* port 2 */
132 P3 = 3, /* port 3 */
133 IDE = -1, /* IDE */
134 NA = -2, /* not avaliable */
135 RV = -3, /* reserved */
136
137 PIIX_AHCI_DEVICE = 6,
138 };
139
140 struct piix_map_db {
141 const u32 mask;
142 const u16 port_enable;
143 const int present_shift;
144 const int map[][4];
145 };
146
147 struct piix_host_priv {
148 const int *map;
149 const struct piix_map_db *map_db;
150 };
151
152 static int piix_init_one (struct pci_dev *pdev,
153 const struct pci_device_id *ent);
154 static void piix_host_stop(struct ata_host_set *host_set);
155 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
156 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
157 static void piix_pata_error_handler(struct ata_port *ap);
158 static void piix_sata_error_handler(struct ata_port *ap);
159
160 static unsigned int in_module_init = 1;
161
162 static const struct pci_device_id piix_pci_tbl[] = {
163 #ifdef ATA_ENABLE_PATA
164 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
165 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
166 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
167 { 0x8086, 0x27df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
168 #endif
169
170 /* NOTE: The following PCI ids must be kept in sync with the
171 * list in drivers/pci/quirks.c.
172 */
173
174 /* 82801EB (ICH5) */
175 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
176 /* 82801EB (ICH5) */
177 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
178 /* 6300ESB (ICH5 variant with broken PCS present bits) */
179 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
180 /* 6300ESB pretending RAID */
181 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
182 /* 82801FB/FW (ICH6/ICH6W) */
183 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
184 /* 82801FR/FRW (ICH6R/ICH6RW) */
185 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
186 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
187 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
188 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
189 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
190 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
191 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
192 /* Enterprise Southbridge 2 (where's the datasheet?) */
193 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
194 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
195 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
196 /* SATA Controller 2 IDE (ICH8, ditto) */
197 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
198 /* Mobile SATA Controller IDE (ICH8M, ditto) */
199 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
200
201 { } /* terminate list */
202 };
203
204 static struct pci_driver piix_pci_driver = {
205 .name = DRV_NAME,
206 .id_table = piix_pci_tbl,
207 .probe = piix_init_one,
208 .remove = ata_pci_remove_one,
209 .suspend = ata_pci_device_suspend,
210 .resume = ata_pci_device_resume,
211 };
212
213 static struct scsi_host_template piix_sht = {
214 .module = THIS_MODULE,
215 .name = DRV_NAME,
216 .ioctl = ata_scsi_ioctl,
217 .queuecommand = ata_scsi_queuecmd,
218 .can_queue = ATA_DEF_QUEUE,
219 .this_id = ATA_SHT_THIS_ID,
220 .sg_tablesize = LIBATA_MAX_PRD,
221 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
222 .emulated = ATA_SHT_EMULATED,
223 .use_clustering = ATA_SHT_USE_CLUSTERING,
224 .proc_name = DRV_NAME,
225 .dma_boundary = ATA_DMA_BOUNDARY,
226 .slave_configure = ata_scsi_slave_config,
227 .slave_destroy = ata_scsi_slave_destroy,
228 .bios_param = ata_std_bios_param,
229 .resume = ata_scsi_device_resume,
230 .suspend = ata_scsi_device_suspend,
231 };
232
233 static const struct ata_port_operations piix_pata_ops = {
234 .port_disable = ata_port_disable,
235 .set_piomode = piix_set_piomode,
236 .set_dmamode = piix_set_dmamode,
237 .mode_filter = ata_pci_default_filter,
238
239 .tf_load = ata_tf_load,
240 .tf_read = ata_tf_read,
241 .check_status = ata_check_status,
242 .exec_command = ata_exec_command,
243 .dev_select = ata_std_dev_select,
244
245 .bmdma_setup = ata_bmdma_setup,
246 .bmdma_start = ata_bmdma_start,
247 .bmdma_stop = ata_bmdma_stop,
248 .bmdma_status = ata_bmdma_status,
249 .qc_prep = ata_qc_prep,
250 .qc_issue = ata_qc_issue_prot,
251 .data_xfer = ata_pio_data_xfer,
252
253 .freeze = ata_bmdma_freeze,
254 .thaw = ata_bmdma_thaw,
255 .error_handler = piix_pata_error_handler,
256 .post_internal_cmd = ata_bmdma_post_internal_cmd,
257
258 .irq_handler = ata_interrupt,
259 .irq_clear = ata_bmdma_irq_clear,
260
261 .port_start = ata_port_start,
262 .port_stop = ata_port_stop,
263 .host_stop = piix_host_stop,
264 };
265
266 static const struct ata_port_operations piix_sata_ops = {
267 .port_disable = ata_port_disable,
268
269 .tf_load = ata_tf_load,
270 .tf_read = ata_tf_read,
271 .check_status = ata_check_status,
272 .exec_command = ata_exec_command,
273 .dev_select = ata_std_dev_select,
274
275 .bmdma_setup = ata_bmdma_setup,
276 .bmdma_start = ata_bmdma_start,
277 .bmdma_stop = ata_bmdma_stop,
278 .bmdma_status = ata_bmdma_status,
279 .qc_prep = ata_qc_prep,
280 .qc_issue = ata_qc_issue_prot,
281 .data_xfer = ata_pio_data_xfer,
282
283 .freeze = ata_bmdma_freeze,
284 .thaw = ata_bmdma_thaw,
285 .error_handler = piix_sata_error_handler,
286 .post_internal_cmd = ata_bmdma_post_internal_cmd,
287
288 .irq_handler = ata_interrupt,
289 .irq_clear = ata_bmdma_irq_clear,
290
291 .port_start = ata_port_start,
292 .port_stop = ata_port_stop,
293 .host_stop = piix_host_stop,
294 };
295
296 static const struct piix_map_db ich5_map_db = {
297 .mask = 0x7,
298 .port_enable = 0x3,
299 .present_shift = 4,
300 .map = {
301 /* PM PS SM SS MAP */
302 { P0, NA, P1, NA }, /* 000b */
303 { P1, NA, P0, NA }, /* 001b */
304 { RV, RV, RV, RV },
305 { RV, RV, RV, RV },
306 { P0, P1, IDE, IDE }, /* 100b */
307 { P1, P0, IDE, IDE }, /* 101b */
308 { IDE, IDE, P0, P1 }, /* 110b */
309 { IDE, IDE, P1, P0 }, /* 111b */
310 },
311 };
312
313 static const struct piix_map_db ich6_map_db = {
314 .mask = 0x3,
315 .port_enable = 0xf,
316 .present_shift = 4,
317 .map = {
318 /* PM PS SM SS MAP */
319 { P0, P2, P1, P3 }, /* 00b */
320 { IDE, IDE, P1, P3 }, /* 01b */
321 { P0, P2, IDE, IDE }, /* 10b */
322 { RV, RV, RV, RV },
323 },
324 };
325
326 static const struct piix_map_db ich6m_map_db = {
327 .mask = 0x3,
328 .port_enable = 0x5,
329 .present_shift = 4,
330 .map = {
331 /* PM PS SM SS MAP */
332 { P0, P2, RV, RV }, /* 00b */
333 { RV, RV, RV, RV },
334 { P0, P2, IDE, IDE }, /* 10b */
335 { RV, RV, RV, RV },
336 },
337 };
338
339 static const struct piix_map_db ich8_map_db = {
340 .mask = 0x3,
341 .port_enable = 0x3,
342 .present_shift = 8,
343 .map = {
344 /* PM PS SM SS MAP */
345 { P0, NA, P1, NA }, /* 00b (hardwired) */
346 { RV, RV, RV, RV },
347 { RV, RV, RV, RV }, /* 10b (never) */
348 { RV, RV, RV, RV },
349 },
350 };
351
352 static const struct piix_map_db *piix_map_db_table[] = {
353 [ich5_sata] = &ich5_map_db,
354 [esb_sata] = &ich5_map_db,
355 [ich6_sata] = &ich6_map_db,
356 [ich6_sata_ahci] = &ich6_map_db,
357 [ich6m_sata_ahci] = &ich6m_map_db,
358 [ich8_sata_ahci] = &ich8_map_db,
359 };
360
361 static struct ata_port_info piix_port_info[] = {
362 /* piix4_pata */
363 {
364 .sht = &piix_sht,
365 .host_flags = ATA_FLAG_SLAVE_POSS,
366 .pio_mask = 0x1f, /* pio0-4 */
367 #if 0
368 .mwdma_mask = 0x06, /* mwdma1-2 */
369 #else
370 .mwdma_mask = 0x00, /* mwdma broken */
371 #endif
372 .udma_mask = ATA_UDMA_MASK_40C,
373 .port_ops = &piix_pata_ops,
374 },
375
376 /* ich5_pata */
377 {
378 .sht = &piix_sht,
379 .host_flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
380 .pio_mask = 0x1f, /* pio0-4 */
381 #if 0
382 .mwdma_mask = 0x06, /* mwdma1-2 */
383 #else
384 .mwdma_mask = 0x00, /* mwdma broken */
385 #endif
386 .udma_mask = 0x3f, /* udma0-5 */
387 .port_ops = &piix_pata_ops,
388 },
389
390 /* ich5_sata */
391 {
392 .sht = &piix_sht,
393 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
394 .pio_mask = 0x1f, /* pio0-4 */
395 .mwdma_mask = 0x07, /* mwdma0-2 */
396 .udma_mask = 0x7f, /* udma0-6 */
397 .port_ops = &piix_sata_ops,
398 },
399
400 /* i6300esb_sata */
401 {
402 .sht = &piix_sht,
403 .host_flags = ATA_FLAG_SATA |
404 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS,
405 .pio_mask = 0x1f, /* pio0-4 */
406 .mwdma_mask = 0x07, /* mwdma0-2 */
407 .udma_mask = 0x7f, /* udma0-6 */
408 .port_ops = &piix_sata_ops,
409 },
410
411 /* ich6_sata */
412 {
413 .sht = &piix_sht,
414 .host_flags = ATA_FLAG_SATA |
415 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR,
416 .pio_mask = 0x1f, /* pio0-4 */
417 .mwdma_mask = 0x07, /* mwdma0-2 */
418 .udma_mask = 0x7f, /* udma0-6 */
419 .port_ops = &piix_sata_ops,
420 },
421
422 /* ich6_sata_ahci */
423 {
424 .sht = &piix_sht,
425 .host_flags = ATA_FLAG_SATA |
426 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
427 PIIX_FLAG_AHCI,
428 .pio_mask = 0x1f, /* pio0-4 */
429 .mwdma_mask = 0x07, /* mwdma0-2 */
430 .udma_mask = 0x7f, /* udma0-6 */
431 .port_ops = &piix_sata_ops,
432 },
433
434 /* ich6m_sata_ahci */
435 {
436 .sht = &piix_sht,
437 .host_flags = ATA_FLAG_SATA |
438 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
439 PIIX_FLAG_AHCI,
440 .pio_mask = 0x1f, /* pio0-4 */
441 .mwdma_mask = 0x07, /* mwdma0-2 */
442 .udma_mask = 0x7f, /* udma0-6 */
443 .port_ops = &piix_sata_ops,
444 },
445
446 /* ich8_sata_ahci */
447 {
448 .sht = &piix_sht,
449 .host_flags = ATA_FLAG_SATA |
450 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
451 PIIX_FLAG_AHCI,
452 .pio_mask = 0x1f, /* pio0-4 */
453 .mwdma_mask = 0x07, /* mwdma0-2 */
454 .udma_mask = 0x7f, /* udma0-6 */
455 .port_ops = &piix_sata_ops,
456 },
457 };
458
459 static struct pci_bits piix_enable_bits[] = {
460 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
461 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
462 };
463
464 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
465 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
466 MODULE_LICENSE("GPL");
467 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
468 MODULE_VERSION(DRV_VERSION);
469
470 /**
471 * piix_pata_cbl_detect - Probe host controller cable detect info
472 * @ap: Port for which cable detect info is desired
473 *
474 * Read 80c cable indicator from ATA PCI device's PCI config
475 * register. This register is normally set by firmware (BIOS).
476 *
477 * LOCKING:
478 * None (inherited from caller).
479 */
480 static void piix_pata_cbl_detect(struct ata_port *ap)
481 {
482 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
483 u8 tmp, mask;
484
485 /* no 80c support in host controller? */
486 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
487 goto cbl40;
488
489 /* check BIOS cable detect results */
490 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
491 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
492 if ((tmp & mask) == 0)
493 goto cbl40;
494
495 ap->cbl = ATA_CBL_PATA80;
496 return;
497
498 cbl40:
499 ap->cbl = ATA_CBL_PATA40;
500 ap->udma_mask &= ATA_UDMA_MASK_40C;
501 }
502
503 /**
504 * piix_pata_prereset - prereset for PATA host controller
505 * @ap: Target port
506 *
507 * Prereset including cable detection.
508 *
509 * LOCKING:
510 * None (inherited from caller).
511 */
512 static int piix_pata_prereset(struct ata_port *ap)
513 {
514 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
515
516 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
517 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
518 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
519 return 0;
520 }
521
522 piix_pata_cbl_detect(ap);
523
524 return ata_std_prereset(ap);
525 }
526
527 static void piix_pata_error_handler(struct ata_port *ap)
528 {
529 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
530 ata_std_postreset);
531 }
532
533 /**
534 * piix_sata_present_mask - determine present mask for SATA host controller
535 * @ap: Target port
536 *
537 * Reads SATA PCI device's PCI config register Port Configuration
538 * and Status (PCS) to determine port and device availability.
539 *
540 * LOCKING:
541 * None (inherited from caller).
542 *
543 * RETURNS:
544 * determined present_mask
545 */
546 static unsigned int piix_sata_present_mask(struct ata_port *ap)
547 {
548 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
549 struct piix_host_priv *hpriv = ap->host_set->private_data;
550 const unsigned int *map = hpriv->map;
551 int base = 2 * ap->hard_port_no;
552 unsigned int present_mask = 0;
553 int port, i;
554 u16 pcs;
555
556 pci_read_config_word(pdev, ICH5_PCS, &pcs);
557 DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base);
558
559 for (i = 0; i < 2; i++) {
560 port = map[base + i];
561 if (port < 0)
562 continue;
563 if ((ap->flags & PIIX_FLAG_IGNORE_PCS) ||
564 (pcs & 1 << (hpriv->map_db->present_shift + port)))
565 present_mask |= 1 << i;
566 }
567
568 DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n",
569 ap->id, pcs, present_mask);
570
571 return present_mask;
572 }
573
574 /**
575 * piix_sata_softreset - reset SATA host port via ATA SRST
576 * @ap: port to reset
577 * @classes: resulting classes of attached devices
578 *
579 * Reset SATA host port via ATA SRST. On controllers with
580 * reliable PCS present bits, the bits are used to determine
581 * device presence.
582 *
583 * LOCKING:
584 * Kernel thread context (may sleep)
585 *
586 * RETURNS:
587 * 0 on success, -errno otherwise.
588 */
589 static int piix_sata_softreset(struct ata_port *ap, unsigned int *classes)
590 {
591 unsigned int present_mask;
592 int i, rc;
593
594 present_mask = piix_sata_present_mask(ap);
595
596 rc = ata_std_softreset(ap, classes);
597 if (rc)
598 return rc;
599
600 for (i = 0; i < ATA_MAX_DEVICES; i++) {
601 if (!(present_mask & (1 << i)))
602 classes[i] = ATA_DEV_NONE;
603 }
604
605 return 0;
606 }
607
608 static void piix_sata_error_handler(struct ata_port *ap)
609 {
610 ata_bmdma_drive_eh(ap, ata_std_prereset, piix_sata_softreset, NULL,
611 ata_std_postreset);
612 }
613
614 /**
615 * piix_set_piomode - Initialize host controller PATA PIO timings
616 * @ap: Port whose timings we are configuring
617 * @adev: um
618 *
619 * Set PIO mode for device, in host controller PCI config space.
620 *
621 * LOCKING:
622 * None (inherited from caller).
623 */
624
625 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
626 {
627 unsigned int pio = adev->pio_mode - XFER_PIO_0;
628 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
629 unsigned int is_slave = (adev->devno != 0);
630 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
631 unsigned int slave_port = 0x44;
632 u16 master_data;
633 u8 slave_data;
634
635 static const /* ISP RTC */
636 u8 timings[][2] = { { 0, 0 },
637 { 0, 0 },
638 { 1, 0 },
639 { 2, 1 },
640 { 2, 3 }, };
641
642 pci_read_config_word(dev, master_port, &master_data);
643 if (is_slave) {
644 master_data |= 0x4000;
645 /* enable PPE, IE and TIME */
646 master_data |= 0x0070;
647 pci_read_config_byte(dev, slave_port, &slave_data);
648 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
649 slave_data |=
650 (timings[pio][0] << 2) |
651 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
652 } else {
653 master_data &= 0xccf8;
654 /* enable PPE, IE and TIME */
655 master_data |= 0x0007;
656 master_data |=
657 (timings[pio][0] << 12) |
658 (timings[pio][1] << 8);
659 }
660 pci_write_config_word(dev, master_port, master_data);
661 if (is_slave)
662 pci_write_config_byte(dev, slave_port, slave_data);
663 }
664
665 /**
666 * piix_set_dmamode - Initialize host controller PATA PIO timings
667 * @ap: Port whose timings we are configuring
668 * @adev: um
669 * @udma: udma mode, 0 - 6
670 *
671 * Set UDMA mode for device, in host controller PCI config space.
672 *
673 * LOCKING:
674 * None (inherited from caller).
675 */
676
677 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
678 {
679 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
680 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
681 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
682 u8 speed = udma;
683 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
684 int a_speed = 3 << (drive_dn * 4);
685 int u_flag = 1 << drive_dn;
686 int v_flag = 0x01 << drive_dn;
687 int w_flag = 0x10 << drive_dn;
688 int u_speed = 0;
689 int sitre;
690 u16 reg4042, reg4a;
691 u8 reg48, reg54, reg55;
692
693 pci_read_config_word(dev, maslave, &reg4042);
694 DPRINTK("reg4042 = 0x%04x\n", reg4042);
695 sitre = (reg4042 & 0x4000) ? 1 : 0;
696 pci_read_config_byte(dev, 0x48, &reg48);
697 pci_read_config_word(dev, 0x4a, &reg4a);
698 pci_read_config_byte(dev, 0x54, &reg54);
699 pci_read_config_byte(dev, 0x55, &reg55);
700
701 switch(speed) {
702 case XFER_UDMA_4:
703 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
704 case XFER_UDMA_6:
705 case XFER_UDMA_5:
706 case XFER_UDMA_3:
707 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
708 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
709 case XFER_MW_DMA_2:
710 case XFER_MW_DMA_1: break;
711 default:
712 BUG();
713 return;
714 }
715
716 if (speed >= XFER_UDMA_0) {
717 if (!(reg48 & u_flag))
718 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
719 if (speed == XFER_UDMA_5) {
720 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
721 } else {
722 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
723 }
724 if ((reg4a & a_speed) != u_speed)
725 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
726 if (speed > XFER_UDMA_2) {
727 if (!(reg54 & v_flag))
728 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
729 } else
730 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
731 } else {
732 if (reg48 & u_flag)
733 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
734 if (reg4a & a_speed)
735 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
736 if (reg54 & v_flag)
737 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
738 if (reg55 & w_flag)
739 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
740 }
741 }
742
743 #define AHCI_PCI_BAR 5
744 #define AHCI_GLOBAL_CTL 0x04
745 #define AHCI_ENABLE (1 << 31)
746 static int piix_disable_ahci(struct pci_dev *pdev)
747 {
748 void __iomem *mmio;
749 u32 tmp;
750 int rc = 0;
751
752 /* BUG: pci_enable_device has not yet been called. This
753 * works because this device is usually set up by BIOS.
754 */
755
756 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
757 !pci_resource_len(pdev, AHCI_PCI_BAR))
758 return 0;
759
760 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
761 if (!mmio)
762 return -ENOMEM;
763
764 tmp = readl(mmio + AHCI_GLOBAL_CTL);
765 if (tmp & AHCI_ENABLE) {
766 tmp &= ~AHCI_ENABLE;
767 writel(tmp, mmio + AHCI_GLOBAL_CTL);
768
769 tmp = readl(mmio + AHCI_GLOBAL_CTL);
770 if (tmp & AHCI_ENABLE)
771 rc = -EIO;
772 }
773
774 pci_iounmap(pdev, mmio);
775 return rc;
776 }
777
778 /**
779 * piix_check_450nx_errata - Check for problem 450NX setup
780 * @ata_dev: the PCI device to check
781 *
782 * Check for the present of 450NX errata #19 and errata #25. If
783 * they are found return an error code so we can turn off DMA
784 */
785
786 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
787 {
788 struct pci_dev *pdev = NULL;
789 u16 cfg;
790 u8 rev;
791 int no_piix_dma = 0;
792
793 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
794 {
795 /* Look for 450NX PXB. Check for problem configurations
796 A PCI quirk checks bit 6 already */
797 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
798 pci_read_config_word(pdev, 0x41, &cfg);
799 /* Only on the original revision: IDE DMA can hang */
800 if (rev == 0x00)
801 no_piix_dma = 1;
802 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
803 else if (cfg & (1<<14) && rev < 5)
804 no_piix_dma = 2;
805 }
806 if (no_piix_dma)
807 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
808 if (no_piix_dma == 2)
809 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
810 return no_piix_dma;
811 }
812
813 static void __devinit piix_init_pcs(struct pci_dev *pdev,
814 const struct piix_map_db *map_db)
815 {
816 u16 pcs, new_pcs;
817
818 pci_read_config_word(pdev, ICH5_PCS, &pcs);
819
820 new_pcs = pcs | map_db->port_enable;
821
822 if (new_pcs != pcs) {
823 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
824 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
825 msleep(150);
826 }
827 }
828
829 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
830 struct ata_port_info *pinfo,
831 const struct piix_map_db *map_db)
832 {
833 struct piix_host_priv *hpriv = pinfo[0].private_data;
834 const unsigned int *map;
835 int i, invalid_map = 0;
836 u8 map_value;
837
838 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
839
840 map = map_db->map[map_value & map_db->mask];
841
842 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
843 for (i = 0; i < 4; i++) {
844 switch (map[i]) {
845 case RV:
846 invalid_map = 1;
847 printk(" XX");
848 break;
849
850 case NA:
851 printk(" --");
852 break;
853
854 case IDE:
855 WARN_ON((i & 1) || map[i + 1] != IDE);
856 pinfo[i / 2] = piix_port_info[ich5_pata];
857 pinfo[i / 2].private_data = hpriv;
858 i++;
859 printk(" IDE IDE");
860 break;
861
862 default:
863 printk(" P%d", map[i]);
864 if (i & 1)
865 pinfo[i / 2].host_flags |= ATA_FLAG_SLAVE_POSS;
866 break;
867 }
868 }
869 printk(" ]\n");
870
871 if (invalid_map)
872 dev_printk(KERN_ERR, &pdev->dev,
873 "invalid MAP value %u\n", map_value);
874
875 hpriv->map = map;
876 hpriv->map_db = map_db;
877 }
878
879 /**
880 * piix_init_one - Register PIIX ATA PCI device with kernel services
881 * @pdev: PCI device to register
882 * @ent: Entry in piix_pci_tbl matching with @pdev
883 *
884 * Called from kernel PCI layer. We probe for combined mode (sigh),
885 * and then hand over control to libata, for it to do the rest.
886 *
887 * LOCKING:
888 * Inherited from PCI layer (may sleep).
889 *
890 * RETURNS:
891 * Zero on success, or -ERRNO value.
892 */
893
894 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
895 {
896 static int printed_version;
897 struct ata_port_info port_info[2];
898 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
899 struct piix_host_priv *hpriv;
900 unsigned long host_flags;
901
902 if (!printed_version++)
903 dev_printk(KERN_DEBUG, &pdev->dev,
904 "version " DRV_VERSION "\n");
905
906 /* no hotplugging support (FIXME) */
907 if (!in_module_init)
908 return -ENODEV;
909
910 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
911 if (!hpriv)
912 return -ENOMEM;
913
914 port_info[0] = piix_port_info[ent->driver_data];
915 port_info[1] = piix_port_info[ent->driver_data];
916 port_info[0].private_data = hpriv;
917 port_info[1].private_data = hpriv;
918
919 host_flags = port_info[0].host_flags;
920
921 if (host_flags & PIIX_FLAG_AHCI) {
922 u8 tmp;
923 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
924 if (tmp == PIIX_AHCI_DEVICE) {
925 int rc = piix_disable_ahci(pdev);
926 if (rc)
927 return rc;
928 }
929 }
930
931 /* Initialize SATA map */
932 if (host_flags & ATA_FLAG_SATA) {
933 piix_init_sata_map(pdev, port_info,
934 piix_map_db_table[ent->driver_data]);
935 piix_init_pcs(pdev, piix_map_db_table[ent->driver_data]);
936 }
937
938 /* On ICH5, some BIOSen disable the interrupt using the
939 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
940 * On ICH6, this bit has the same effect, but only when
941 * MSI is disabled (and it is disabled, as we don't use
942 * message-signalled interrupts currently).
943 */
944 if (host_flags & PIIX_FLAG_CHECKINTR)
945 pci_intx(pdev, 1);
946
947 if (piix_check_450nx_errata(pdev)) {
948 /* This writes into the master table but it does not
949 really matter for this errata as we will apply it to
950 all the PIIX devices on the board */
951 port_info[0].mwdma_mask = 0;
952 port_info[0].udma_mask = 0;
953 port_info[1].mwdma_mask = 0;
954 port_info[1].udma_mask = 0;
955 }
956 return ata_pci_init_one(pdev, ppinfo, 2);
957 }
958
959 static void piix_host_stop(struct ata_host_set *host_set)
960 {
961 if (host_set->next == NULL)
962 kfree(host_set->private_data);
963 ata_host_stop(host_set);
964 }
965
966 static int __init piix_init(void)
967 {
968 int rc;
969
970 DPRINTK("pci_module_init\n");
971 rc = pci_module_init(&piix_pci_driver);
972 if (rc)
973 return rc;
974
975 in_module_init = 0;
976
977 DPRINTK("done\n");
978 return 0;
979 }
980
981 static void __exit piix_exit(void)
982 {
983 pci_unregister_driver(&piix_pci_driver);
984 }
985
986 module_init(piix_init);
987 module_exit(piix_exit);
988
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