drivers/i2c/busses/i2c-au1550.c

   1 /*
   2  * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
   3  * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
   4  *
   5  * 2.6 port by Matt Porter <mporter@kernel.crashing.org>
   6  *
   7  * The documentation describes this as an SMBus controller, but it doesn't
   8  * understand any of the SMBus protocol in hardware.  It's really an I2C
   9  * controller that could emulate most of the SMBus in software.
  10  *
  11  * This is just a skeleton adapter to use with the Au1550 PSC
  12  * algorithm.  It was developed for the Pb1550, but will work with
  13  * any Au1550 board that has a similar PSC configuration.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version 2
  18  * of the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  28  */
  29
  30 #include <linux/delay.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/init.h>
  34 #include <linux/errno.h>
  35 #include <linux/i2c.h>
  36
  37 #include <asm/mach-au1x00/au1000.h>
  38 #include <asm/mach-pb1x00/pb1550.h>
  39 #include <asm/mach-au1x00/au1xxx_psc.h>
  40
  41 #include "i2c-au1550.h"
  42
  43 static int
  44 wait_xfer_done(struct i2c_au1550_data *adap)
  45 {
  46         u32     stat;
  47         int     i;
  48         volatile psc_smb_t      *sp;
  49
  50         sp = (volatile psc_smb_t *)(adap->psc_base);
  51
  52         /* Wait for Tx FIFO Underflow.
  53         */
  54         for (i = 0; i < adap->xfer_timeout; i++) {
  55                 stat = sp->psc_smbevnt;
  56                 au_sync();
  57                 if ((stat & PSC_SMBEVNT_TU) != 0) {
  58                         /* Clear it.  */
  59                         sp->psc_smbevnt = PSC_SMBEVNT_TU;
  60                         au_sync();
  61                         return 0;
  62                 }
  63                 udelay(1);
  64         }
  65
  66         return -ETIMEDOUT;
  67 }
  68
  69 static int
  70 wait_ack(struct i2c_au1550_data *adap)
  71 {
  72         u32     stat;
  73         volatile psc_smb_t      *sp;
  74
  75         if (wait_xfer_done(adap))
  76                 return -ETIMEDOUT;
  77
  78         sp = (volatile psc_smb_t *)(adap->psc_base);
  79
  80         stat = sp->psc_smbevnt;
  81         au_sync();
  82
  83         if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0)
  84                 return -ETIMEDOUT;
  85
  86         return 0;
  87 }
  88
  89 static int
  90 wait_master_done(struct i2c_au1550_data *adap)
  91 {
  92         u32     stat;
  93         int     i;
  94         volatile psc_smb_t      *sp;
  95
  96         sp = (volatile psc_smb_t *)(adap->psc_base);
  97
  98         /* Wait for Master Done.
  99         */
 100         for (i = 0; i < adap->xfer_timeout; i++) {
 101                 stat = sp->psc_smbevnt;
 102                 au_sync();
 103                 if ((stat & PSC_SMBEVNT_MD) != 0)
 104                         return 0;
 105                 udelay(1);
 106         }
 107
 108         return -ETIMEDOUT;
 109 }
 110
 111 static int
 112 do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd)
 113 {
 114         volatile psc_smb_t      *sp;
 115         u32                     stat;
 116
 117         sp = (volatile psc_smb_t *)(adap->psc_base);
 118
 119         /* Reset the FIFOs, clear events.
 120         */
 121         sp->psc_smbpcr = PSC_SMBPCR_DC;
 122         sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR;
 123         au_sync();
 124         do {
 125                 stat = sp->psc_smbpcr;
 126                 au_sync();
 127         } while ((stat & PSC_SMBPCR_DC) != 0);
 128
 129         /* Write out the i2c chip address and specify operation
 130         */
 131         addr <<= 1;
 132         if (rd)
 133                 addr |= 1;
 134
 135         /* Put byte into fifo, start up master.
 136         */
 137         sp->psc_smbtxrx = addr;
 138         au_sync();
 139         sp->psc_smbpcr = PSC_SMBPCR_MS;
 140         au_sync();
 141         if (wait_ack(adap))
 142                 return -EIO;
 143         return 0;
 144 }
 145
 146 static u32
 147 wait_for_rx_byte(struct i2c_au1550_data *adap, u32 *ret_data)
 148 {
 149         int     j;
 150         u32     data, stat;
 151         volatile psc_smb_t      *sp;
 152
 153         if (wait_xfer_done(adap))
 154                 return -EIO;
 155
 156         sp = (volatile psc_smb_t *)(adap->psc_base);
 157
 158         j =  adap->xfer_timeout * 100;
 159         do {
 160                 j--;
 161                 if (j <= 0)
 162                         return -EIO;
 163
 164                 stat = sp->psc_smbstat;
 165                 au_sync();
 166                 if ((stat & PSC_SMBSTAT_RE) == 0)
 167                         j = 0;
 168                 else
 169                         udelay(1);
 170         } while (j > 0);
 171         data = sp->psc_smbtxrx;
 172         au_sync();
 173         *ret_data = data;
 174
 175         return 0;
 176 }
 177
 178 static int
 179 i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
 180                     unsigned int len)
 181 {
 182         int     i;
 183         u32     data;
 184         volatile psc_smb_t      *sp;
 185
 186         if (len == 0)
 187                 return 0;
 188
 189         /* A read is performed by stuffing the transmit fifo with
 190          * zero bytes for timing, waiting for bytes to appear in the
 191          * receive fifo, then reading the bytes.
 192          */
 193
 194         sp = (volatile psc_smb_t *)(adap->psc_base);
 195
 196         i = 0;
 197         while (i < (len-1)) {
 198                 sp->psc_smbtxrx = 0;
 199                 au_sync();
 200                 if (wait_for_rx_byte(adap, &data))
 201                         return -EIO;
 202
 203                 buf[i] = data;
 204                 i++;
 205         }
 206
 207         /* The last byte has to indicate transfer done.
 208         */
 209         sp->psc_smbtxrx = PSC_SMBTXRX_STP;
 210         au_sync();
 211         if (wait_master_done(adap))
 212                 return -EIO;
 213
 214         data = sp->psc_smbtxrx;
 215         au_sync();
 216         buf[i] = data;
 217         return 0;
 218 }
 219
 220 static int
 221 i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
 222                      unsigned int len)
 223 {
 224         int     i;
 225         u32     data;
 226         volatile psc_smb_t      *sp;
 227
 228         if (len == 0)
 229                 return 0;
 230
 231         sp = (volatile psc_smb_t *)(adap->psc_base);
 232
 233         i = 0;
 234         while (i < (len-1)) {
 235                 data = buf[i];
 236                 sp->psc_smbtxrx = data;
 237                 au_sync();
 238                 if (wait_ack(adap))
 239                         return -EIO;
 240                 i++;
 241         }
 242
 243         /* The last byte has to indicate transfer done.
 244         */
 245         data = buf[i];
 246         data |= PSC_SMBTXRX_STP;
 247         sp->psc_smbtxrx = data;
 248         au_sync();
 249         if (wait_master_done(adap))
 250                 return -EIO;
 251         return 0;
 252 }
 253
 254 static int
 255 au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
 256 {
 257         struct i2c_au1550_data *adap = i2c_adap->algo_data;
 258         struct i2c_msg *p;
 259         int i, err = 0;
 260
 261         for (i = 0; !err && i < num; i++) {
 262                 p = &msgs[i];
 263                 err = do_address(adap, p->addr, p->flags & I2C_M_RD);
 264                 if (err || !p->len)
 265                         continue;
 266                 if (p->flags & I2C_M_RD)
 267                         err = i2c_read(adap, p->buf, p->len);
 268                 else
 269                         err = i2c_write(adap, p->buf, p->len);
 270         }
 271
 272         /* Return the number of messages processed, or the error code.
 273         */
 274         if (err == 0)
 275                 err = num;
 276         return err;
 277 }
 278
 279 static u32
 280 au1550_func(struct i2c_adapter *adap)
 281 {
 282         return I2C_FUNC_I2C;
 283 }
 284
 285 static struct i2c_algorithm au1550_algo = {
 286         .name           = "Au1550 algorithm",
 287         .id             = I2C_ALGO_AU1550,
 288         .master_xfer    = au1550_xfer,
 289         .functionality  = au1550_func,
 290 };
 291
 292 /*
 293  * registering functions to load algorithms at runtime
 294  * Prior to calling us, the 50MHz clock frequency and routing
 295  * must have been set up for the PSC indicated by the adapter.
 296  */
 297 int
 298 i2c_au1550_add_bus(struct i2c_adapter *i2c_adap)
 299 {
 300         struct i2c_au1550_data *adap = i2c_adap->algo_data;
 301         volatile psc_smb_t      *sp;
 302         u32     stat;
 303
 304         i2c_adap->algo = &au1550_algo;
 305
 306         /* Now, set up the PSC for SMBus PIO mode.
 307         */
 308         sp = (volatile psc_smb_t *)(adap->psc_base);
 309         sp->psc_ctrl = PSC_CTRL_DISABLE;
 310         au_sync();
 311         sp->psc_sel = PSC_SEL_PS_SMBUSMODE;
 312         sp->psc_smbcfg = 0;
 313         au_sync();
 314         sp->psc_ctrl = PSC_CTRL_ENABLE;
 315         au_sync();
 316         do {
 317                 stat = sp->psc_smbstat;
 318                 au_sync();
 319         } while ((stat & PSC_SMBSTAT_SR) == 0);
 320
 321         sp->psc_smbcfg = (PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 |
 322                                 PSC_SMBCFG_DD_DISABLE);
 323
 324         /* Divide by 8 to get a 6.25 MHz clock.  The later protocol
 325          * timings are based on this clock.
 326          */
 327         sp->psc_smbcfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
 328         sp->psc_smbmsk = PSC_SMBMSK_ALLMASK;
 329         au_sync();
 330
 331         /* Set the protocol timer values.  See Table 71 in the
 332          * Au1550 Data Book for standard timing values.
 333          */
 334         sp->psc_smbtmr = PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \
 335                 PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \
 336                 PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \
 337                 PSC_SMBTMR_SET_CH(15);
 338         au_sync();
 339
 340         sp->psc_smbcfg |= PSC_SMBCFG_DE_ENABLE;
 341         do {
 342                 stat = sp->psc_smbstat;
 343                 au_sync();
 344         } while ((stat & PSC_SMBSTAT_DR) == 0);
 345
 346         return i2c_add_adapter(i2c_adap);
 347 }
 348
 349
 350 int
 351 i2c_au1550_del_bus(struct i2c_adapter *adap)
 352 {
 353         return i2c_del_adapter(adap);
 354 }
 355
 356 static int
 357 pb1550_reg(struct i2c_client *client)
 358 {
 359         return 0;
 360 }
 361
 362 static int
 363 pb1550_unreg(struct i2c_client *client)
 364 {
 365         return 0;
 366 }
 367
 368 static struct i2c_au1550_data pb1550_i2c_info = {
 369         SMBUS_PSC_BASE, 200, 200
 370 };
 371
 372 static struct i2c_adapter pb1550_board_adapter = {
 373         name:              "pb1550 adapter",
 374         id:                I2C_HW_AU1550_PSC,
 375         algo:              NULL,
 376         algo_data:         &pb1550_i2c_info,
 377         client_register:   pb1550_reg,
 378         client_unregister: pb1550_unreg,
 379 };
 380
 381 /* BIG hack to support the control interface on the Wolfson WM8731
 382  * audio codec on the Pb1550 board.  We get an address and two data
 383  * bytes to write, create an i2c message, and send it across the
 384  * i2c transfer function.  We do this here because we have access to
 385  * the i2c adapter structure.
 386  */
 387 static struct i2c_msg wm_i2c_msg;  /* We don't want this stuff on the stack */
 388 static  u8 i2cbuf[2];
 389
 390 int
 391 pb1550_wm_codec_write(u8 addr, u8 reg, u8 val)
 392 {
 393         wm_i2c_msg.addr = addr;
 394         wm_i2c_msg.flags = 0;
 395         wm_i2c_msg.buf = i2cbuf;
 396         wm_i2c_msg.len = 2;
 397         i2cbuf[0] = reg;
 398         i2cbuf[1] = val;
 399
 400         return pb1550_board_adapter.algo->master_xfer(&pb1550_board_adapter, &wm_i2c_msg, 1);
 401 }
 402
 403 static int __init
 404 i2c_au1550_init(void)
 405 {
 406         printk(KERN_INFO "Au1550 I2C: ");
 407
 408         /* This is where we would set up a 50MHz clock source
 409          * and routing.  On the Pb1550, the SMBus is PSC2, which
 410          * uses a shared clock with USB.  This has been already
 411          * configured by Yamon as a 48MHz clock, close enough
 412          * for our work.
 413          */
 414         if (i2c_au1550_add_bus(&pb1550_board_adapter) < 0) {
 415                 printk("failed to initialize.\n");
 416                 return -ENODEV;
 417         }
 418
 419         printk("initialized.\n");
 420         return 0;
 421 }
 422
 423 static void __exit
 424 i2c_au1550_exit(void)
 425 {
 426         i2c_au1550_del_bus(&pb1550_board_adapter);
 427 }
 428
 429 MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
 430 MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
 431 MODULE_LICENSE("GPL");
 432
 433 module_init (i2c_au1550_init);
 434 module_exit (i2c_au1550_exit);