?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] bcm43xx: fix "include" issues on some platforms.
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / net / wireless / bcm43xx / bcm43xx_main.c
blob29df4f844c9ba16d3783bc0d4a605cbc2503d4ad
1 /*
2
3 Broadcom BCM43xx wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Stefano Brivio <st3@riseup.net>
7 Michael Buesch <mbuesch@freenet.de>
8 Danny van Dyk <kugelfang@gentoo.org>
9 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <net/iw_handler.h>
43
44 #include "bcm43xx.h"
45 #include "bcm43xx_main.h"
46 #include "bcm43xx_debugfs.h"
47 #include "bcm43xx_radio.h"
48 #include "bcm43xx_phy.h"
49 #include "bcm43xx_dma.h"
50 #include "bcm43xx_pio.h"
51 #include "bcm43xx_power.h"
52 #include "bcm43xx_wx.h"
53 #include "bcm43xx_ethtool.h"
54 #include "bcm43xx_xmit.h"
55
56
57 MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
62
63 #ifdef CONFIG_BCM947XX
64 extern char *nvram_get(char *name);
65 #endif
66
67 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
68 static int modparam_pio;
69 module_param_named(pio, modparam_pio, int, 0444);
70 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
71 #elif defined(CONFIG_BCM43XX_DMA)
72 # define modparam_pio 0
73 #elif defined(CONFIG_BCM43XX_PIO)
74 # define modparam_pio 1
75 #endif
76
77 static int modparam_bad_frames_preempt;
78 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
79 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
80
81 static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
82 module_param_named(short_retry, modparam_short_retry, int, 0444);
83 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
84
85 static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
86 module_param_named(long_retry, modparam_long_retry, int, 0444);
87 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
88
89 static int modparam_locale = -1;
90 module_param_named(locale, modparam_locale, int, 0444);
91 MODULE_PARM_DESC(country, "Select LocaleCode 0-11 (For travelers)");
92
93 static int modparam_noleds;
94 module_param_named(noleds, modparam_noleds, int, 0444);
95 MODULE_PARM_DESC(noleds, "Turn off all LED activity");
96
97 #ifdef CONFIG_BCM43XX_DEBUG
98 static char modparam_fwpostfix[64];
99 module_param_string(fwpostfix, modparam_fwpostfix, 64, 0444);
100 MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for debugging.");
101 #else
102 # define modparam_fwpostfix ""
103 #endif /* CONFIG_BCM43XX_DEBUG*/
104
105
106 /* If you want to debug with just a single device, enable this,
107 * where the string is the pci device ID (as given by the kernel's
108 * pci_name function) of the device to be used.
109 */
110 //#define DEBUG_SINGLE_DEVICE_ONLY "0001:11:00.0"
111
112 /* If you want to enable printing of each MMIO access, enable this. */
113 //#define DEBUG_ENABLE_MMIO_PRINT
114
115 /* If you want to enable printing of MMIO access within
116 * ucode/pcm upload, initvals write, enable this.
117 */
118 //#define DEBUG_ENABLE_UCODE_MMIO_PRINT
119
120 /* If you want to enable printing of PCI Config Space access, enable this */
121 //#define DEBUG_ENABLE_PCILOG
122
123
124 /* Detailed list maintained at:
125 * http://openfacts.berlios.de/index-en.phtml?title=Bcm43xxDevices
126 */
127 static struct pci_device_id bcm43xx_pci_tbl[] = {
128 /* Broadcom 4303 802.11b */
129 { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
130 /* Broadcom 4307 802.11b */
131 { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
132 /* Broadcom 4318 802.11b/g */
133 { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
134 /* Broadcom 4306 802.11b/g */
135 { PCI_VENDOR_ID_BROADCOM, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
136 /* Broadcom 4306 802.11a */
137 // { PCI_VENDOR_ID_BROADCOM, 0x4321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
138 /* Broadcom 4309 802.11a/b/g */
139 { PCI_VENDOR_ID_BROADCOM, 0x4324, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
140 /* Broadcom 43XG 802.11b/g */
141 { PCI_VENDOR_ID_BROADCOM, 0x4325, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
142 #ifdef CONFIG_BCM947XX
143 /* SB bus on BCM947xx */
144 { PCI_VENDOR_ID_BROADCOM, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 #endif
146 { 0 },
147 };
148 MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
149
150 static void bcm43xx_ram_write(struct bcm43xx_private *bcm, u16 offset, u32 val)
151 {
152 u32 status;
153
154 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
155 if (!(status & BCM43xx_SBF_XFER_REG_BYTESWAP))
156 val = swab32(val);
157
158 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_CONTROL, offset);
159 mmiowb();
160 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_DATA, val);
161 }
162
163 static inline
164 void bcm43xx_shm_control_word(struct bcm43xx_private *bcm,
165 u16 routing, u16 offset)
166 {
167 u32 control;
168
169 /* "offset" is the WORD offset. */
170
171 control = routing;
172 control <<= 16;
173 control |= offset;
174 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_CONTROL, control);
175 }
176
177 u32 bcm43xx_shm_read32(struct bcm43xx_private *bcm,
178 u16 routing, u16 offset)
179 {
180 u32 ret;
181
182 if (routing == BCM43xx_SHM_SHARED) {
183 if (offset & 0x0003) {
184 /* Unaligned access */
185 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
186 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
187 ret <<= 16;
188 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
189 ret |= bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
190
191 return ret;
192 }
193 offset >>= 2;
194 }
195 bcm43xx_shm_control_word(bcm, routing, offset);
196 ret = bcm43xx_read32(bcm, BCM43xx_MMIO_SHM_DATA);
197
198 return ret;
199 }
200
201 u16 bcm43xx_shm_read16(struct bcm43xx_private *bcm,
202 u16 routing, u16 offset)
203 {
204 u16 ret;
205
206 if (routing == BCM43xx_SHM_SHARED) {
207 if (offset & 0x0003) {
208 /* Unaligned access */
209 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
210 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
211
212 return ret;
213 }
214 offset >>= 2;
215 }
216 bcm43xx_shm_control_word(bcm, routing, offset);
217 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
218
219 return ret;
220 }
221
222 void bcm43xx_shm_write32(struct bcm43xx_private *bcm,
223 u16 routing, u16 offset,
224 u32 value)
225 {
226 if (routing == BCM43xx_SHM_SHARED) {
227 if (offset & 0x0003) {
228 /* Unaligned access */
229 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
230 mmiowb();
231 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
232 (value >> 16) & 0xffff);
233 mmiowb();
234 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
235 mmiowb();
236 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA,
237 value & 0xffff);
238 return;
239 }
240 offset >>= 2;
241 }
242 bcm43xx_shm_control_word(bcm, routing, offset);
243 mmiowb();
244 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, value);
245 }
246
247 void bcm43xx_shm_write16(struct bcm43xx_private *bcm,
248 u16 routing, u16 offset,
249 u16 value)
250 {
251 if (routing == BCM43xx_SHM_SHARED) {
252 if (offset & 0x0003) {
253 /* Unaligned access */
254 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
255 mmiowb();
256 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
257 value);
258 return;
259 }
260 offset >>= 2;
261 }
262 bcm43xx_shm_control_word(bcm, routing, offset);
263 mmiowb();
264 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA, value);
265 }
266
267 void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf)
268 {
269 /* We need to be careful. As we read the TSF from multiple
270 * registers, we should take care of register overflows.
271 * In theory, the whole tsf read process should be atomic.
272 * We try to be atomic here, by restaring the read process,
273 * if any of the high registers changed (overflew).
274 */
275 if (bcm->current_core->rev >= 3) {
276 u32 low, high, high2;
277
278 do {
279 high = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
280 low = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
281 high2 = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
282 } while (unlikely(high != high2));
283
284 *tsf = high;
285 *tsf <<= 32;
286 *tsf |= low;
287 } else {
288 u64 tmp;
289 u16 v0, v1, v2, v3;
290 u16 test1, test2, test3;
291
292 do {
293 v3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
294 v2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
295 v1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
296 v0 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_0);
297
298 test3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
299 test2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
300 test1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
301 } while (v3 != test3 || v2 != test2 || v1 != test1);
302
303 *tsf = v3;
304 *tsf <<= 48;
305 tmp = v2;
306 tmp <<= 32;
307 *tsf |= tmp;
308 tmp = v1;
309 tmp <<= 16;
310 *tsf |= tmp;
311 *tsf |= v0;
312 }
313 }
314
315 void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf)
316 {
317 u32 status;
318
319 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
320 status |= BCM43xx_SBF_TIME_UPDATE;
321 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
322 mmiowb();
323
324 /* Be careful with the in-progress timer.
325 * First zero out the low register, so we have a full
326 * register-overflow duration to complete the operation.
327 */
328 if (bcm->current_core->rev >= 3) {
329 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
330 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
331
332 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
333 mmiowb();
334 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
335 mmiowb();
336 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
337 } else {
338 u16 v0 = (tsf & 0x000000000000FFFFULL);
339 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
340 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
341 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
342
343 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, 0);
344 mmiowb();
345 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_3, v3);
346 mmiowb();
347 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_2, v2);
348 mmiowb();
349 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_1, v1);
350 mmiowb();
351 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, v0);
352 }
353
354 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
355 status &= ~BCM43xx_SBF_TIME_UPDATE;
356 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
357 }
358
359 static
360 void bcm43xx_macfilter_set(struct bcm43xx_private *bcm,
361 u16 offset,
362 const u8 *mac)
363 {
364 u16 data;
365
366 offset |= 0x0020;
367 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
368
369 data = mac[0];
370 data |= mac[1] << 8;
371 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
372 data = mac[2];
373 data |= mac[3] << 8;
374 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
375 data = mac[4];
376 data |= mac[5] << 8;
377 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
378 }
379
380 static void bcm43xx_macfilter_clear(struct bcm43xx_private *bcm,
381 u16 offset)
382 {
383 const u8 zero_addr[ETH_ALEN] = { 0 };
384
385 bcm43xx_macfilter_set(bcm, offset, zero_addr);
386 }
387
388 static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_private *bcm)
389 {
390 const u8 *mac = (const u8 *)(bcm->net_dev->dev_addr);
391 const u8 *bssid = (const u8 *)(bcm->ieee->bssid);
392 u8 mac_bssid[ETH_ALEN * 2];
393 int i;
394
395 memcpy(mac_bssid, mac, ETH_ALEN);
396 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
397
398 /* Write our MAC address and BSSID to template ram */
399 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
400 bcm43xx_ram_write(bcm, 0x20 + i, *((u32 *)(mac_bssid + i)));
401 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
402 bcm43xx_ram_write(bcm, 0x78 + i, *((u32 *)(mac_bssid + i)));
403 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
404 bcm43xx_ram_write(bcm, 0x478 + i, *((u32 *)(mac_bssid + i)));
405 }
406
407 static void bcm43xx_set_slot_time(struct bcm43xx_private *bcm, u16 slot_time)
408 {
409 /* slot_time is in usec. */
410 if (bcm43xx_current_phy(bcm)->type != BCM43xx_PHYTYPE_G)
411 return;
412 bcm43xx_write16(bcm, 0x684, 510 + slot_time);
413 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0010, slot_time);
414 }
415
416 static void bcm43xx_short_slot_timing_enable(struct bcm43xx_private *bcm)
417 {
418 bcm43xx_set_slot_time(bcm, 9);
419 }
420
421 static void bcm43xx_short_slot_timing_disable(struct bcm43xx_private *bcm)
422 {
423 bcm43xx_set_slot_time(bcm, 20);
424 }
425
426 //FIXME: rename this func?
427 static void bcm43xx_disassociate(struct bcm43xx_private *bcm)
428 {
429 bcm43xx_mac_suspend(bcm);
430 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
431
432 bcm43xx_ram_write(bcm, 0x0026, 0x0000);
433 bcm43xx_ram_write(bcm, 0x0028, 0x0000);
434 bcm43xx_ram_write(bcm, 0x007E, 0x0000);
435 bcm43xx_ram_write(bcm, 0x0080, 0x0000);
436 bcm43xx_ram_write(bcm, 0x047E, 0x0000);
437 bcm43xx_ram_write(bcm, 0x0480, 0x0000);
438
439 if (bcm->current_core->rev < 3) {
440 bcm43xx_write16(bcm, 0x0610, 0x8000);
441 bcm43xx_write16(bcm, 0x060E, 0x0000);
442 } else
443 bcm43xx_write32(bcm, 0x0188, 0x80000000);
444
445 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
446
447 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G &&
448 ieee80211_is_ofdm_rate(bcm->softmac->txrates.default_rate))
449 bcm43xx_short_slot_timing_enable(bcm);
450
451 bcm43xx_mac_enable(bcm);
452 }
453
454 //FIXME: rename this func?
455 static void bcm43xx_associate(struct bcm43xx_private *bcm,
456 const u8 *mac)
457 {
458 memcpy(bcm->ieee->bssid, mac, ETH_ALEN);
459
460 bcm43xx_mac_suspend(bcm);
461 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_ASSOC, mac);
462 bcm43xx_write_mac_bssid_templates(bcm);
463 bcm43xx_mac_enable(bcm);
464 }
465
466 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
467 * Returns the _previously_ enabled IRQ mask.
468 */
469 static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_private *bcm, u32 mask)
470 {
471 u32 old_mask;
472
473 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
474 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
475
476 return old_mask;
477 }
478
479 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
480 * Returns the _previously_ enabled IRQ mask.
481 */
482 static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_private *bcm, u32 mask)
483 {
484 u32 old_mask;
485
486 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
487 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
488
489 return old_mask;
490 }
491
492 /* Make sure we don't receive more data from the device. */
493 static int bcm43xx_disable_interrupts_sync(struct bcm43xx_private *bcm, u32 *oldstate)
494 {
495 u32 old;
496 unsigned long flags;
497
498 bcm43xx_lock_mmio(bcm, flags);
499 if (bcm43xx_is_initializing(bcm) || bcm->shutting_down) {
500 bcm43xx_unlock_mmio(bcm, flags);
501 return -EBUSY;
502 }
503 old = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
504 tasklet_disable(&bcm->isr_tasklet);
505 bcm43xx_unlock_mmio(bcm, flags);
506 if (oldstate)
507 *oldstate = old;
508
509 return 0;
510 }
511
512 static int bcm43xx_read_radioinfo(struct bcm43xx_private *bcm)
513 {
514 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
515 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
516 u32 radio_id;
517 u16 manufact;
518 u16 version;
519 u8 revision;
520 s8 i;
521
522 if (bcm->chip_id == 0x4317) {
523 if (bcm->chip_rev == 0x00)
524 radio_id = 0x3205017F;
525 else if (bcm->chip_rev == 0x01)
526 radio_id = 0x4205017F;
527 else
528 radio_id = 0x5205017F;
529 } else {
530 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
531 radio_id = bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_HIGH);
532 radio_id <<= 16;
533 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
534 radio_id |= bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
535 }
536
537 manufact = (radio_id & 0x00000FFF);
538 version = (radio_id & 0x0FFFF000) >> 12;
539 revision = (radio_id & 0xF0000000) >> 28;
540
541 dprintk(KERN_INFO PFX "Detected Radio: ID: %x (Manuf: %x Ver: %x Rev: %x)\n",
542 radio_id, manufact, version, revision);
543
544 switch (phy->type) {
545 case BCM43xx_PHYTYPE_A:
546 if ((version != 0x2060) || (revision != 1) || (manufact != 0x17f))
547 goto err_unsupported_radio;
548 break;
549 case BCM43xx_PHYTYPE_B:
550 if ((version & 0xFFF0) != 0x2050)
551 goto err_unsupported_radio;
552 break;
553 case BCM43xx_PHYTYPE_G:
554 if (version != 0x2050)
555 goto err_unsupported_radio;
556 break;
557 }
558
559 radio->manufact = manufact;
560 radio->version = version;
561 radio->revision = revision;
562
563 /* Set default attenuation values. */
564 radio->baseband_atten = bcm43xx_default_baseband_attenuation(bcm);
565 radio->radio_atten = bcm43xx_default_radio_attenuation(bcm);
566 radio->txctl1 = bcm43xx_default_txctl1(bcm);
567 if (phy->type == BCM43xx_PHYTYPE_A)
568 radio->txpower_desired = bcm->sprom.maxpower_aphy;
569 else
570 radio->txpower_desired = bcm->sprom.maxpower_bgphy;
571
572 /* Initialize the in-memory nrssi Lookup Table. */
573 for (i = 0; i < 64; i++)
574 radio->nrssi_lt[i] = i;
575
576 return 0;
577
578 err_unsupported_radio:
579 printk(KERN_ERR PFX "Unsupported Radio connected to the PHY!\n");
580 return -ENODEV;
581 }
582
583 static const char * bcm43xx_locale_iso(u8 locale)
584 {
585 /* ISO 3166-1 country codes.
586 * Note that there aren't ISO 3166-1 codes for
587 * all or locales. (Not all locales are countries)
588 */
589 switch (locale) {
590 case BCM43xx_LOCALE_WORLD:
591 case BCM43xx_LOCALE_ALL:
592 return "XX";
593 case BCM43xx_LOCALE_THAILAND:
594 return "TH";
595 case BCM43xx_LOCALE_ISRAEL:
596 return "IL";
597 case BCM43xx_LOCALE_JORDAN:
598 return "JO";
599 case BCM43xx_LOCALE_CHINA:
600 return "CN";
601 case BCM43xx_LOCALE_JAPAN:
602 case BCM43xx_LOCALE_JAPAN_HIGH:
603 return "JP";
604 case BCM43xx_LOCALE_USA_CANADA_ANZ:
605 case BCM43xx_LOCALE_USA_LOW:
606 return "US";
607 case BCM43xx_LOCALE_EUROPE:
608 return "EU";
609 case BCM43xx_LOCALE_NONE:
610 return " ";
611 }
612 assert(0);
613 return " ";
614 }
615
616 static const char * bcm43xx_locale_string(u8 locale)
617 {
618 switch (locale) {
619 case BCM43xx_LOCALE_WORLD:
620 return "World";
621 case BCM43xx_LOCALE_THAILAND:
622 return "Thailand";
623 case BCM43xx_LOCALE_ISRAEL:
624 return "Israel";
625 case BCM43xx_LOCALE_JORDAN:
626 return "Jordan";
627 case BCM43xx_LOCALE_CHINA:
628 return "China";
629 case BCM43xx_LOCALE_JAPAN:
630 return "Japan";
631 case BCM43xx_LOCALE_USA_CANADA_ANZ:
632 return "USA/Canada/ANZ";
633 case BCM43xx_LOCALE_EUROPE:
634 return "Europe";
635 case BCM43xx_LOCALE_USA_LOW:
636 return "USAlow";
637 case BCM43xx_LOCALE_JAPAN_HIGH:
638 return "JapanHigh";
639 case BCM43xx_LOCALE_ALL:
640 return "All";
641 case BCM43xx_LOCALE_NONE:
642 return "None";
643 }
644 assert(0);
645 return "";
646 }
647
648 static inline u8 bcm43xx_crc8(u8 crc, u8 data)
649 {
650 static const u8 t[] = {
651 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
652 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
653 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
654 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
655 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
656 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
657 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
658 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
659 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
660 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
661 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
662 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
663 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
664 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
665 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
666 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
667 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
668 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
669 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
670 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
671 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
672 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
673 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
674 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
675 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
676 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
677 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
678 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
679 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
680 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
681 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
682 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
683 };
684 return t[crc ^ data];
685 }
686
687 static u8 bcm43xx_sprom_crc(const u16 *sprom)
688 {
689 int word;
690 u8 crc = 0xFF;
691
692 for (word = 0; word < BCM43xx_SPROM_SIZE - 1; word++) {
693 crc = bcm43xx_crc8(crc, sprom[word] & 0x00FF);
694 crc = bcm43xx_crc8(crc, (sprom[word] & 0xFF00) >> 8);
695 }
696 crc = bcm43xx_crc8(crc, sprom[BCM43xx_SPROM_VERSION] & 0x00FF);
697 crc ^= 0xFF;
698
699 return crc;
700 }
701
702 int bcm43xx_sprom_read(struct bcm43xx_private *bcm, u16 *sprom)
703 {
704 int i;
705 u8 crc, expected_crc;
706
707 for (i = 0; i < BCM43xx_SPROM_SIZE; i++)
708 sprom[i] = bcm43xx_read16(bcm, BCM43xx_SPROM_BASE + (i * 2));
709 /* CRC-8 check. */
710 crc = bcm43xx_sprom_crc(sprom);
711 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
712 if (crc != expected_crc) {
713 printk(KERN_WARNING PFX "WARNING: Invalid SPROM checksum "
714 "(0x%02X, expected: 0x%02X)\n",
715 crc, expected_crc);
716 return -EINVAL;
717 }
718
719 return 0;
720 }
721
722 int bcm43xx_sprom_write(struct bcm43xx_private *bcm, const u16 *sprom)
723 {
724 int i, err;
725 u8 crc, expected_crc;
726 u32 spromctl;
727
728 /* CRC-8 validation of the input data. */
729 crc = bcm43xx_sprom_crc(sprom);
730 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
731 if (crc != expected_crc) {
732 printk(KERN_ERR PFX "SPROM input data: Invalid CRC\n");
733 return -EINVAL;
734 }
735
736 printk(KERN_INFO PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
737 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_SPROMCTL, &spromctl);
738 if (err)
739 goto err_ctlreg;
740 spromctl |= 0x10; /* SPROM WRITE enable. */
741 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
742 if (err)
743 goto err_ctlreg;
744 /* We must burn lots of CPU cycles here, but that does not
745 * really matter as one does not write the SPROM every other minute...
746 */
747 printk(KERN_INFO PFX "[ 0%%");
748 mdelay(500);
749 for (i = 0; i < BCM43xx_SPROM_SIZE; i++) {
750 if (i == 16)
751 printk("25%%");
752 else if (i == 32)
753 printk("50%%");
754 else if (i == 48)
755 printk("75%%");
756 else if (i % 2)
757 printk(".");
758 bcm43xx_write16(bcm, BCM43xx_SPROM_BASE + (i * 2), sprom[i]);
759 mmiowb();
760 mdelay(20);
761 }
762 spromctl &= ~0x10; /* SPROM WRITE enable. */
763 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
764 if (err)
765 goto err_ctlreg;
766 mdelay(500);
767 printk("100%% ]\n");
768 printk(KERN_INFO PFX "SPROM written.\n");
769 bcm43xx_controller_restart(bcm, "SPROM update");
770
771 return 0;
772 err_ctlreg:
773 printk(KERN_ERR PFX "Could not access SPROM control register.\n");
774 return -ENODEV;
775 }
776
777 static int bcm43xx_sprom_extract(struct bcm43xx_private *bcm)
778 {
779 u16 value;
780 u16 *sprom;
781 #ifdef CONFIG_BCM947XX
782 char *c;
783 #endif
784
785 sprom = kzalloc(BCM43xx_SPROM_SIZE * sizeof(u16),
786 GFP_KERNEL);
787 if (!sprom) {
788 printk(KERN_ERR PFX "sprom_extract OOM\n");
789 return -ENOMEM;
790 }
791 #ifdef CONFIG_BCM947XX
792 sprom[BCM43xx_SPROM_BOARDFLAGS2] = atoi(nvram_get("boardflags2"));
793 sprom[BCM43xx_SPROM_BOARDFLAGS] = atoi(nvram_get("boardflags"));
794
795 if ((c = nvram_get("il0macaddr")) != NULL)
796 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_IL0MACADDR]));
797
798 if ((c = nvram_get("et1macaddr")) != NULL)
799 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_ET1MACADDR]));
800
801 sprom[BCM43xx_SPROM_PA0B0] = atoi(nvram_get("pa0b0"));
802 sprom[BCM43xx_SPROM_PA0B1] = atoi(nvram_get("pa0b1"));
803 sprom[BCM43xx_SPROM_PA0B2] = atoi(nvram_get("pa0b2"));
804
805 sprom[BCM43xx_SPROM_PA1B0] = atoi(nvram_get("pa1b0"));
806 sprom[BCM43xx_SPROM_PA1B1] = atoi(nvram_get("pa1b1"));
807 sprom[BCM43xx_SPROM_PA1B2] = atoi(nvram_get("pa1b2"));
808
809 sprom[BCM43xx_SPROM_BOARDREV] = atoi(nvram_get("boardrev"));
810 #else
811 bcm43xx_sprom_read(bcm, sprom);
812 #endif
813
814 /* boardflags2 */
815 value = sprom[BCM43xx_SPROM_BOARDFLAGS2];
816 bcm->sprom.boardflags2 = value;
817
818 /* il0macaddr */
819 value = sprom[BCM43xx_SPROM_IL0MACADDR + 0];
820 *(((u16 *)bcm->sprom.il0macaddr) + 0) = cpu_to_be16(value);
821 value = sprom[BCM43xx_SPROM_IL0MACADDR + 1];
822 *(((u16 *)bcm->sprom.il0macaddr) + 1) = cpu_to_be16(value);
823 value = sprom[BCM43xx_SPROM_IL0MACADDR + 2];
824 *(((u16 *)bcm->sprom.il0macaddr) + 2) = cpu_to_be16(value);
825
826 /* et0macaddr */
827 value = sprom[BCM43xx_SPROM_ET0MACADDR + 0];
828 *(((u16 *)bcm->sprom.et0macaddr) + 0) = cpu_to_be16(value);
829 value = sprom[BCM43xx_SPROM_ET0MACADDR + 1];
830 *(((u16 *)bcm->sprom.et0macaddr) + 1) = cpu_to_be16(value);
831 value = sprom[BCM43xx_SPROM_ET0MACADDR + 2];
832 *(((u16 *)bcm->sprom.et0macaddr) + 2) = cpu_to_be16(value);
833
834 /* et1macaddr */
835 value = sprom[BCM43xx_SPROM_ET1MACADDR + 0];
836 *(((u16 *)bcm->sprom.et1macaddr) + 0) = cpu_to_be16(value);
837 value = sprom[BCM43xx_SPROM_ET1MACADDR + 1];
838 *(((u16 *)bcm->sprom.et1macaddr) + 1) = cpu_to_be16(value);
839 value = sprom[BCM43xx_SPROM_ET1MACADDR + 2];
840 *(((u16 *)bcm->sprom.et1macaddr) + 2) = cpu_to_be16(value);
841
842 /* ethernet phy settings */
843 value = sprom[BCM43xx_SPROM_ETHPHY];
844 bcm->sprom.et0phyaddr = (value & 0x001F);
845 bcm->sprom.et1phyaddr = (value & 0x03E0) >> 5;
846 bcm->sprom.et0mdcport = (value & (1 << 14)) >> 14;
847 bcm->sprom.et1mdcport = (value & (1 << 15)) >> 15;
848
849 /* boardrev, antennas, locale */
850 value = sprom[BCM43xx_SPROM_BOARDREV];
851 bcm->sprom.boardrev = (value & 0x00FF);
852 bcm->sprom.locale = (value & 0x0F00) >> 8;
853 bcm->sprom.antennas_aphy = (value & 0x3000) >> 12;
854 bcm->sprom.antennas_bgphy = (value & 0xC000) >> 14;
855 if (modparam_locale != -1) {
856 if (modparam_locale >= 0 && modparam_locale <= 11) {
857 bcm->sprom.locale = modparam_locale;
858 printk(KERN_WARNING PFX "Operating with modified "
859 "LocaleCode %u (%s)\n",
860 bcm->sprom.locale,
861 bcm43xx_locale_string(bcm->sprom.locale));
862 } else {
863 printk(KERN_WARNING PFX "Module parameter \"locale\" "
864 "invalid value. (0 - 11)\n");
865 }
866 }
867
868 /* pa0b* */
869 value = sprom[BCM43xx_SPROM_PA0B0];
870 bcm->sprom.pa0b0 = value;
871 value = sprom[BCM43xx_SPROM_PA0B1];
872 bcm->sprom.pa0b1 = value;
873 value = sprom[BCM43xx_SPROM_PA0B2];
874 bcm->sprom.pa0b2 = value;
875
876 /* wl0gpio* */
877 value = sprom[BCM43xx_SPROM_WL0GPIO0];
878 if (value == 0x0000)
879 value = 0xFFFF;
880 bcm->sprom.wl0gpio0 = value & 0x00FF;
881 bcm->sprom.wl0gpio1 = (value & 0xFF00) >> 8;
882 value = sprom[BCM43xx_SPROM_WL0GPIO2];
883 if (value == 0x0000)
884 value = 0xFFFF;
885 bcm->sprom.wl0gpio2 = value & 0x00FF;
886 bcm->sprom.wl0gpio3 = (value & 0xFF00) >> 8;
887
888 /* maxpower */
889 value = sprom[BCM43xx_SPROM_MAXPWR];
890 bcm->sprom.maxpower_aphy = (value & 0xFF00) >> 8;
891 bcm->sprom.maxpower_bgphy = value & 0x00FF;
892
893 /* pa1b* */
894 value = sprom[BCM43xx_SPROM_PA1B0];
895 bcm->sprom.pa1b0 = value;
896 value = sprom[BCM43xx_SPROM_PA1B1];
897 bcm->sprom.pa1b1 = value;
898 value = sprom[BCM43xx_SPROM_PA1B2];
899 bcm->sprom.pa1b2 = value;
900
901 /* idle tssi target */
902 value = sprom[BCM43xx_SPROM_IDL_TSSI_TGT];
903 bcm->sprom.idle_tssi_tgt_aphy = value & 0x00FF;
904 bcm->sprom.idle_tssi_tgt_bgphy = (value & 0xFF00) >> 8;
905
906 /* boardflags */
907 value = sprom[BCM43xx_SPROM_BOARDFLAGS];
908 if (value == 0xFFFF)
909 value = 0x0000;
910 bcm->sprom.boardflags = value;
911 /* boardflags workarounds */
912 if (bcm->board_vendor == PCI_VENDOR_ID_DELL &&
913 bcm->chip_id == 0x4301 &&
914 bcm->board_revision == 0x74)
915 bcm->sprom.boardflags |= BCM43xx_BFL_BTCOEXIST;
916 if (bcm->board_vendor == PCI_VENDOR_ID_APPLE &&
917 bcm->board_type == 0x4E &&
918 bcm->board_revision > 0x40)
919 bcm->sprom.boardflags |= BCM43xx_BFL_PACTRL;
920
921 /* antenna gain */
922 value = sprom[BCM43xx_SPROM_ANTENNA_GAIN];
923 if (value == 0x0000 || value == 0xFFFF)
924 value = 0x0202;
925 /* convert values to Q5.2 */
926 bcm->sprom.antennagain_aphy = ((value & 0xFF00) >> 8) * 4;
927 bcm->sprom.antennagain_bgphy = (value & 0x00FF) * 4;
928
929 kfree(sprom);
930
931 return 0;
932 }
933
934 static void bcm43xx_geo_init(struct bcm43xx_private *bcm)
935 {
936 struct ieee80211_geo geo;
937 struct ieee80211_channel *chan;
938 int have_a = 0, have_bg = 0;
939 int i;
940 u8 channel;
941 struct bcm43xx_phyinfo *phy;
942 const char *iso_country;
943
944 memset(&geo, 0, sizeof(geo));
945 for (i = 0; i < bcm->nr_80211_available; i++) {
946 phy = &(bcm->core_80211_ext[i].phy);
947 switch (phy->type) {
948 case BCM43xx_PHYTYPE_B:
949 case BCM43xx_PHYTYPE_G:
950 have_bg = 1;
951 break;
952 case BCM43xx_PHYTYPE_A:
953 have_a = 1;
954 break;
955 default:
956 assert(0);
957 }
958 }
959 iso_country = bcm43xx_locale_iso(bcm->sprom.locale);
960
961 if (have_a) {
962 for (i = 0, channel = 0; channel < 201; channel++) {
963 chan = &geo.a[i++];
964 chan->freq = bcm43xx_channel_to_freq_a(channel);
965 chan->channel = channel;
966 }
967 geo.a_channels = i;
968 }
969 if (have_bg) {
970 for (i = 0, channel = 1; channel < 15; channel++) {
971 chan = &geo.bg[i++];
972 chan->freq = bcm43xx_channel_to_freq_bg(channel);
973 chan->channel = channel;
974 }
975 geo.bg_channels = i;
976 }
977 memcpy(geo.name, iso_country, 2);
978 if (0 /*TODO: Outdoor use only */)
979 geo.name[2] = 'O';
980 else if (0 /*TODO: Indoor use only */)
981 geo.name[2] = 'I';
982 else
983 geo.name[2] = ' ';
984 geo.name[3] = '\0';
985
986 ieee80211_set_geo(bcm->ieee, &geo);
987 }
988
989 /* DummyTransmission function, as documented on
990 * http://bcm-specs.sipsolutions.net/DummyTransmission
991 */
992 void bcm43xx_dummy_transmission(struct bcm43xx_private *bcm)
993 {
994 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
995 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
996 unsigned int i, max_loop;
997 u16 value = 0;
998 u32 buffer[5] = {
999 0x00000000,
1000 0x0000D400,
1001 0x00000000,
1002 0x00000001,
1003 0x00000000,
1004 };
1005
1006 switch (phy->type) {
1007 case BCM43xx_PHYTYPE_A:
1008 max_loop = 0x1E;
1009 buffer[0] = 0xCC010200;
1010 break;
1011 case BCM43xx_PHYTYPE_B:
1012 case BCM43xx_PHYTYPE_G:
1013 max_loop = 0xFA;
1014 buffer[0] = 0x6E840B00;
1015 break;
1016 default:
1017 assert(0);
1018 return;
1019 }
1020
1021 for (i = 0; i < 5; i++)
1022 bcm43xx_ram_write(bcm, i * 4, buffer[i]);
1023
1024 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
1025
1026 bcm43xx_write16(bcm, 0x0568, 0x0000);
1027 bcm43xx_write16(bcm, 0x07C0, 0x0000);
1028 bcm43xx_write16(bcm, 0x050C, ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0));
1029 bcm43xx_write16(bcm, 0x0508, 0x0000);
1030 bcm43xx_write16(bcm, 0x050A, 0x0000);
1031 bcm43xx_write16(bcm, 0x054C, 0x0000);
1032 bcm43xx_write16(bcm, 0x056A, 0x0014);
1033 bcm43xx_write16(bcm, 0x0568, 0x0826);
1034 bcm43xx_write16(bcm, 0x0500, 0x0000);
1035 bcm43xx_write16(bcm, 0x0502, 0x0030);
1036
1037 if (radio->version == 0x2050 && radio->revision <= 0x5)
1038 bcm43xx_radio_write16(bcm, 0x0051, 0x0017);
1039 for (i = 0x00; i < max_loop; i++) {
1040 value = bcm43xx_read16(bcm, 0x050E);
1041 if (value & 0x0080)
1042 break;
1043 udelay(10);
1044 }
1045 for (i = 0x00; i < 0x0A; i++) {
1046 value = bcm43xx_read16(bcm, 0x050E);
1047 if (value & 0x0400)
1048 break;
1049 udelay(10);
1050 }
1051 for (i = 0x00; i < 0x0A; i++) {
1052 value = bcm43xx_read16(bcm, 0x0690);
1053 if (!(value & 0x0100))
1054 break;
1055 udelay(10);
1056 }
1057 if (radio->version == 0x2050 && radio->revision <= 0x5)
1058 bcm43xx_radio_write16(bcm, 0x0051, 0x0037);
1059 }
1060
1061 static void key_write(struct bcm43xx_private *bcm,
1062 u8 index, u8 algorithm, const u16 *key)
1063 {
1064 unsigned int i, basic_wep = 0;
1065 u32 offset;
1066 u16 value;
1067
1068 /* Write associated key information */
1069 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x100 + (index * 2),
1070 ((index << 4) | (algorithm & 0x0F)));
1071
1072 /* The first 4 WEP keys need extra love */
1073 if (((algorithm == BCM43xx_SEC_ALGO_WEP) ||
1074 (algorithm == BCM43xx_SEC_ALGO_WEP104)) && (index < 4))
1075 basic_wep = 1;
1076
1077 /* Write key payload, 8 little endian words */
1078 offset = bcm->security_offset + (index * BCM43xx_SEC_KEYSIZE);
1079 for (i = 0; i < (BCM43xx_SEC_KEYSIZE / sizeof(u16)); i++) {
1080 value = cpu_to_le16(key[i]);
1081 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1082 offset + (i * 2), value);
1083
1084 if (!basic_wep)
1085 continue;
1086
1087 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1088 offset + (i * 2) + 4 * BCM43xx_SEC_KEYSIZE,
1089 value);
1090 }
1091 }
1092
1093 static void keymac_write(struct bcm43xx_private *bcm,
1094 u8 index, const u32 *addr)
1095 {
1096 /* for keys 0-3 there is no associated mac address */
1097 if (index < 4)
1098 return;
1099
1100 index -= 4;
1101 if (bcm->current_core->rev >= 5) {
1102 bcm43xx_shm_write32(bcm,
1103 BCM43xx_SHM_HWMAC,
1104 index * 2,
1105 cpu_to_be32(*addr));
1106 bcm43xx_shm_write16(bcm,
1107 BCM43xx_SHM_HWMAC,
1108 (index * 2) + 1,
1109 cpu_to_be16(*((u16 *)(addr + 1))));
1110 } else {
1111 if (index < 8) {
1112 TODO(); /* Put them in the macaddress filter */
1113 } else {
1114 TODO();
1115 /* Put them BCM43xx_SHM_SHARED, stating index 0x0120.
1116 Keep in mind to update the count of keymacs in 0x003E as well! */
1117 }
1118 }
1119 }
1120
1121 static int bcm43xx_key_write(struct bcm43xx_private *bcm,
1122 u8 index, u8 algorithm,
1123 const u8 *_key, int key_len,
1124 const u8 *mac_addr)
1125 {
1126 u8 key[BCM43xx_SEC_KEYSIZE] = { 0 };
1127
1128 if (index >= ARRAY_SIZE(bcm->key))
1129 return -EINVAL;
1130 if (key_len > ARRAY_SIZE(key))
1131 return -EINVAL;
1132 if (algorithm < 1 || algorithm > 5)
1133 return -EINVAL;
1134
1135 memcpy(key, _key, key_len);
1136 key_write(bcm, index, algorithm, (const u16 *)key);
1137 keymac_write(bcm, index, (const u32 *)mac_addr);
1138
1139 bcm->key[index].algorithm = algorithm;
1140
1141 return 0;
1142 }
1143
1144 static void bcm43xx_clear_keys(struct bcm43xx_private *bcm)
1145 {
1146 static const u32 zero_mac[2] = { 0 };
1147 unsigned int i,j, nr_keys = 54;
1148 u16 offset;
1149
1150 if (bcm->current_core->rev < 5)
1151 nr_keys = 16;
1152 assert(nr_keys <= ARRAY_SIZE(bcm->key));
1153
1154 for (i = 0; i < nr_keys; i++) {
1155 bcm->key[i].enabled = 0;
1156 /* returns for i < 4 immediately */
1157 keymac_write(bcm, i, zero_mac);
1158 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1159 0x100 + (i * 2), 0x0000);
1160 for (j = 0; j < 8; j++) {
1161 offset = bcm->security_offset + (j * 4) + (i * BCM43xx_SEC_KEYSIZE);
1162 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1163 offset, 0x0000);
1164 }
1165 }
1166 dprintk(KERN_INFO PFX "Keys cleared\n");
1167 }
1168
1169 /* Lowlevel core-switch function. This is only to be used in
1170 * bcm43xx_switch_core() and bcm43xx_probe_cores()
1171 */
1172 static int _switch_core(struct bcm43xx_private *bcm, int core)
1173 {
1174 int err;
1175 int attempts = 0;
1176 u32 current_core;
1177
1178 assert(core >= 0);
1179 while (1) {
1180 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1181 (core * 0x1000) + 0x18000000);
1182 if (unlikely(err))
1183 goto error;
1184 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1185 &current_core);
1186 if (unlikely(err))
1187 goto error;
1188 current_core = (current_core - 0x18000000) / 0x1000;
1189 if (current_core == core)
1190 break;
1191
1192 if (unlikely(attempts++ > BCM43xx_SWITCH_CORE_MAX_RETRIES))
1193 goto error;
1194 udelay(10);
1195 }
1196 #ifdef CONFIG_BCM947XX
1197 if (bcm->pci_dev->bus->number == 0)
1198 bcm->current_core_offset = 0x1000 * core;
1199 else
1200 bcm->current_core_offset = 0;
1201 #endif
1202
1203 return 0;
1204 error:
1205 printk(KERN_ERR PFX "Failed to switch to core %d\n", core);
1206 return -ENODEV;
1207 }
1208
1209 int bcm43xx_switch_core(struct bcm43xx_private *bcm, struct bcm43xx_coreinfo *new_core)
1210 {
1211 int err;
1212
1213 if (unlikely(!new_core))
1214 return 0;
1215 if (!new_core->available)
1216 return -ENODEV;
1217 if (bcm->current_core == new_core)
1218 return 0;
1219 err = _switch_core(bcm, new_core->index);
1220 if (unlikely(err))
1221 goto out;
1222
1223 bcm->current_core = new_core;
1224 bcm->current_80211_core_idx = -1;
1225 if (new_core->id == BCM43xx_COREID_80211)
1226 bcm->current_80211_core_idx = (int)(new_core - &(bcm->core_80211[0]));
1227
1228 out:
1229 return err;
1230 }
1231
1232 static int bcm43xx_core_enabled(struct bcm43xx_private *bcm)
1233 {
1234 u32 value;
1235
1236 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1237 value &= BCM43xx_SBTMSTATELOW_CLOCK | BCM43xx_SBTMSTATELOW_RESET
1238 | BCM43xx_SBTMSTATELOW_REJECT;
1239
1240 return (value == BCM43xx_SBTMSTATELOW_CLOCK);
1241 }
1242
1243 /* disable current core */
1244 static int bcm43xx_core_disable(struct bcm43xx_private *bcm, u32 core_flags)
1245 {
1246 u32 sbtmstatelow;
1247 u32 sbtmstatehigh;
1248 int i;
1249
1250 /* fetch sbtmstatelow from core information registers */
1251 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1252
1253 /* core is already in reset */
1254 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_RESET)
1255 goto out;
1256
1257 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_CLOCK) {
1258 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1259 BCM43xx_SBTMSTATELOW_REJECT;
1260 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1261
1262 for (i = 0; i < 1000; i++) {
1263 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1264 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_REJECT) {
1265 i = -1;
1266 break;
1267 }
1268 udelay(10);
1269 }
1270 if (i != -1) {
1271 printk(KERN_ERR PFX "Error: core_disable() REJECT timeout!\n");
1272 return -EBUSY;
1273 }
1274
1275 for (i = 0; i < 1000; i++) {
1276 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1277 if (!(sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_BUSY)) {
1278 i = -1;
1279 break;
1280 }
1281 udelay(10);
1282 }
1283 if (i != -1) {
1284 printk(KERN_ERR PFX "Error: core_disable() BUSY timeout!\n");
1285 return -EBUSY;
1286 }
1287
1288 sbtmstatelow = BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1289 BCM43xx_SBTMSTATELOW_REJECT |
1290 BCM43xx_SBTMSTATELOW_RESET |
1291 BCM43xx_SBTMSTATELOW_CLOCK |
1292 core_flags;
1293 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1294 udelay(10);
1295 }
1296
1297 sbtmstatelow = BCM43xx_SBTMSTATELOW_RESET |
1298 BCM43xx_SBTMSTATELOW_REJECT |
1299 core_flags;
1300 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1301
1302 out:
1303 bcm->current_core->enabled = 0;
1304
1305 return 0;
1306 }
1307
1308 /* enable (reset) current core */
1309 static int bcm43xx_core_enable(struct bcm43xx_private *bcm, u32 core_flags)
1310 {
1311 u32 sbtmstatelow;
1312 u32 sbtmstatehigh;
1313 u32 sbimstate;
1314 int err;
1315
1316 err = bcm43xx_core_disable(bcm, core_flags);
1317 if (err)
1318 goto out;
1319
1320 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1321 BCM43xx_SBTMSTATELOW_RESET |
1322 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1323 core_flags;
1324 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1325 udelay(1);
1326
1327 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1328 if (sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_SERROR) {
1329 sbtmstatehigh = 0x00000000;
1330 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATEHIGH, sbtmstatehigh);
1331 }
1332
1333 sbimstate = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMSTATE);
1334 if (sbimstate & (BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT)) {
1335 sbimstate &= ~(BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT);
1336 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMSTATE, sbimstate);
1337 }
1338
1339 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1340 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1341 core_flags;
1342 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1343 udelay(1);
1344
1345 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK | core_flags;
1346 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1347 udelay(1);
1348
1349 bcm->current_core->enabled = 1;
1350 assert(err == 0);
1351 out:
1352 return err;
1353 }
1354
1355 /* http://bcm-specs.sipsolutions.net/80211CoreReset */
1356 void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy)
1357 {
1358 u32 flags = 0x00040000;
1359
1360 if ((bcm43xx_core_enabled(bcm)) &&
1361 !bcm43xx_using_pio(bcm)) {
1362 //FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?
1363 #ifndef CONFIG_BCM947XX
1364 /* reset all used DMA controllers. */
1365 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1366 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA2_BASE);
1367 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA3_BASE);
1368 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1369 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1370 if (bcm->current_core->rev < 5)
1371 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1372 #endif
1373 }
1374 if (bcm->shutting_down) {
1375 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1376 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1377 & ~(BCM43xx_SBF_MAC_ENABLED | 0x00000002));
1378 } else {
1379 if (connect_phy)
1380 flags |= 0x20000000;
1381 bcm43xx_phy_connect(bcm, connect_phy);
1382 bcm43xx_core_enable(bcm, flags);
1383 bcm43xx_write16(bcm, 0x03E6, 0x0000);
1384 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1385 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1386 | BCM43xx_SBF_400);
1387 }
1388 }
1389
1390 static void bcm43xx_wireless_core_disable(struct bcm43xx_private *bcm)
1391 {
1392 bcm43xx_radio_turn_off(bcm);
1393 bcm43xx_write16(bcm, 0x03E6, 0x00F4);
1394 bcm43xx_core_disable(bcm, 0);
1395 }
1396
1397 /* Mark the current 80211 core inactive.
1398 * "active_80211_core" is the other 80211 core, which is used.
1399 */
1400 static int bcm43xx_wireless_core_mark_inactive(struct bcm43xx_private *bcm,
1401 struct bcm43xx_coreinfo *active_80211_core)
1402 {
1403 u32 sbtmstatelow;
1404 struct bcm43xx_coreinfo *old_core;
1405 int err = 0;
1406
1407 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1408 bcm43xx_radio_turn_off(bcm);
1409 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1410 sbtmstatelow &= ~0x200a0000;
1411 sbtmstatelow |= 0xa0000;
1412 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1413 udelay(1);
1414 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1415 sbtmstatelow &= ~0xa0000;
1416 sbtmstatelow |= 0x80000;
1417 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1418 udelay(1);
1419
1420 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G) {
1421 old_core = bcm->current_core;
1422 err = bcm43xx_switch_core(bcm, active_80211_core);
1423 if (err)
1424 goto out;
1425 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1426 sbtmstatelow &= ~0x20000000;
1427 sbtmstatelow |= 0x20000000;
1428 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1429 err = bcm43xx_switch_core(bcm, old_core);
1430 }
1431
1432 out:
1433 return err;
1434 }
1435
1436 static void handle_irq_transmit_status(struct bcm43xx_private *bcm)
1437 {
1438 u32 v0, v1;
1439 u16 tmp;
1440 struct bcm43xx_xmitstatus stat;
1441
1442 while (1) {
1443 v0 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
1444 if (!v0)
1445 break;
1446 v1 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
1447
1448 stat.cookie = (v0 >> 16) & 0x0000FFFF;
1449 tmp = (u16)((v0 & 0xFFF0) | ((v0 & 0xF) >> 1));
1450 stat.flags = tmp & 0xFF;
1451 stat.cnt1 = (tmp & 0x0F00) >> 8;
1452 stat.cnt2 = (tmp & 0xF000) >> 12;
1453 stat.seq = (u16)(v1 & 0xFFFF);
1454 stat.unknown = (u16)((v1 >> 16) & 0xFF);
1455
1456 bcm43xx_debugfs_log_txstat(bcm, &stat);
1457
1458 if (stat.flags & BCM43xx_TXSTAT_FLAG_IGNORE)
1459 continue;
1460 if (!(stat.flags & BCM43xx_TXSTAT_FLAG_ACK)) {
1461 //TODO: packet was not acked (was lost)
1462 }
1463 //TODO: There are more (unknown) flags to test. see bcm43xx_main.h
1464
1465 if (bcm43xx_using_pio(bcm))
1466 bcm43xx_pio_handle_xmitstatus(bcm, &stat);
1467 else
1468 bcm43xx_dma_handle_xmitstatus(bcm, &stat);
1469 }
1470 }
1471
1472 static void bcm43xx_generate_noise_sample(struct bcm43xx_private *bcm)
1473 {
1474 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x408, 0x7F7F);
1475 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x40A, 0x7F7F);
1476 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1477 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD) | (1 << 4));
1478 assert(bcm->noisecalc.core_at_start == bcm->current_core);
1479 assert(bcm->noisecalc.channel_at_start == bcm43xx_current_radio(bcm)->channel);
1480 }
1481
1482 static void bcm43xx_calculate_link_quality(struct bcm43xx_private *bcm)
1483 {
1484 /* Top half of Link Quality calculation. */
1485
1486 if (bcm->noisecalc.calculation_running)
1487 return;
1488 bcm->noisecalc.core_at_start = bcm->current_core;
1489 bcm->noisecalc.channel_at_start = bcm43xx_current_radio(bcm)->channel;
1490 bcm->noisecalc.calculation_running = 1;
1491 bcm->noisecalc.nr_samples = 0;
1492
1493 bcm43xx_generate_noise_sample(bcm);
1494 }
1495
1496 static void handle_irq_noise(struct bcm43xx_private *bcm)
1497 {
1498 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1499 u16 tmp;
1500 u8 noise[4];
1501 u8 i, j;
1502 s32 average;
1503
1504 /* Bottom half of Link Quality calculation. */
1505
1506 assert(bcm->noisecalc.calculation_running);
1507 if (bcm->noisecalc.core_at_start != bcm->current_core ||
1508 bcm->noisecalc.channel_at_start != radio->channel)
1509 goto drop_calculation;
1510 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x408);
1511 noise[0] = (tmp & 0x00FF);
1512 noise[1] = (tmp & 0xFF00) >> 8;
1513 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40A);
1514 noise[2] = (tmp & 0x00FF);
1515 noise[3] = (tmp & 0xFF00) >> 8;
1516 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1517 noise[2] == 0x7F || noise[3] == 0x7F)
1518 goto generate_new;
1519
1520 /* Get the noise samples. */
1521 assert(bcm->noisecalc.nr_samples <= 8);
1522 i = bcm->noisecalc.nr_samples;
1523 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1524 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1525 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1526 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1527 bcm->noisecalc.samples[i][0] = radio->nrssi_lt[noise[0]];
1528 bcm->noisecalc.samples[i][1] = radio->nrssi_lt[noise[1]];
1529 bcm->noisecalc.samples[i][2] = radio->nrssi_lt[noise[2]];
1530 bcm->noisecalc.samples[i][3] = radio->nrssi_lt[noise[3]];
1531 bcm->noisecalc.nr_samples++;
1532 if (bcm->noisecalc.nr_samples == 8) {
1533 /* Calculate the Link Quality by the noise samples. */
1534 average = 0;
1535 for (i = 0; i < 8; i++) {
1536 for (j = 0; j < 4; j++)
1537 average += bcm->noisecalc.samples[i][j];
1538 }
1539 average /= (8 * 4);
1540 average *= 125;
1541 average += 64;
1542 average /= 128;
1543
1544 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40C);
1545 tmp = (tmp / 128) & 0x1F;
1546 if (tmp >= 8)
1547 average += 2;
1548 else
1549 average -= 25;
1550 if (tmp == 8)
1551 average -= 72;
1552 else
1553 average -= 48;
1554
1555 /* FIXME: This is wrong, but people want fancy stats. well... */
1556 bcm->stats.noise = average;
1557 if (average > -65)
1558 bcm->stats.link_quality = 0;
1559 else if (average > -75)
1560 bcm->stats.link_quality = 1;
1561 else if (average > -85)
1562 bcm->stats.link_quality = 2;
1563 else
1564 bcm->stats.link_quality = 3;
1565 // dprintk(KERN_INFO PFX "Link Quality: %u (avg was %d)\n", bcm->stats.link_quality, average);
1566 drop_calculation:
1567 bcm->noisecalc.calculation_running = 0;
1568 return;
1569 }
1570 generate_new:
1571 bcm43xx_generate_noise_sample(bcm);
1572 }
1573
1574 static void handle_irq_ps(struct bcm43xx_private *bcm)
1575 {
1576 if (bcm->ieee->iw_mode == IW_MODE_MASTER) {
1577 ///TODO: PS TBTT
1578 } else {
1579 if (1/*FIXME: the last PSpoll frame was sent successfully */)
1580 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
1581 }
1582 if (bcm->ieee->iw_mode == IW_MODE_ADHOC)
1583 bcm->reg124_set_0x4 = 1;
1584 //FIXME else set to false?
1585 }
1586
1587 static void handle_irq_reg124(struct bcm43xx_private *bcm)
1588 {
1589 if (!bcm->reg124_set_0x4)
1590 return;
1591 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1592 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD)
1593 | 0x4);
1594 //FIXME: reset reg124_set_0x4 to false?
1595 }
1596
1597 static void handle_irq_pmq(struct bcm43xx_private *bcm)
1598 {
1599 u32 tmp;
1600
1601 //TODO: AP mode.
1602
1603 while (1) {
1604 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_PS_STATUS);
1605 if (!(tmp & 0x00000008))
1606 break;
1607 }
1608 /* 16bit write is odd, but correct. */
1609 bcm43xx_write16(bcm, BCM43xx_MMIO_PS_STATUS, 0x0002);
1610 }
1611
1612 static void bcm43xx_generate_beacon_template(struct bcm43xx_private *bcm,
1613 u16 ram_offset, u16 shm_size_offset)
1614 {
1615 u32 value;
1616 u16 size = 0;
1617
1618 /* Timestamp. */
1619 //FIXME: assumption: The chip sets the timestamp
1620 value = 0;
1621 bcm43xx_ram_write(bcm, ram_offset++, value);
1622 bcm43xx_ram_write(bcm, ram_offset++, value);
1623 size += 8;
1624
1625 /* Beacon Interval / Capability Information */
1626 value = 0x0000;//FIXME: Which interval?
1627 value |= (1 << 0) << 16; /* ESS */
1628 value |= (1 << 2) << 16; /* CF Pollable */ //FIXME?
1629 value |= (1 << 3) << 16; /* CF Poll Request */ //FIXME?
1630 if (!bcm->ieee->open_wep)
1631 value |= (1 << 4) << 16; /* Privacy */
1632 bcm43xx_ram_write(bcm, ram_offset++, value);
1633 size += 4;
1634
1635 /* SSID */
1636 //TODO
1637
1638 /* FH Parameter Set */
1639 //TODO
1640
1641 /* DS Parameter Set */
1642 //TODO
1643
1644 /* CF Parameter Set */
1645 //TODO
1646
1647 /* TIM */
1648 //TODO
1649
1650 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, shm_size_offset, size);
1651 }
1652
1653 static void handle_irq_beacon(struct bcm43xx_private *bcm)
1654 {
1655 u32 status;
1656
1657 bcm->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
1658 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD);
1659
1660 if ((status & 0x1) && (status & 0x2)) {
1661 /* ACK beacon IRQ. */
1662 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON,
1663 BCM43xx_IRQ_BEACON);
1664 bcm->irq_savedstate |= BCM43xx_IRQ_BEACON;
1665 return;
1666 }
1667 if (!(status & 0x1)) {
1668 bcm43xx_generate_beacon_template(bcm, 0x68, 0x18);
1669 status |= 0x1;
1670 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1671 }
1672 if (!(status & 0x2)) {
1673 bcm43xx_generate_beacon_template(bcm, 0x468, 0x1A);
1674 status |= 0x2;
1675 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1676 }
1677 }
1678
1679 /* Interrupt handler bottom-half */
1680 static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm)
1681 {
1682 u32 reason;
1683 u32 dma_reason[4];
1684 int activity = 0;
1685 unsigned long flags;
1686
1687 #ifdef CONFIG_BCM43XX_DEBUG
1688 u32 _handled = 0x00000000;
1689 # define bcmirq_handled(irq) do { _handled |= (irq); } while (0)
1690 #else
1691 # define bcmirq_handled(irq) do { /* nothing */ } while (0)
1692 #endif /* CONFIG_BCM43XX_DEBUG*/
1693
1694 bcm43xx_lock_mmio(bcm, flags);
1695 reason = bcm->irq_reason;
1696 dma_reason[0] = bcm->dma_reason[0];
1697 dma_reason[1] = bcm->dma_reason[1];
1698 dma_reason[2] = bcm->dma_reason[2];
1699 dma_reason[3] = bcm->dma_reason[3];
1700
1701 if (unlikely(reason & BCM43xx_IRQ_XMIT_ERROR)) {
1702 /* TX error. We get this when Template Ram is written in wrong endianess
1703 * in dummy_tx(). We also get this if something is wrong with the TX header
1704 * on DMA or PIO queues.
1705 * Maybe we get this in other error conditions, too.
1706 */
1707 printkl(KERN_ERR PFX "FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");
1708 bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR);
1709 }
1710 if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_FATALMASK) |
1711 (dma_reason[1] & BCM43xx_DMAIRQ_FATALMASK) |
1712 (dma_reason[2] & BCM43xx_DMAIRQ_FATALMASK) |
1713 (dma_reason[3] & BCM43xx_DMAIRQ_FATALMASK))) {
1714 printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
1715 "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1716 dma_reason[0], dma_reason[1],
1717 dma_reason[2], dma_reason[3]);
1718 bcm43xx_controller_restart(bcm, "DMA error");
1719 bcm43xx_unlock_mmio(bcm, flags);
1720 return;
1721 }
1722 if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_NONFATALMASK) |
1723 (dma_reason[1] & BCM43xx_DMAIRQ_NONFATALMASK) |
1724 (dma_reason[2] & BCM43xx_DMAIRQ_NONFATALMASK) |
1725 (dma_reason[3] & BCM43xx_DMAIRQ_NONFATALMASK))) {
1726 printkl(KERN_ERR PFX "DMA error: "
1727 "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1728 dma_reason[0], dma_reason[1],
1729 dma_reason[2], dma_reason[3]);
1730 }
1731
1732 if (reason & BCM43xx_IRQ_PS) {
1733 handle_irq_ps(bcm);
1734 bcmirq_handled(BCM43xx_IRQ_PS);
1735 }
1736
1737 if (reason & BCM43xx_IRQ_REG124) {
1738 handle_irq_reg124(bcm);
1739 bcmirq_handled(BCM43xx_IRQ_REG124);
1740 }
1741
1742 if (reason & BCM43xx_IRQ_BEACON) {
1743 if (bcm->ieee->iw_mode == IW_MODE_MASTER)
1744 handle_irq_beacon(bcm);
1745 bcmirq_handled(BCM43xx_IRQ_BEACON);
1746 }
1747
1748 if (reason & BCM43xx_IRQ_PMQ) {
1749 handle_irq_pmq(bcm);
1750 bcmirq_handled(BCM43xx_IRQ_PMQ);
1751 }
1752
1753 if (reason & BCM43xx_IRQ_SCAN) {
1754 /*TODO*/
1755 //bcmirq_handled(BCM43xx_IRQ_SCAN);
1756 }
1757
1758 if (reason & BCM43xx_IRQ_NOISE) {
1759 handle_irq_noise(bcm);
1760 bcmirq_handled(BCM43xx_IRQ_NOISE);
1761 }
1762
1763 /* Check the DMA reason registers for received data. */
1764 assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
1765 assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
1766 if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
1767 if (bcm43xx_using_pio(bcm))
1768 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue0);
1769 else
1770 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring0);
1771 /* We intentionally don't set "activity" to 1, here. */
1772 }
1773 if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
1774 if (bcm43xx_using_pio(bcm))
1775 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue3);
1776 else
1777 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring1);
1778 activity = 1;
1779 }
1780 bcmirq_handled(BCM43xx_IRQ_RX);
1781
1782 if (reason & BCM43xx_IRQ_XMIT_STATUS) {
1783 handle_irq_transmit_status(bcm);
1784 activity = 1;
1785 //TODO: In AP mode, this also causes sending of powersave responses.
1786 bcmirq_handled(BCM43xx_IRQ_XMIT_STATUS);
1787 }
1788
1789 /* IRQ_PIO_WORKAROUND is handled in the top-half. */
1790 bcmirq_handled(BCM43xx_IRQ_PIO_WORKAROUND);
1791 #ifdef CONFIG_BCM43XX_DEBUG
1792 if (unlikely(reason & ~_handled)) {
1793 printkl(KERN_WARNING PFX
1794 "Unhandled IRQ! Reason: 0x%08x, Unhandled: 0x%08x, "
1795 "DMA: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1796 reason, (reason & ~_handled),
1797 dma_reason[0], dma_reason[1],
1798 dma_reason[2], dma_reason[3]);
1799 }
1800 #endif
1801 #undef bcmirq_handled
1802
1803 if (!modparam_noleds)
1804 bcm43xx_leds_update(bcm, activity);
1805 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
1806 bcm43xx_unlock_mmio(bcm, flags);
1807 }
1808
1809 static void pio_irq_workaround(struct bcm43xx_private *bcm,
1810 u16 base, int queueidx)
1811 {
1812 u16 rxctl;
1813
1814 rxctl = bcm43xx_read16(bcm, base + BCM43xx_PIO_RXCTL);
1815 if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
1816 bcm->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
1817 else
1818 bcm->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
1819 }
1820
1821 static void bcm43xx_interrupt_ack(struct bcm43xx_private *bcm, u32 reason)
1822 {
1823 if (bcm43xx_using_pio(bcm) &&
1824 (bcm->current_core->rev < 3) &&
1825 (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
1826 /* Apply a PIO specific workaround to the dma_reasons */
1827 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO1_BASE, 0);
1828 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO2_BASE, 1);
1829 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO3_BASE, 2);
1830 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO4_BASE, 3);
1831 }
1832
1833 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
1834
1835 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,
1836 bcm->dma_reason[0]);
1837 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,
1838 bcm->dma_reason[1]);
1839 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,
1840 bcm->dma_reason[2]);
1841 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,
1842 bcm->dma_reason[3]);
1843 }
1844
1845 /* Interrupt handler top-half */
1846 static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id, struct pt_regs *regs)
1847 {
1848 irqreturn_t ret = IRQ_HANDLED;
1849 struct bcm43xx_private *bcm = dev_id;
1850 u32 reason;
1851
1852 if (!bcm)
1853 return IRQ_NONE;
1854
1855 spin_lock(&bcm->_lock);
1856
1857 reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
1858 if (reason == 0xffffffff) {
1859 /* irq not for us (shared irq) */
1860 ret = IRQ_NONE;
1861 goto out;
1862 }
1863 reason &= bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
1864 if (!reason)
1865 goto out;
1866
1867 bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)
1868 & 0x0001dc00;
1869 bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)
1870 & 0x0000dc00;
1871 bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)
1872 & 0x0000dc00;
1873 bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)
1874 & 0x0001dc00;
1875
1876 bcm43xx_interrupt_ack(bcm, reason);
1877
1878 /* Only accept IRQs, if we are initialized properly.
1879 * This avoids an RX race while initializing.
1880 * We should probably not enable IRQs before we are initialized
1881 * completely, but some careful work is needed to fix this. I think it
1882 * is best to stay with this cheap workaround for now... .
1883 */
1884 if (likely(bcm->initialized)) {
1885 /* disable all IRQs. They are enabled again in the bottom half. */
1886 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1887 /* save the reason code and call our bottom half. */
1888 bcm->irq_reason = reason;
1889 tasklet_schedule(&bcm->isr_tasklet);
1890 }
1891
1892 out:
1893 mmiowb();
1894 spin_unlock(&bcm->_lock);
1895
1896 return ret;
1897 }
1898
1899 static void bcm43xx_release_firmware(struct bcm43xx_private *bcm, int force)
1900 {
1901 if (bcm->firmware_norelease && !force)
1902 return; /* Suspending or controller reset. */
1903 release_firmware(bcm->ucode);
1904 bcm->ucode = NULL;
1905 release_firmware(bcm->pcm);
1906 bcm->pcm = NULL;
1907 release_firmware(bcm->initvals0);
1908 bcm->initvals0 = NULL;
1909 release_firmware(bcm->initvals1);
1910 bcm->initvals1 = NULL;
1911 }
1912
1913 static int bcm43xx_request_firmware(struct bcm43xx_private *bcm)
1914 {
1915 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1916 u8 rev = bcm->current_core->rev;
1917 int err = 0;
1918 int nr;
1919 char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
1920
1921 if (!bcm->ucode) {
1922 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
1923 (rev >= 5 ? 5 : rev),
1924 modparam_fwpostfix);
1925 err = request_firmware(&bcm->ucode, buf, &bcm->pci_dev->dev);
1926 if (err) {
1927 printk(KERN_ERR PFX
1928 "Error: Microcode \"%s\" not available or load failed.\n",
1929 buf);
1930 goto error;
1931 }
1932 }
1933
1934 if (!bcm->pcm) {
1935 snprintf(buf, ARRAY_SIZE(buf),
1936 "bcm43xx_pcm%d%s.fw",
1937 (rev < 5 ? 4 : 5),
1938 modparam_fwpostfix);
1939 err = request_firmware(&bcm->pcm, buf, &bcm->pci_dev->dev);
1940 if (err) {
1941 printk(KERN_ERR PFX
1942 "Error: PCM \"%s\" not available or load failed.\n",
1943 buf);
1944 goto error;
1945 }
1946 }
1947
1948 if (!bcm->initvals0) {
1949 if (rev == 2 || rev == 4) {
1950 switch (phy->type) {
1951 case BCM43xx_PHYTYPE_A:
1952 nr = 3;
1953 break;
1954 case BCM43xx_PHYTYPE_B:
1955 case BCM43xx_PHYTYPE_G:
1956 nr = 1;
1957 break;
1958 default:
1959 goto err_noinitval;
1960 }
1961
1962 } else if (rev >= 5) {
1963 switch (phy->type) {
1964 case BCM43xx_PHYTYPE_A:
1965 nr = 7;
1966 break;
1967 case BCM43xx_PHYTYPE_B:
1968 case BCM43xx_PHYTYPE_G:
1969 nr = 5;
1970 break;
1971 default:
1972 goto err_noinitval;
1973 }
1974 } else
1975 goto err_noinitval;
1976 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
1977 nr, modparam_fwpostfix);
1978
1979 err = request_firmware(&bcm->initvals0, buf, &bcm->pci_dev->dev);
1980 if (err) {
1981 printk(KERN_ERR PFX
1982 "Error: InitVals \"%s\" not available or load failed.\n",
1983 buf);
1984 goto error;
1985 }
1986 if (bcm->initvals0->size % sizeof(struct bcm43xx_initval)) {
1987 printk(KERN_ERR PFX "InitVals fileformat error.\n");
1988 goto error;
1989 }
1990 }
1991
1992 if (!bcm->initvals1) {
1993 if (rev >= 5) {
1994 u32 sbtmstatehigh;
1995
1996 switch (phy->type) {
1997 case BCM43xx_PHYTYPE_A:
1998 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1999 if (sbtmstatehigh & 0x00010000)
2000 nr = 9;
2001 else
2002 nr = 10;
2003 break;
2004 case BCM43xx_PHYTYPE_B:
2005 case BCM43xx_PHYTYPE_G:
2006 nr = 6;
2007 break;
2008 default:
2009 goto err_noinitval;
2010 }
2011 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
2012 nr, modparam_fwpostfix);
2013
2014 err = request_firmware(&bcm->initvals1, buf, &bcm->pci_dev->dev);
2015 if (err) {
2016 printk(KERN_ERR PFX
2017 "Error: InitVals \"%s\" not available or load failed.\n",
2018 buf);
2019 goto error;
2020 }
2021 if (bcm->initvals1->size % sizeof(struct bcm43xx_initval)) {
2022 printk(KERN_ERR PFX "InitVals fileformat error.\n");
2023 goto error;
2024 }
2025 }
2026 }
2027
2028 out:
2029 return err;
2030 error:
2031 bcm43xx_release_firmware(bcm, 1);
2032 goto out;
2033 err_noinitval:
2034 printk(KERN_ERR PFX "Error: No InitVals available!\n");
2035 err = -ENOENT;
2036 goto error;
2037 }
2038
2039 static void bcm43xx_upload_microcode(struct bcm43xx_private *bcm)
2040 {
2041 const u32 *data;
2042 unsigned int i, len;
2043
2044 /* Upload Microcode. */
2045 data = (u32 *)(bcm->ucode->data);
2046 len = bcm->ucode->size / sizeof(u32);
2047 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_UCODE, 0x0000);
2048 for (i = 0; i < len; i++) {
2049 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2050 be32_to_cpu(data[i]));
2051 udelay(10);
2052 }
2053
2054 /* Upload PCM data. */
2055 data = (u32 *)(bcm->pcm->data);
2056 len = bcm->pcm->size / sizeof(u32);
2057 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01ea);
2058 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, 0x00004000);
2059 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01eb);
2060 for (i = 0; i < len; i++) {
2061 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2062 be32_to_cpu(data[i]));
2063 udelay(10);
2064 }
2065 }
2066
2067 static int bcm43xx_write_initvals(struct bcm43xx_private *bcm,
2068 const struct bcm43xx_initval *data,
2069 const unsigned int len)
2070 {
2071 u16 offset, size;
2072 u32 value;
2073 unsigned int i;
2074
2075 for (i = 0; i < len; i++) {
2076 offset = be16_to_cpu(data[i].offset);
2077 size = be16_to_cpu(data[i].size);
2078 value = be32_to_cpu(data[i].value);
2079
2080 if (unlikely(offset >= 0x1000))
2081 goto err_format;
2082 if (size == 2) {
2083 if (unlikely(value & 0xFFFF0000))
2084 goto err_format;
2085 bcm43xx_write16(bcm, offset, (u16)value);
2086 } else if (size == 4) {
2087 bcm43xx_write32(bcm, offset, value);
2088 } else
2089 goto err_format;
2090 }
2091
2092 return 0;
2093
2094 err_format:
2095 printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
2096 "Please fix your bcm43xx firmware files.\n");
2097 return -EPROTO;
2098 }
2099
2100 static int bcm43xx_upload_initvals(struct bcm43xx_private *bcm)
2101 {
2102 int err;
2103
2104 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals0->data,
2105 bcm->initvals0->size / sizeof(struct bcm43xx_initval));
2106 if (err)
2107 goto out;
2108 if (bcm->initvals1) {
2109 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals1->data,
2110 bcm->initvals1->size / sizeof(struct bcm43xx_initval));
2111 if (err)
2112 goto out;
2113 }
2114 out:
2115 return err;
2116 }
2117
2118 static int bcm43xx_initialize_irq(struct bcm43xx_private *bcm)
2119 {
2120 int res;
2121 unsigned int i;
2122 u32 data;
2123
2124 bcm->irq = bcm->pci_dev->irq;
2125 #ifdef CONFIG_BCM947XX
2126 if (bcm->pci_dev->bus->number == 0) {
2127 struct pci_dev *d = NULL;
2128 /* FIXME: we will probably need more device IDs here... */
2129 d = pci_find_device(PCI_VENDOR_ID_BROADCOM, 0x4324, NULL);
2130 if (d != NULL) {
2131 bcm->irq = d->irq;
2132 }
2133 }
2134 #endif
2135 res = request_irq(bcm->irq, bcm43xx_interrupt_handler,
2136 SA_SHIRQ, KBUILD_MODNAME, bcm);
2137 if (res) {
2138 printk(KERN_ERR PFX "Cannot register IRQ%d\n", bcm->irq);
2139 return -ENODEV;
2140 }
2141 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0xffffffff);
2142 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
2143 i = 0;
2144 while (1) {
2145 data = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2146 if (data == BCM43xx_IRQ_READY)
2147 break;
2148 i++;
2149 if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
2150 printk(KERN_ERR PFX "Card IRQ register not responding. "
2151 "Giving up.\n");
2152 free_irq(bcm->irq, bcm);
2153 return -ENODEV;
2154 }
2155 udelay(10);
2156 }
2157 // dummy read
2158 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2159
2160 return 0;
2161 }
2162
2163 /* Switch to the core used to write the GPIO register.
2164 * This is either the ChipCommon, or the PCI core.
2165 */
2166 static int switch_to_gpio_core(struct bcm43xx_private *bcm)
2167 {
2168 int err;
2169
2170 /* Where to find the GPIO register depends on the chipset.
2171 * If it has a ChipCommon, its register at offset 0x6c is the GPIO
2172 * control register. Otherwise the register at offset 0x6c in the
2173 * PCI core is the GPIO control register.
2174 */
2175 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
2176 if (err == -ENODEV) {
2177 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2178 if (unlikely(err == -ENODEV)) {
2179 printk(KERN_ERR PFX "gpio error: "
2180 "Neither ChipCommon nor PCI core available!\n");
2181 }
2182 }
2183
2184 return err;
2185 }
2186
2187 /* Initialize the GPIOs
2188 * http://bcm-specs.sipsolutions.net/GPIO
2189 */
2190 static int bcm43xx_gpio_init(struct bcm43xx_private *bcm)
2191 {
2192 struct bcm43xx_coreinfo *old_core;
2193 int err;
2194 u32 mask, set;
2195
2196 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2197 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2198 & 0xFFFF3FFF);
2199
2200 bcm43xx_leds_switch_all(bcm, 0);
2201 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2202 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK) | 0x000F);
2203
2204 mask = 0x0000001F;
2205 set = 0x0000000F;
2206 if (bcm->chip_id == 0x4301) {
2207 mask |= 0x0060;
2208 set |= 0x0060;
2209 }
2210 if (0 /* FIXME: conditional unknown */) {
2211 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2212 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2213 | 0x0100);
2214 mask |= 0x0180;
2215 set |= 0x0180;
2216 }
2217 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
2218 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2219 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2220 | 0x0200);
2221 mask |= 0x0200;
2222 set |= 0x0200;
2223 }
2224 if (bcm->current_core->rev >= 2)
2225 mask |= 0x0010; /* FIXME: This is redundant. */
2226
2227 old_core = bcm->current_core;
2228 err = switch_to_gpio_core(bcm);
2229 if (err)
2230 goto out;
2231 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL,
2232 (bcm43xx_read32(bcm, BCM43xx_GPIO_CONTROL) & mask) | set);
2233 err = bcm43xx_switch_core(bcm, old_core);
2234 out:
2235 return err;
2236 }
2237
2238 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2239 static int bcm43xx_gpio_cleanup(struct bcm43xx_private *bcm)
2240 {
2241 struct bcm43xx_coreinfo *old_core;
2242 int err;
2243
2244 old_core = bcm->current_core;
2245 err = switch_to_gpio_core(bcm);
2246 if (err)
2247 return err;
2248 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL, 0x00000000);
2249 err = bcm43xx_switch_core(bcm, old_core);
2250 assert(err == 0);
2251
2252 return 0;
2253 }
2254
2255 /* http://bcm-specs.sipsolutions.net/EnableMac */
2256 void bcm43xx_mac_enable(struct bcm43xx_private *bcm)
2257 {
2258 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2259 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2260 | BCM43xx_SBF_MAC_ENABLED);
2261 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_READY);
2262 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
2263 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2264 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
2265 }
2266
2267 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2268 void bcm43xx_mac_suspend(struct bcm43xx_private *bcm)
2269 {
2270 int i;
2271 u32 tmp;
2272
2273 bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
2274 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2275 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2276 & ~BCM43xx_SBF_MAC_ENABLED);
2277 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2278 for (i = 100000; i; i--) {
2279 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2280 if (tmp & BCM43xx_IRQ_READY)
2281 return;
2282 udelay(10);
2283 }
2284 printkl(KERN_ERR PFX "MAC suspend failed\n");
2285 }
2286
2287 void bcm43xx_set_iwmode(struct bcm43xx_private *bcm,
2288 int iw_mode)
2289 {
2290 unsigned long flags;
2291 struct net_device *net_dev = bcm->net_dev;
2292 u32 status;
2293 u16 value;
2294
2295 spin_lock_irqsave(&bcm->ieee->lock, flags);
2296 bcm->ieee->iw_mode = iw_mode;
2297 spin_unlock_irqrestore(&bcm->ieee->lock, flags);
2298 if (iw_mode == IW_MODE_MONITOR)
2299 net_dev->type = ARPHRD_IEEE80211;
2300 else
2301 net_dev->type = ARPHRD_ETHER;
2302
2303 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2304 /* Reset status to infrastructured mode */
2305 status &= ~(BCM43xx_SBF_MODE_AP | BCM43xx_SBF_MODE_MONITOR);
2306 status &= ~BCM43xx_SBF_MODE_PROMISC;
2307 status |= BCM43xx_SBF_MODE_NOTADHOC;
2308
2309 /* FIXME: Always enable promisc mode, until we get the MAC filters working correctly. */
2310 status |= BCM43xx_SBF_MODE_PROMISC;
2311
2312 switch (iw_mode) {
2313 case IW_MODE_MONITOR:
2314 status |= BCM43xx_SBF_MODE_MONITOR;
2315 status |= BCM43xx_SBF_MODE_PROMISC;
2316 break;
2317 case IW_MODE_ADHOC:
2318 status &= ~BCM43xx_SBF_MODE_NOTADHOC;
2319 break;
2320 case IW_MODE_MASTER:
2321 status |= BCM43xx_SBF_MODE_AP;
2322 break;
2323 case IW_MODE_SECOND:
2324 case IW_MODE_REPEAT:
2325 TODO(); /* TODO */
2326 break;
2327 case IW_MODE_INFRA:
2328 /* nothing to be done here... */
2329 break;
2330 default:
2331 dprintk(KERN_ERR PFX "Unknown mode in set_iwmode: %d\n", iw_mode);
2332 }
2333 if (net_dev->flags & IFF_PROMISC)
2334 status |= BCM43xx_SBF_MODE_PROMISC;
2335 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
2336
2337 value = 0x0002;
2338 if (iw_mode != IW_MODE_ADHOC && iw_mode != IW_MODE_MASTER) {
2339 if (bcm->chip_id == 0x4306 && bcm->chip_rev == 3)
2340 value = 0x0064;
2341 else
2342 value = 0x0032;
2343 }
2344 bcm43xx_write16(bcm, 0x0612, value);
2345 }
2346
2347 /* This is the opposite of bcm43xx_chip_init() */
2348 static void bcm43xx_chip_cleanup(struct bcm43xx_private *bcm)
2349 {
2350 bcm43xx_radio_turn_off(bcm);
2351 if (!modparam_noleds)
2352 bcm43xx_leds_exit(bcm);
2353 bcm43xx_gpio_cleanup(bcm);
2354 free_irq(bcm->irq, bcm);
2355 bcm43xx_release_firmware(bcm, 0);
2356 }
2357
2358 /* Initialize the chip
2359 * http://bcm-specs.sipsolutions.net/ChipInit
2360 */
2361 static int bcm43xx_chip_init(struct bcm43xx_private *bcm)
2362 {
2363 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2364 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2365 int err;
2366 int tmp;
2367 u32 value32;
2368 u16 value16;
2369
2370 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2371 BCM43xx_SBF_CORE_READY
2372 | BCM43xx_SBF_400);
2373
2374 err = bcm43xx_request_firmware(bcm);
2375 if (err)
2376 goto out;
2377 bcm43xx_upload_microcode(bcm);
2378
2379 err = bcm43xx_initialize_irq(bcm);
2380 if (err)
2381 goto err_release_fw;
2382
2383 err = bcm43xx_gpio_init(bcm);
2384 if (err)
2385 goto err_free_irq;
2386
2387 err = bcm43xx_upload_initvals(bcm);
2388 if (err)
2389 goto err_gpio_cleanup;
2390 bcm43xx_radio_turn_on(bcm);
2391
2392 bcm43xx_write16(bcm, 0x03E6, 0x0000);
2393 err = bcm43xx_phy_init(bcm);
2394 if (err)
2395 goto err_radio_off;
2396
2397 /* Select initial Interference Mitigation. */
2398 tmp = radio->interfmode;
2399 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2400 bcm43xx_radio_set_interference_mitigation(bcm, tmp);
2401
2402 bcm43xx_phy_set_antenna_diversity(bcm);
2403 bcm43xx_radio_set_txantenna(bcm, BCM43xx_RADIO_TXANTENNA_DEFAULT);
2404 if (phy->type == BCM43xx_PHYTYPE_B) {
2405 value16 = bcm43xx_read16(bcm, 0x005E);
2406 value16 |= 0x0004;
2407 bcm43xx_write16(bcm, 0x005E, value16);
2408 }
2409 bcm43xx_write32(bcm, 0x0100, 0x01000000);
2410 if (bcm->current_core->rev < 5)
2411 bcm43xx_write32(bcm, 0x010C, 0x01000000);
2412
2413 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2414 value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
2415 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2416 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2417 value32 |= BCM43xx_SBF_MODE_NOTADHOC;
2418 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2419
2420 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2421 value32 |= 0x100000;
2422 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2423
2424 if (bcm43xx_using_pio(bcm)) {
2425 bcm43xx_write32(bcm, 0x0210, 0x00000100);
2426 bcm43xx_write32(bcm, 0x0230, 0x00000100);
2427 bcm43xx_write32(bcm, 0x0250, 0x00000100);
2428 bcm43xx_write32(bcm, 0x0270, 0x00000100);
2429 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
2430 }
2431
2432 /* Probe Response Timeout value */
2433 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2434 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
2435
2436 /* Initially set the wireless operation mode. */
2437 bcm43xx_set_iwmode(bcm, bcm->ieee->iw_mode);
2438
2439 if (bcm->current_core->rev < 3) {
2440 bcm43xx_write16(bcm, 0x060E, 0x0000);
2441 bcm43xx_write16(bcm, 0x0610, 0x8000);
2442 bcm43xx_write16(bcm, 0x0604, 0x0000);
2443 bcm43xx_write16(bcm, 0x0606, 0x0200);
2444 } else {
2445 bcm43xx_write32(bcm, 0x0188, 0x80000000);
2446 bcm43xx_write32(bcm, 0x018C, 0x02000000);
2447 }
2448 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
2449 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0001DC00);
2450 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2451 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0000DC00);
2452 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0001DC00);
2453
2454 value32 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
2455 value32 |= 0x00100000;
2456 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, value32);
2457
2458 bcm43xx_write16(bcm, BCM43xx_MMIO_POWERUP_DELAY, bcm43xx_pctl_powerup_delay(bcm));
2459
2460 assert(err == 0);
2461 dprintk(KERN_INFO PFX "Chip initialized\n");
2462 out:
2463 return err;
2464
2465 err_radio_off:
2466 bcm43xx_radio_turn_off(bcm);
2467 err_gpio_cleanup:
2468 bcm43xx_gpio_cleanup(bcm);
2469 err_free_irq:
2470 free_irq(bcm->irq, bcm);
2471 err_release_fw:
2472 bcm43xx_release_firmware(bcm, 1);
2473 goto out;
2474 }
2475
2476 /* Validate chip access
2477 * http://bcm-specs.sipsolutions.net/ValidateChipAccess */
2478 static int bcm43xx_validate_chip(struct bcm43xx_private *bcm)
2479 {
2480 u32 value;
2481 u32 shm_backup;
2482
2483 shm_backup = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000);
2484 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0xAA5555AA);
2485 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0xAA5555AA)
2486 goto error;
2487 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0x55AAAA55);
2488 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0x55AAAA55)
2489 goto error;
2490 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, shm_backup);
2491
2492 value = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2493 if ((value | 0x80000000) != 0x80000400)
2494 goto error;
2495
2496 value = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2497 if (value != 0x00000000)
2498 goto error;
2499
2500 return 0;
2501 error:
2502 printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
2503 return -ENODEV;
2504 }
2505
2506 void bcm43xx_init_struct_phyinfo(struct bcm43xx_phyinfo *phy)
2507 {
2508 /* Initialize a "phyinfo" structure. The structure is already
2509 * zeroed out.
2510 */
2511 phy->antenna_diversity = 0xFFFF;
2512 phy->savedpctlreg = 0xFFFF;
2513 phy->minlowsig[0] = 0xFFFF;
2514 phy->minlowsig[1] = 0xFFFF;
2515 spin_lock_init(&phy->lock);
2516 }
2517
2518 void bcm43xx_init_struct_radioinfo(struct bcm43xx_radioinfo *radio)
2519 {
2520 /* Initialize a "radioinfo" structure. The structure is already
2521 * zeroed out.
2522 */
2523 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2524 radio->channel = 0xFF;
2525 radio->initial_channel = 0xFF;
2526 radio->lofcal = 0xFFFF;
2527 radio->initval = 0xFFFF;
2528 radio->nrssi[0] = -1000;
2529 radio->nrssi[1] = -1000;
2530 }
2531
2532 static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2533 {
2534 int err, i;
2535 int current_core;
2536 u32 core_vendor, core_id, core_rev;
2537 u32 sb_id_hi, chip_id_32 = 0;
2538 u16 pci_device, chip_id_16;
2539 u8 core_count;
2540
2541 memset(&bcm->core_chipcommon, 0, sizeof(struct bcm43xx_coreinfo));
2542 memset(&bcm->core_pci, 0, sizeof(struct bcm43xx_coreinfo));
2543 memset(&bcm->core_80211, 0, sizeof(struct bcm43xx_coreinfo)
2544 * BCM43xx_MAX_80211_CORES);
2545 memset(&bcm->core_80211_ext, 0, sizeof(struct bcm43xx_coreinfo_80211)
2546 * BCM43xx_MAX_80211_CORES);
2547 bcm->current_80211_core_idx = -1;
2548 bcm->nr_80211_available = 0;
2549 bcm->current_core = NULL;
2550 bcm->active_80211_core = NULL;
2551
2552 /* map core 0 */
2553 err = _switch_core(bcm, 0);
2554 if (err)
2555 goto out;
2556
2557 /* fetch sb_id_hi from core information registers */
2558 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2559
2560 core_id = (sb_id_hi & 0xFFF0) >> 4;
2561 core_rev = (sb_id_hi & 0xF);
2562 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2563
2564 /* if present, chipcommon is always core 0; read the chipid from it */
2565 if (core_id == BCM43xx_COREID_CHIPCOMMON) {
2566 chip_id_32 = bcm43xx_read32(bcm, 0);
2567 chip_id_16 = chip_id_32 & 0xFFFF;
2568 bcm->core_chipcommon.available = 1;
2569 bcm->core_chipcommon.id = core_id;
2570 bcm->core_chipcommon.rev = core_rev;
2571 bcm->core_chipcommon.index = 0;
2572 /* While we are at it, also read the capabilities. */
2573 bcm->chipcommon_capabilities = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_CAPABILITIES);
2574 } else {
2575 /* without a chipCommon, use a hard coded table. */
2576 pci_device = bcm->pci_dev->device;
2577 if (pci_device == 0x4301)
2578 chip_id_16 = 0x4301;
2579 else if ((pci_device >= 0x4305) && (pci_device <= 0x4307))
2580 chip_id_16 = 0x4307;
2581 else if ((pci_device >= 0x4402) && (pci_device <= 0x4403))
2582 chip_id_16 = 0x4402;
2583 else if ((pci_device >= 0x4610) && (pci_device <= 0x4615))
2584 chip_id_16 = 0x4610;
2585 else if ((pci_device >= 0x4710) && (pci_device <= 0x4715))
2586 chip_id_16 = 0x4710;
2587 #ifdef CONFIG_BCM947XX
2588 else if ((pci_device >= 0x4320) && (pci_device <= 0x4325))
2589 chip_id_16 = 0x4309;
2590 #endif
2591 else {
2592 printk(KERN_ERR PFX "Could not determine Chip ID\n");
2593 return -ENODEV;
2594 }
2595 }
2596
2597 /* ChipCommon with Core Rev >=4 encodes number of cores,
2598 * otherwise consult hardcoded table */
2599 if ((core_id == BCM43xx_COREID_CHIPCOMMON) && (core_rev >= 4)) {
2600 core_count = (chip_id_32 & 0x0F000000) >> 24;
2601 } else {
2602 switch (chip_id_16) {
2603 case 0x4610:
2604 case 0x4704:
2605 case 0x4710:
2606 core_count = 9;
2607 break;
2608 case 0x4310:
2609 core_count = 8;
2610 break;
2611 case 0x5365:
2612 core_count = 7;
2613 break;
2614 case 0x4306:
2615 core_count = 6;
2616 break;
2617 case 0x4301:
2618 case 0x4307:
2619 core_count = 5;
2620 break;
2621 case 0x4402:
2622 core_count = 3;
2623 break;
2624 default:
2625 /* SOL if we get here */
2626 assert(0);
2627 core_count = 1;
2628 }
2629 }
2630
2631 bcm->chip_id = chip_id_16;
2632 bcm->chip_rev = (chip_id_32 & 0x000f0000) >> 16;
2633
2634 dprintk(KERN_INFO PFX "Chip ID 0x%x, rev 0x%x\n",
2635 bcm->chip_id, bcm->chip_rev);
2636 dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
2637 if (bcm->core_chipcommon.available) {
2638 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2639 core_id, core_rev, core_vendor,
2640 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled");
2641 }
2642
2643 if (bcm->core_chipcommon.available)
2644 current_core = 1;
2645 else
2646 current_core = 0;
2647 for ( ; current_core < core_count; current_core++) {
2648 struct bcm43xx_coreinfo *core;
2649 struct bcm43xx_coreinfo_80211 *ext_80211;
2650
2651 err = _switch_core(bcm, current_core);
2652 if (err)
2653 goto out;
2654 /* Gather information */
2655 /* fetch sb_id_hi from core information registers */
2656 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2657
2658 /* extract core_id, core_rev, core_vendor */
2659 core_id = (sb_id_hi & 0xFFF0) >> 4;
2660 core_rev = (sb_id_hi & 0xF);
2661 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2662
2663 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2664 current_core, core_id, core_rev, core_vendor,
2665 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled" );
2666
2667 core = NULL;
2668 switch (core_id) {
2669 case BCM43xx_COREID_PCI:
2670 core = &bcm->core_pci;
2671 if (core->available) {
2672 printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
2673 continue;
2674 }
2675 break;
2676 case BCM43xx_COREID_80211:
2677 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
2678 core = &(bcm->core_80211[i]);
2679 ext_80211 = &(bcm->core_80211_ext[i]);
2680 if (!core->available)
2681 break;
2682 core = NULL;
2683 }
2684 if (!core) {
2685 printk(KERN_WARNING PFX "More than %d cores of type 802.11 found.\n",
2686 BCM43xx_MAX_80211_CORES);
2687 continue;
2688 }
2689 if (i != 0) {
2690 /* More than one 80211 core is only supported
2691 * by special chips.
2692 * There are chips with two 80211 cores, but with
2693 * dangling pins on the second core. Be careful
2694 * and ignore these cores here.
2695 */
2696 if (bcm->pci_dev->device != 0x4324) {
2697 dprintk(KERN_INFO PFX "Ignoring additional 802.11 core.\n");
2698 continue;
2699 }
2700 }
2701 switch (core_rev) {
2702 case 2:
2703 case 4:
2704 case 5:
2705 case 6:
2706 case 7:
2707 case 9:
2708 break;
2709 default:
2710 printk(KERN_ERR PFX "Error: Unsupported 80211 core revision %u\n",
2711 core_rev);
2712 err = -ENODEV;
2713 goto out;
2714 }
2715 bcm->nr_80211_available++;
2716 bcm43xx_init_struct_phyinfo(&ext_80211->phy);
2717 bcm43xx_init_struct_radioinfo(&ext_80211->radio);
2718 break;
2719 case BCM43xx_COREID_CHIPCOMMON:
2720 printk(KERN_WARNING PFX "Multiple CHIPCOMMON cores found.\n");
2721 break;
2722 }
2723 if (core) {
2724 core->available = 1;
2725 core->id = core_id;
2726 core->rev = core_rev;
2727 core->index = current_core;
2728 }
2729 }
2730
2731 if (!bcm->core_80211[0].available) {
2732 printk(KERN_ERR PFX "Error: No 80211 core found!\n");
2733 err = -ENODEV;
2734 goto out;
2735 }
2736
2737 err = bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
2738
2739 assert(err == 0);
2740 out:
2741 return err;
2742 }
2743
2744 static void bcm43xx_gen_bssid(struct bcm43xx_private *bcm)
2745 {
2746 const u8 *mac = (const u8*)(bcm->net_dev->dev_addr);
2747 u8 *bssid = bcm->ieee->bssid;
2748
2749 switch (bcm->ieee->iw_mode) {
2750 case IW_MODE_ADHOC:
2751 random_ether_addr(bssid);
2752 break;
2753 case IW_MODE_MASTER:
2754 case IW_MODE_INFRA:
2755 case IW_MODE_REPEAT:
2756 case IW_MODE_SECOND:
2757 case IW_MODE_MONITOR:
2758 memcpy(bssid, mac, ETH_ALEN);
2759 break;
2760 default:
2761 assert(0);
2762 }
2763 }
2764
2765 static void bcm43xx_rate_memory_write(struct bcm43xx_private *bcm,
2766 u16 rate,
2767 int is_ofdm)
2768 {
2769 u16 offset;
2770
2771 if (is_ofdm) {
2772 offset = 0x480;
2773 offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2774 }
2775 else {
2776 offset = 0x4C0;
2777 offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2778 }
2779 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, offset + 0x20,
2780 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, offset));
2781 }
2782
2783 static void bcm43xx_rate_memory_init(struct bcm43xx_private *bcm)
2784 {
2785 switch (bcm43xx_current_phy(bcm)->type) {
2786 case BCM43xx_PHYTYPE_A:
2787 case BCM43xx_PHYTYPE_G:
2788 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_6MB, 1);
2789 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_12MB, 1);
2790 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_18MB, 1);
2791 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_24MB, 1);
2792 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_36MB, 1);
2793 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_48MB, 1);
2794 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_54MB, 1);
2795 case BCM43xx_PHYTYPE_B:
2796 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_1MB, 0);
2797 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_2MB, 0);
2798 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_5MB, 0);
2799 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_11MB, 0);
2800 break;
2801 default:
2802 assert(0);
2803 }
2804 }
2805
2806 static void bcm43xx_wireless_core_cleanup(struct bcm43xx_private *bcm)
2807 {
2808 bcm43xx_chip_cleanup(bcm);
2809 bcm43xx_pio_free(bcm);
2810 bcm43xx_dma_free(bcm);
2811
2812 bcm->current_core->initialized = 0;
2813 }
2814
2815 /* http://bcm-specs.sipsolutions.net/80211Init */
2816 static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm)
2817 {
2818 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2819 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2820 u32 ucodeflags;
2821 int err;
2822 u32 sbimconfiglow;
2823 u8 limit;
2824
2825 if (bcm->chip_rev < 5) {
2826 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
2827 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
2828 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
2829 if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
2830 sbimconfiglow |= 0x32;
2831 else if (bcm->bustype == BCM43xx_BUSTYPE_SB)
2832 sbimconfiglow |= 0x53;
2833 else
2834 assert(0);
2835 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
2836 }
2837
2838 bcm43xx_phy_calibrate(bcm);
2839 err = bcm43xx_chip_init(bcm);
2840 if (err)
2841 goto out;
2842
2843 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0016, bcm->current_core->rev);
2844 ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, BCM43xx_UCODEFLAGS_OFFSET);
2845
2846 if (0 /*FIXME: which condition has to be used here? */)
2847 ucodeflags |= 0x00000010;
2848
2849 /* HW decryption needs to be set now */
2850 ucodeflags |= 0x40000000;
2851
2852 if (phy->type == BCM43xx_PHYTYPE_G) {
2853 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2854 if (phy->rev == 1)
2855 ucodeflags |= BCM43xx_UCODEFLAG_UNKGPHY;
2856 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
2857 ucodeflags |= BCM43xx_UCODEFLAG_UNKPACTRL;
2858 } else if (phy->type == BCM43xx_PHYTYPE_B) {
2859 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2860 if (phy->rev >= 2 && radio->version == 0x2050)
2861 ucodeflags &= ~BCM43xx_UCODEFLAG_UNKGPHY;
2862 }
2863
2864 if (ucodeflags != bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2865 BCM43xx_UCODEFLAGS_OFFSET)) {
2866 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
2867 BCM43xx_UCODEFLAGS_OFFSET, ucodeflags);
2868 }
2869
2870 /* Short/Long Retry Limit.
2871 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
2872 * the chip-internal counter.
2873 */
2874 limit = limit_value(modparam_short_retry, 0, 0xF);
2875 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0006, limit);
2876 limit = limit_value(modparam_long_retry, 0, 0xF);
2877 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0007, limit);
2878
2879 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0044, 3);
2880 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0046, 2);
2881
2882 bcm43xx_rate_memory_init(bcm);
2883
2884 /* Minimum Contention Window */
2885 if (phy->type == BCM43xx_PHYTYPE_B)
2886 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000001f);
2887 else
2888 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000000f);
2889 /* Maximum Contention Window */
2890 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
2891
2892 bcm43xx_gen_bssid(bcm);
2893 bcm43xx_write_mac_bssid_templates(bcm);
2894
2895 if (bcm->current_core->rev >= 5)
2896 bcm43xx_write16(bcm, 0x043C, 0x000C);
2897
2898 if (bcm43xx_using_pio(bcm))
2899 err = bcm43xx_pio_init(bcm);
2900 else
2901 err = bcm43xx_dma_init(bcm);
2902 if (err)
2903 goto err_chip_cleanup;
2904 bcm43xx_write16(bcm, 0x0612, 0x0050);
2905 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
2906 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
2907
2908 bcm43xx_mac_enable(bcm);
2909 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
2910
2911 bcm->current_core->initialized = 1;
2912 out:
2913 return err;
2914
2915 err_chip_cleanup:
2916 bcm43xx_chip_cleanup(bcm);
2917 goto out;
2918 }
2919
2920 static int bcm43xx_chipset_attach(struct bcm43xx_private *bcm)
2921 {
2922 int err;
2923 u16 pci_status;
2924
2925 err = bcm43xx_pctl_set_crystal(bcm, 1);
2926 if (err)
2927 goto out;
2928 bcm43xx_pci_read_config16(bcm, PCI_STATUS, &pci_status);
2929 bcm43xx_pci_write_config16(bcm, PCI_STATUS, pci_status & ~PCI_STATUS_SIG_TARGET_ABORT);
2930
2931 out:
2932 return err;
2933 }
2934
2935 static void bcm43xx_chipset_detach(struct bcm43xx_private *bcm)
2936 {
2937 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
2938 bcm43xx_pctl_set_crystal(bcm, 0);
2939 }
2940
2941 static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
2942 u32 address,
2943 u32 data)
2944 {
2945 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_ADDR, address);
2946 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_DATA, data);
2947 }
2948
2949 static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
2950 {
2951 int err;
2952 struct bcm43xx_coreinfo *old_core;
2953
2954 old_core = bcm->current_core;
2955 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2956 if (err)
2957 goto out;
2958
2959 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
2960
2961 bcm43xx_switch_core(bcm, old_core);
2962 assert(err == 0);
2963 out:
2964 return err;
2965 }
2966
2967 /* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
2968 * To enable core 0, pass a core_mask of 1<<0
2969 */
2970 static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
2971 u32 core_mask)
2972 {
2973 u32 backplane_flag_nr;
2974 u32 value;
2975 struct bcm43xx_coreinfo *old_core;
2976 int err = 0;
2977
2978 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTPSFLAG);
2979 backplane_flag_nr = value & BCM43xx_BACKPLANE_FLAG_NR_MASK;
2980
2981 old_core = bcm->current_core;
2982 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2983 if (err)
2984 goto out;
2985
2986 if (bcm->core_pci.rev < 6) {
2987 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
2988 value |= (1 << backplane_flag_nr);
2989 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
2990 } else {
2991 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ICR, &value);
2992 if (err) {
2993 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
2994 goto out_switch_back;
2995 }
2996 value |= core_mask << 8;
2997 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ICR, value);
2998 if (err) {
2999 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3000 goto out_switch_back;
3001 }
3002 }
3003
3004 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3005 value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
3006 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3007
3008 if (bcm->core_pci.rev < 5) {
3009 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
3010 value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
3011 & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
3012 value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
3013 & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
3014 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
3015 err = bcm43xx_pcicore_commit_settings(bcm);
3016 assert(err == 0);
3017 }
3018
3019 out_switch_back:
3020 err = bcm43xx_switch_core(bcm, old_core);
3021 out:
3022 return err;
3023 }
3024
3025 static void bcm43xx_softmac_init(struct bcm43xx_private *bcm)
3026 {
3027 ieee80211softmac_start(bcm->net_dev);
3028 }
3029
3030 static void bcm43xx_periodic_every120sec(struct bcm43xx_private *bcm)
3031 {
3032 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3033
3034 if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
3035 return;
3036
3037 bcm43xx_mac_suspend(bcm);
3038 bcm43xx_phy_lo_g_measure(bcm);
3039 bcm43xx_mac_enable(bcm);
3040 }
3041
3042 static void bcm43xx_periodic_every60sec(struct bcm43xx_private *bcm)
3043 {
3044 bcm43xx_phy_lo_mark_all_unused(bcm);
3045 if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
3046 bcm43xx_mac_suspend(bcm);
3047 bcm43xx_calc_nrssi_slope(bcm);
3048 bcm43xx_mac_enable(bcm);
3049 }
3050 }
3051
3052 static void bcm43xx_periodic_every30sec(struct bcm43xx_private *bcm)
3053 {
3054 /* Update device statistics. */
3055 bcm43xx_calculate_link_quality(bcm);
3056 }
3057
3058 static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
3059 {
3060 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3061 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
3062
3063 if (phy->type == BCM43xx_PHYTYPE_G) {
3064 //TODO: update_aci_moving_average
3065 if (radio->aci_enable && radio->aci_wlan_automatic) {
3066 bcm43xx_mac_suspend(bcm);
3067 if (!radio->aci_enable && 1 /*TODO: not scanning? */) {
3068 if (0 /*TODO: bunch of conditions*/) {
3069 bcm43xx_radio_set_interference_mitigation(bcm,
3070 BCM43xx_RADIO_INTERFMODE_MANUALWLAN);
3071 }
3072 } else if (1/*TODO*/) {
3073 /*
3074 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(bcm))) {
3075 bcm43xx_radio_set_interference_mitigation(bcm,
3076 BCM43xx_RADIO_INTERFMODE_NONE);
3077 }
3078 */
3079 }
3080 bcm43xx_mac_enable(bcm);
3081 } else if (radio->interfmode == BCM43xx_RADIO_INTERFMODE_NONWLAN &&
3082 phy->rev == 1) {
3083 //TODO: implement rev1 workaround
3084 }
3085 }
3086 bcm43xx_phy_xmitpower(bcm); //FIXME: unless scanning?
3087 //TODO for APHY (temperature?)
3088 }
3089
3090 static void bcm43xx_periodic_task_handler(unsigned long d)
3091 {
3092 struct bcm43xx_private *bcm = (struct bcm43xx_private *)d;
3093 unsigned long flags;
3094 unsigned int state;
3095
3096 bcm43xx_lock_mmio(bcm, flags);
3097
3098 assert(bcm->initialized);
3099 state = bcm->periodic_state;
3100 if (state % 8 == 0)
3101 bcm43xx_periodic_every120sec(bcm);
3102 if (state % 4 == 0)
3103 bcm43xx_periodic_every60sec(bcm);
3104 if (state % 2 == 0)
3105 bcm43xx_periodic_every30sec(bcm);
3106 bcm43xx_periodic_every15sec(bcm);
3107 bcm->periodic_state = state + 1;
3108
3109 mod_timer(&bcm->periodic_tasks, jiffies + (HZ * 15));
3110
3111 bcm43xx_unlock_mmio(bcm, flags);
3112 }
3113
3114 static void bcm43xx_periodic_tasks_delete(struct bcm43xx_private *bcm)
3115 {
3116 del_timer_sync(&bcm->periodic_tasks);
3117 }
3118
3119 static void bcm43xx_periodic_tasks_setup(struct bcm43xx_private *bcm)
3120 {
3121 struct timer_list *timer = &(bcm->periodic_tasks);
3122
3123 assert(bcm->initialized);
3124 setup_timer(timer,
3125 bcm43xx_periodic_task_handler,
3126 (unsigned long)bcm);
3127 timer->expires = jiffies;
3128 add_timer(timer);
3129 }
3130
3131 static void bcm43xx_security_init(struct bcm43xx_private *bcm)
3132 {
3133 bcm->security_offset = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
3134 0x0056) * 2;
3135 bcm43xx_clear_keys(bcm);
3136 }
3137
3138 /* This is the opposite of bcm43xx_init_board() */
3139 static void bcm43xx_free_board(struct bcm43xx_private *bcm)
3140 {
3141 int i, err;
3142 unsigned long flags;
3143
3144 bcm43xx_sysfs_unregister(bcm);
3145
3146 bcm43xx_periodic_tasks_delete(bcm);
3147
3148 bcm43xx_lock(bcm, flags);
3149 bcm->initialized = 0;
3150 bcm->shutting_down = 1;
3151 bcm43xx_unlock(bcm, flags);
3152
3153 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3154 if (!bcm->core_80211[i].available)
3155 continue;
3156 if (!bcm->core_80211[i].initialized)
3157 continue;
3158
3159 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3160 assert(err == 0);
3161 bcm43xx_wireless_core_cleanup(bcm);
3162 }
3163
3164 bcm43xx_pctl_set_crystal(bcm, 0);
3165
3166 bcm43xx_lock(bcm, flags);
3167 bcm->shutting_down = 0;
3168 bcm43xx_unlock(bcm, flags);
3169 }
3170
3171 static int bcm43xx_init_board(struct bcm43xx_private *bcm)
3172 {
3173 int i, err;
3174 int connect_phy;
3175 unsigned long flags;
3176
3177 might_sleep();
3178
3179 bcm43xx_lock(bcm, flags);
3180 bcm->initialized = 0;
3181 bcm->shutting_down = 0;
3182 bcm43xx_unlock(bcm, flags);
3183
3184 err = bcm43xx_pctl_set_crystal(bcm, 1);
3185 if (err)
3186 goto out;
3187 err = bcm43xx_pctl_init(bcm);
3188 if (err)
3189 goto err_crystal_off;
3190 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_FAST);
3191 if (err)
3192 goto err_crystal_off;
3193
3194 tasklet_enable(&bcm->isr_tasklet);
3195 for (i = 0; i < bcm->nr_80211_available; i++) {
3196 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3197 assert(err != -ENODEV);
3198 if (err)
3199 goto err_80211_unwind;
3200
3201 /* Enable the selected wireless core.
3202 * Connect PHY only on the first core.
3203 */
3204 if (!bcm43xx_core_enabled(bcm)) {
3205 if (bcm->nr_80211_available == 1) {
3206 connect_phy = bcm43xx_current_phy(bcm)->connected;
3207 } else {
3208 if (i == 0)
3209 connect_phy = 1;
3210 else
3211 connect_phy = 0;
3212 }
3213 bcm43xx_wireless_core_reset(bcm, connect_phy);
3214 }
3215
3216 if (i != 0)
3217 bcm43xx_wireless_core_mark_inactive(bcm, &bcm->core_80211[0]);
3218
3219 err = bcm43xx_wireless_core_init(bcm);
3220 if (err)
3221 goto err_80211_unwind;
3222
3223 if (i != 0) {
3224 bcm43xx_mac_suspend(bcm);
3225 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3226 bcm43xx_radio_turn_off(bcm);
3227 }
3228 }
3229 bcm->active_80211_core = &bcm->core_80211[0];
3230 if (bcm->nr_80211_available >= 2) {
3231 bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
3232 bcm43xx_mac_enable(bcm);
3233 }
3234 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
3235 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_SELF, (u8 *)(bcm->net_dev->dev_addr));
3236 dprintk(KERN_INFO PFX "80211 cores initialized\n");
3237 bcm43xx_security_init(bcm);
3238 bcm43xx_softmac_init(bcm);
3239
3240 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_DYNAMIC);
3241
3242 if (bcm43xx_current_radio(bcm)->initial_channel != 0xFF) {
3243 bcm43xx_mac_suspend(bcm);
3244 bcm43xx_radio_selectchannel(bcm, bcm43xx_current_radio(bcm)->initial_channel, 0);
3245 bcm43xx_mac_enable(bcm);
3246 }
3247
3248 /* Initialization of the board is done. Flag it as such. */
3249 bcm43xx_lock(bcm, flags);
3250 bcm->initialized = 1;
3251 bcm43xx_unlock(bcm, flags);
3252
3253 bcm43xx_periodic_tasks_setup(bcm);
3254 bcm43xx_sysfs_register(bcm);
3255 //FIXME: check for bcm43xx_sysfs_register failure. This function is a bit messy regarding unwinding, though...
3256
3257 assert(err == 0);
3258 out:
3259 return err;
3260
3261 err_80211_unwind:
3262 tasklet_disable(&bcm->isr_tasklet);
3263 /* unwind all 80211 initialization */
3264 for (i = 0; i < bcm->nr_80211_available; i++) {
3265 if (!bcm->core_80211[i].initialized)
3266 continue;
3267 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3268 bcm43xx_wireless_core_cleanup(bcm);
3269 }
3270 err_crystal_off:
3271 bcm43xx_pctl_set_crystal(bcm, 0);
3272 goto out;
3273 }
3274
3275 static void bcm43xx_detach_board(struct bcm43xx_private *bcm)
3276 {
3277 struct pci_dev *pci_dev = bcm->pci_dev;
3278 int i;
3279
3280 bcm43xx_chipset_detach(bcm);
3281 /* Do _not_ access the chip, after it is detached. */
3282 iounmap(bcm->mmio_addr);
3283
3284 pci_release_regions(pci_dev);
3285 pci_disable_device(pci_dev);
3286
3287 /* Free allocated structures/fields */
3288 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3289 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3290 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3291 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3292 }
3293 }
3294
3295 static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3296 {
3297 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3298 u16 value;
3299 u8 phy_version;
3300 u8 phy_type;
3301 u8 phy_rev;
3302 int phy_rev_ok = 1;
3303 void *p;
3304
3305 value = bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER);
3306
3307 phy_version = (value & 0xF000) >> 12;
3308 phy_type = (value & 0x0F00) >> 8;
3309 phy_rev = (value & 0x000F);
3310
3311 dprintk(KERN_INFO PFX "Detected PHY: Version: %x, Type %x, Revision %x\n",
3312 phy_version, phy_type, phy_rev);
3313
3314 switch (phy_type) {
3315 case BCM43xx_PHYTYPE_A:
3316 if (phy_rev >= 4)
3317 phy_rev_ok = 0;
3318 /*FIXME: We need to switch the ieee->modulation, etc.. flags,
3319 * if we switch 80211 cores after init is done.
3320 * As we do not implement on the fly switching between
3321 * wireless cores, I will leave this as a future task.
3322 */
3323 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION;
3324 bcm->ieee->mode = IEEE_A;
3325 bcm->ieee->freq_band = IEEE80211_52GHZ_BAND |
3326 IEEE80211_24GHZ_BAND;
3327 break;
3328 case BCM43xx_PHYTYPE_B:
3329 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
3330 phy_rev_ok = 0;
3331 bcm->ieee->modulation = IEEE80211_CCK_MODULATION;
3332 bcm->ieee->mode = IEEE_B;
3333 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3334 break;
3335 case BCM43xx_PHYTYPE_G:
3336 if (phy_rev > 7)
3337 phy_rev_ok = 0;
3338 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
3339 IEEE80211_CCK_MODULATION;
3340 bcm->ieee->mode = IEEE_G;
3341 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3342 break;
3343 default:
3344 printk(KERN_ERR PFX "Error: Unknown PHY Type %x\n",
3345 phy_type);
3346 return -ENODEV;
3347 };
3348 if (!phy_rev_ok) {
3349 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
3350 phy_rev);
3351 }
3352
3353 phy->version = phy_version;
3354 phy->type = phy_type;
3355 phy->rev = phy_rev;
3356 if ((phy_type == BCM43xx_PHYTYPE_B) || (phy_type == BCM43xx_PHYTYPE_G)) {
3357 p = kzalloc(sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT,
3358 GFP_KERNEL);
3359 if (!p)
3360 return -ENOMEM;
3361 phy->_lo_pairs = p;
3362 }
3363
3364 return 0;
3365 }
3366
3367 static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
3368 {
3369 struct pci_dev *pci_dev = bcm->pci_dev;
3370 struct net_device *net_dev = bcm->net_dev;
3371 int err;
3372 int i;
3373 unsigned long mmio_start, mmio_flags, mmio_len;
3374 u32 coremask;
3375
3376 err = pci_enable_device(pci_dev);
3377 if (err) {
3378 printk(KERN_ERR PFX "unable to wake up pci device (%i)\n", err);
3379 goto out;
3380 }
3381 mmio_start = pci_resource_start(pci_dev, 0);
3382 mmio_flags = pci_resource_flags(pci_dev, 0);
3383 mmio_len = pci_resource_len(pci_dev, 0);
3384 if (!(mmio_flags & IORESOURCE_MEM)) {
3385 printk(KERN_ERR PFX
3386 "%s, region #0 not an MMIO resource, aborting\n",
3387 pci_name(pci_dev));
3388 err = -ENODEV;
3389 goto err_pci_disable;
3390 }
3391 err = pci_request_regions(pci_dev, KBUILD_MODNAME);
3392 if (err) {
3393 printk(KERN_ERR PFX
3394 "could not access PCI resources (%i)\n", err);
3395 goto err_pci_disable;
3396 }
3397 /* enable PCI bus-mastering */
3398 pci_set_master(pci_dev);
3399 bcm->mmio_addr = ioremap(mmio_start, mmio_len);
3400 if (!bcm->mmio_addr) {
3401 printk(KERN_ERR PFX "%s: cannot remap MMIO, aborting\n",
3402 pci_name(pci_dev));
3403 err = -EIO;
3404 goto err_pci_release;
3405 }
3406 bcm->mmio_len = mmio_len;
3407 net_dev->base_addr = (unsigned long)bcm->mmio_addr;
3408
3409 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_VENDOR_ID,
3410 &bcm->board_vendor);
3411 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_ID,
3412 &bcm->board_type);
3413 bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
3414 &bcm->board_revision);
3415
3416 err = bcm43xx_chipset_attach(bcm);
3417 if (err)
3418 goto err_iounmap;
3419 err = bcm43xx_pctl_init(bcm);
3420 if (err)
3421 goto err_chipset_detach;
3422 err = bcm43xx_probe_cores(bcm);
3423 if (err)
3424 goto err_chipset_detach;
3425
3426 /* Attach all IO cores to the backplane. */
3427 coremask = 0;
3428 for (i = 0; i < bcm->nr_80211_available; i++)
3429 coremask |= (1 << bcm->core_80211[i].index);
3430 //FIXME: Also attach some non80211 cores?
3431 err = bcm43xx_setup_backplane_pci_connection(bcm, coremask);
3432 if (err) {
3433 printk(KERN_ERR PFX "Backplane->PCI connection failed!\n");
3434 goto err_chipset_detach;
3435 }
3436
3437 err = bcm43xx_sprom_extract(bcm);
3438 if (err)
3439 goto err_chipset_detach;
3440 err = bcm43xx_leds_init(bcm);
3441 if (err)
3442 goto err_chipset_detach;
3443
3444 for (i = 0; i < bcm->nr_80211_available; i++) {
3445 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3446 assert(err != -ENODEV);
3447 if (err)
3448 goto err_80211_unwind;
3449
3450 /* Enable the selected wireless core.
3451 * Connect PHY only on the first core.
3452 */
3453 bcm43xx_wireless_core_reset(bcm, (i == 0));
3454
3455 err = bcm43xx_read_phyinfo(bcm);
3456 if (err && (i == 0))
3457 goto err_80211_unwind;
3458
3459 err = bcm43xx_read_radioinfo(bcm);
3460 if (err && (i == 0))
3461 goto err_80211_unwind;
3462
3463 err = bcm43xx_validate_chip(bcm);
3464 if (err && (i == 0))
3465 goto err_80211_unwind;
3466
3467 bcm43xx_radio_turn_off(bcm);
3468 err = bcm43xx_phy_init_tssi2dbm_table(bcm);
3469 if (err)
3470 goto err_80211_unwind;
3471 bcm43xx_wireless_core_disable(bcm);
3472 }
3473 bcm43xx_pctl_set_crystal(bcm, 0);
3474
3475 /* Set the MAC address in the networking subsystem */
3476 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_A)
3477 memcpy(bcm->net_dev->dev_addr, bcm->sprom.et1macaddr, 6);
3478 else
3479 memcpy(bcm->net_dev->dev_addr, bcm->sprom.il0macaddr, 6);
3480
3481 bcm43xx_geo_init(bcm);
3482
3483 snprintf(bcm->nick, IW_ESSID_MAX_SIZE,
3484 "Broadcom %04X", bcm->chip_id);
3485
3486 assert(err == 0);
3487 out:
3488 return err;
3489
3490 err_80211_unwind:
3491 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3492 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3493 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3494 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3495 }
3496 err_chipset_detach:
3497 bcm43xx_chipset_detach(bcm);
3498 err_iounmap:
3499 iounmap(bcm->mmio_addr);
3500 err_pci_release:
3501 pci_release_regions(pci_dev);
3502 err_pci_disable:
3503 pci_disable_device(pci_dev);
3504 goto out;
3505 }
3506
3507 /* Do the Hardware IO operations to send the txb */
3508 static inline int bcm43xx_tx(struct bcm43xx_private *bcm,
3509 struct ieee80211_txb *txb)
3510 {
3511 int err = -ENODEV;
3512
3513 if (bcm43xx_using_pio(bcm))
3514 err = bcm43xx_pio_tx(bcm, txb);
3515 else
3516 err = bcm43xx_dma_tx(bcm, txb);
3517
3518 return err;
3519 }
3520
3521 static void bcm43xx_ieee80211_set_chan(struct net_device *net_dev,
3522 u8 channel)
3523 {
3524 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3525 unsigned long flags;
3526
3527 bcm43xx_lock_mmio(bcm, flags);
3528 bcm43xx_mac_suspend(bcm);
3529 bcm43xx_radio_selectchannel(bcm, channel, 0);
3530 bcm43xx_mac_enable(bcm);
3531 bcm43xx_unlock_mmio(bcm, flags);
3532 }
3533
3534 /* set_security() callback in struct ieee80211_device */
3535 static void bcm43xx_ieee80211_set_security(struct net_device *net_dev,
3536 struct ieee80211_security *sec)
3537 {
3538 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3539 struct ieee80211_security *secinfo = &bcm->ieee->sec;
3540 unsigned long flags;
3541 int keyidx;
3542
3543 dprintk(KERN_INFO PFX "set security called\n");
3544
3545 bcm43xx_lock_mmio(bcm, flags);
3546
3547 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++)
3548 if (sec->flags & (1<<keyidx)) {
3549 secinfo->encode_alg[keyidx] = sec->encode_alg[keyidx];
3550 secinfo->key_sizes[keyidx] = sec->key_sizes[keyidx];
3551 memcpy(secinfo->keys[keyidx], sec->keys[keyidx], SCM_KEY_LEN);
3552 }
3553
3554 if (sec->flags & SEC_ACTIVE_KEY) {
3555 secinfo->active_key = sec->active_key;
3556 dprintk(KERN_INFO PFX " .active_key = %d\n", sec->active_key);
3557 }
3558 if (sec->flags & SEC_UNICAST_GROUP) {
3559 secinfo->unicast_uses_group = sec->unicast_uses_group;
3560 dprintk(KERN_INFO PFX " .unicast_uses_group = %d\n", sec->unicast_uses_group);
3561 }
3562 if (sec->flags & SEC_LEVEL) {
3563 secinfo->level = sec->level;
3564 dprintk(KERN_INFO PFX " .level = %d\n", sec->level);
3565 }
3566 if (sec->flags & SEC_ENABLED) {
3567 secinfo->enabled = sec->enabled;
3568 dprintk(KERN_INFO PFX " .enabled = %d\n", sec->enabled);
3569 }
3570 if (sec->flags & SEC_ENCRYPT) {
3571 secinfo->encrypt = sec->encrypt;
3572 dprintk(KERN_INFO PFX " .encrypt = %d\n", sec->encrypt);
3573 }
3574 if (bcm->initialized && !bcm->ieee->host_encrypt) {
3575 if (secinfo->enabled) {
3576 /* upload WEP keys to hardware */
3577 char null_address[6] = { 0 };
3578 u8 algorithm = 0;
3579 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++) {
3580 if (!(sec->flags & (1<<keyidx)))
3581 continue;
3582 switch (sec->encode_alg[keyidx]) {
3583 case SEC_ALG_NONE: algorithm = BCM43xx_SEC_ALGO_NONE; break;
3584 case SEC_ALG_WEP:
3585 algorithm = BCM43xx_SEC_ALGO_WEP;
3586 if (secinfo->key_sizes[keyidx] == 13)
3587 algorithm = BCM43xx_SEC_ALGO_WEP104;
3588 break;
3589 case SEC_ALG_TKIP:
3590 FIXME();
3591 algorithm = BCM43xx_SEC_ALGO_TKIP;
3592 break;
3593 case SEC_ALG_CCMP:
3594 FIXME();
3595 algorithm = BCM43xx_SEC_ALGO_AES;
3596 break;
3597 default:
3598 assert(0);
3599 break;
3600 }
3601 bcm43xx_key_write(bcm, keyidx, algorithm, sec->keys[keyidx], secinfo->key_sizes[keyidx], &null_address[0]);
3602 bcm->key[keyidx].enabled = 1;
3603 bcm->key[keyidx].algorithm = algorithm;
3604 }
3605 } else
3606 bcm43xx_clear_keys(bcm);
3607 }
3608 bcm43xx_unlock_mmio(bcm, flags);
3609 }
3610
3611 /* hard_start_xmit() callback in struct ieee80211_device */
3612 static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb *txb,
3613 struct net_device *net_dev,
3614 int pri)
3615 {
3616 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3617 int err = -ENODEV;
3618 unsigned long flags;
3619
3620 bcm43xx_lock_mmio(bcm, flags);
3621 if (likely(bcm->initialized))
3622 err = bcm43xx_tx(bcm, txb);
3623 bcm43xx_unlock_mmio(bcm, flags);
3624
3625 return err;
3626 }
3627
3628 static struct net_device_stats * bcm43xx_net_get_stats(struct net_device *net_dev)
3629 {
3630 return &(bcm43xx_priv(net_dev)->ieee->stats);
3631 }
3632
3633 static void bcm43xx_net_tx_timeout(struct net_device *net_dev)
3634 {
3635 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3636 unsigned long flags;
3637
3638 bcm43xx_lock_mmio(bcm, flags);
3639 bcm43xx_controller_restart(bcm, "TX timeout");
3640 bcm43xx_unlock_mmio(bcm, flags);
3641 }
3642
3643 #ifdef CONFIG_NET_POLL_CONTROLLER
3644 static void bcm43xx_net_poll_controller(struct net_device *net_dev)
3645 {
3646 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3647 unsigned long flags;
3648
3649 local_irq_save(flags);
3650 bcm43xx_interrupt_handler(bcm->irq, bcm, NULL);
3651 local_irq_restore(flags);
3652 }
3653 #endif /* CONFIG_NET_POLL_CONTROLLER */
3654
3655 static int bcm43xx_net_open(struct net_device *net_dev)
3656 {
3657 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3658
3659 return bcm43xx_init_board(bcm);
3660 }
3661
3662 static int bcm43xx_net_stop(struct net_device *net_dev)
3663 {
3664 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3665
3666 ieee80211softmac_stop(net_dev);
3667 bcm43xx_disable_interrupts_sync(bcm, NULL);
3668 bcm43xx_free_board(bcm);
3669
3670 return 0;
3671 }
3672
3673 static int bcm43xx_init_private(struct bcm43xx_private *bcm,
3674 struct net_device *net_dev,
3675 struct pci_dev *pci_dev)
3676 {
3677 int err;
3678
3679 bcm->ieee = netdev_priv(net_dev);
3680 bcm->softmac = ieee80211_priv(net_dev);
3681 bcm->softmac->set_channel = bcm43xx_ieee80211_set_chan;
3682
3683 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3684 bcm->pci_dev = pci_dev;
3685 bcm->net_dev = net_dev;
3686 bcm->bad_frames_preempt = modparam_bad_frames_preempt;
3687 spin_lock_init(&bcm->_lock);
3688 tasklet_init(&bcm->isr_tasklet,
3689 (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
3690 (unsigned long)bcm);
3691 tasklet_disable_nosync(&bcm->isr_tasklet);
3692 if (modparam_pio) {
3693 bcm->__using_pio = 1;
3694 } else {
3695 err = pci_set_dma_mask(pci_dev, DMA_30BIT_MASK);
3696 err |= pci_set_consistent_dma_mask(pci_dev, DMA_30BIT_MASK);
3697 if (err) {
3698 #ifdef CONFIG_BCM43XX_PIO
3699 printk(KERN_WARNING PFX "DMA not supported. Falling back to PIO.\n");
3700 bcm->__using_pio = 1;
3701 #else
3702 printk(KERN_ERR PFX "FATAL: DMA not supported and PIO not configured. "
3703 "Recompile the driver with PIO support, please.\n");
3704 return -ENODEV;
3705 #endif /* CONFIG_BCM43XX_PIO */
3706 }
3707 }
3708 bcm->rts_threshold = BCM43xx_DEFAULT_RTS_THRESHOLD;
3709
3710 /* default to sw encryption for now */
3711 bcm->ieee->host_build_iv = 0;
3712 bcm->ieee->host_encrypt = 1;
3713 bcm->ieee->host_decrypt = 1;
3714
3715 bcm->ieee->iw_mode = BCM43xx_INITIAL_IWMODE;
3716 bcm->ieee->tx_headroom = sizeof(struct bcm43xx_txhdr);
3717 bcm->ieee->set_security = bcm43xx_ieee80211_set_security;
3718 bcm->ieee->hard_start_xmit = bcm43xx_ieee80211_hard_start_xmit;
3719
3720 return 0;
3721 }
3722
3723 static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
3724 const struct pci_device_id *ent)
3725 {
3726 struct net_device *net_dev;
3727 struct bcm43xx_private *bcm;
3728 int err;
3729
3730 #ifdef CONFIG_BCM947XX
3731 if ((pdev->bus->number == 0) && (pdev->device != 0x0800))
3732 return -ENODEV;
3733 #endif
3734
3735 #ifdef DEBUG_SINGLE_DEVICE_ONLY
3736 if (strcmp(pci_name(pdev), DEBUG_SINGLE_DEVICE_ONLY))
3737 return -ENODEV;
3738 #endif
3739
3740 net_dev = alloc_ieee80211softmac(sizeof(*bcm));
3741 if (!net_dev) {
3742 printk(KERN_ERR PFX
3743 "could not allocate ieee80211 device %s\n",
3744 pci_name(pdev));
3745 err = -ENOMEM;
3746 goto out;
3747 }
3748 /* initialize the net_device struct */
3749 SET_MODULE_OWNER(net_dev);
3750 SET_NETDEV_DEV(net_dev, &pdev->dev);
3751
3752 net_dev->open = bcm43xx_net_open;
3753 net_dev->stop = bcm43xx_net_stop;
3754 net_dev->get_stats = bcm43xx_net_get_stats;
3755 net_dev->tx_timeout = bcm43xx_net_tx_timeout;
3756 #ifdef CONFIG_NET_POLL_CONTROLLER
3757 net_dev->poll_controller = bcm43xx_net_poll_controller;
3758 #endif
3759 net_dev->wireless_handlers = &bcm43xx_wx_handlers_def;
3760 net_dev->irq = pdev->irq;
3761 SET_ETHTOOL_OPS(net_dev, &bcm43xx_ethtool_ops);
3762
3763 /* initialize the bcm43xx_private struct */
3764 bcm = bcm43xx_priv(net_dev);
3765 memset(bcm, 0, sizeof(*bcm));
3766 err = bcm43xx_init_private(bcm, net_dev, pdev);
3767 if (err)
3768 goto err_free_netdev;
3769
3770 pci_set_drvdata(pdev, net_dev);
3771
3772 err = bcm43xx_attach_board(bcm);
3773 if (err)
3774 goto err_free_netdev;
3775
3776 err = register_netdev(net_dev);
3777 if (err) {
3778 printk(KERN_ERR PFX "Cannot register net device, "
3779 "aborting.\n");
3780 err = -ENOMEM;
3781 goto err_detach_board;
3782 }
3783
3784 bcm43xx_debugfs_add_device(bcm);
3785
3786 assert(err == 0);
3787 out:
3788 return err;
3789
3790 err_detach_board:
3791 bcm43xx_detach_board(bcm);
3792 err_free_netdev:
3793 free_ieee80211softmac(net_dev);
3794 goto out;
3795 }
3796
3797 static void __devexit bcm43xx_remove_one(struct pci_dev *pdev)
3798 {
3799 struct net_device *net_dev = pci_get_drvdata(pdev);
3800 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3801
3802 bcm43xx_debugfs_remove_device(bcm);
3803 unregister_netdev(net_dev);
3804 bcm43xx_detach_board(bcm);
3805 assert(bcm->ucode == NULL);
3806 free_ieee80211softmac(net_dev);
3807 }
3808
3809 /* Hard-reset the chip. Do not call this directly.
3810 * Use bcm43xx_controller_restart()
3811 */
3812 static void bcm43xx_chip_reset(void *_bcm)
3813 {
3814 struct bcm43xx_private *bcm = _bcm;
3815 struct net_device *net_dev = bcm->net_dev;
3816 struct pci_dev *pci_dev = bcm->pci_dev;
3817 int err;
3818 int was_initialized = bcm->initialized;
3819
3820 netif_stop_queue(bcm->net_dev);
3821 tasklet_disable(&bcm->isr_tasklet);
3822
3823 bcm->firmware_norelease = 1;
3824 if (was_initialized)
3825 bcm43xx_free_board(bcm);
3826 bcm->firmware_norelease = 0;
3827 bcm43xx_detach_board(bcm);
3828 err = bcm43xx_init_private(bcm, net_dev, pci_dev);
3829 if (err)
3830 goto failure;
3831 err = bcm43xx_attach_board(bcm);
3832 if (err)
3833 goto failure;
3834 if (was_initialized) {
3835 err = bcm43xx_init_board(bcm);
3836 if (err)
3837 goto failure;
3838 }
3839 netif_wake_queue(bcm->net_dev);
3840 printk(KERN_INFO PFX "Controller restarted\n");
3841
3842 return;
3843 failure:
3844 printk(KERN_ERR PFX "Controller restart failed\n");
3845 }
3846
3847 /* Hard-reset the chip.
3848 * This can be called from interrupt or process context.
3849 * Make sure to _not_ re-enable device interrupts after this has been called.
3850 */
3851 void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason)
3852 {
3853 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3854 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
3855 printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
3856 INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset, bcm);
3857 schedule_work(&bcm->restart_work);
3858 }
3859
3860 #ifdef CONFIG_PM
3861
3862 static int bcm43xx_suspend(struct pci_dev *pdev, pm_message_t state)
3863 {
3864 struct net_device *net_dev = pci_get_drvdata(pdev);
3865 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3866 unsigned long flags;
3867 int try_to_shutdown = 0, err;
3868
3869 dprintk(KERN_INFO PFX "Suspending...\n");
3870
3871 bcm43xx_lock(bcm, flags);
3872 bcm->was_initialized = bcm->initialized;
3873 if (bcm->initialized)
3874 try_to_shutdown = 1;
3875 bcm43xx_unlock(bcm, flags);
3876
3877 netif_device_detach(net_dev);
3878 if (try_to_shutdown) {
3879 ieee80211softmac_stop(net_dev);
3880 err = bcm43xx_disable_interrupts_sync(bcm, &bcm->irq_savedstate);
3881 if (unlikely(err)) {
3882 dprintk(KERN_ERR PFX "Suspend failed.\n");
3883 return -EAGAIN;
3884 }
3885 bcm->firmware_norelease = 1;
3886 bcm43xx_free_board(bcm);
3887 bcm->firmware_norelease = 0;
3888 }
3889 bcm43xx_chipset_detach(bcm);
3890
3891 pci_save_state(pdev);
3892 pci_disable_device(pdev);
3893 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3894
3895 dprintk(KERN_INFO PFX "Device suspended.\n");
3896
3897 return 0;
3898 }
3899
3900 static int bcm43xx_resume(struct pci_dev *pdev)
3901 {
3902 struct net_device *net_dev = pci_get_drvdata(pdev);
3903 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3904 int err = 0;
3905
3906 dprintk(KERN_INFO PFX "Resuming...\n");
3907
3908 pci_set_power_state(pdev, 0);
3909 pci_enable_device(pdev);
3910 pci_restore_state(pdev);
3911
3912 bcm43xx_chipset_attach(bcm);
3913 if (bcm->was_initialized) {
3914 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3915 err = bcm43xx_init_board(bcm);
3916 }
3917 if (err) {
3918 printk(KERN_ERR PFX "Resume failed!\n");
3919 return err;
3920 }
3921
3922 netif_device_attach(net_dev);
3923
3924 /*FIXME: This should be handled by softmac instead. */
3925 schedule_work(&bcm->softmac->associnfo.work);
3926
3927 dprintk(KERN_INFO PFX "Device resumed.\n");
3928
3929 return 0;
3930 }
3931
3932 #endif /* CONFIG_PM */
3933
3934 static struct pci_driver bcm43xx_pci_driver = {
3935 .name = KBUILD_MODNAME,
3936 .id_table = bcm43xx_pci_tbl,
3937 .probe = bcm43xx_init_one,
3938 .remove = __devexit_p(bcm43xx_remove_one),
3939 #ifdef CONFIG_PM
3940 .suspend = bcm43xx_suspend,
3941 .resume = bcm43xx_resume,
3942 #endif /* CONFIG_PM */
3943 };
3944
3945 static int __init bcm43xx_init(void)
3946 {
3947 printk(KERN_INFO KBUILD_MODNAME " driver\n");
3948 bcm43xx_debugfs_init();
3949 return pci_register_driver(&bcm43xx_pci_driver);
3950 }
3951
3952 static void __exit bcm43xx_exit(void)
3953 {
3954 pci_unregister_driver(&bcm43xx_pci_driver);
3955 bcm43xx_debugfs_exit();
3956 }
3957
3958 module_init(bcm43xx_init)
3959 module_exit(bcm43xx_exit)
Community contributions to the Openmoko Kernel