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[PATCH] cyber2000fb.c __iomem annotations
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / net / ns83820.c
blobf857ae94d261ab505dd809499c372878c0d79e93
1 #define VERSION "0.22"
2 /* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
71 * Driver Overview
72 * ===============
73 *
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
82 *
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
85 *
86 * Cameo SOHO-GA2000T SOHO-GA2500T
87 * D-Link DGE-500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
90 * Netgear GA621
91 *
92 * Special thanks to SMC for providing hardware to test this driver on.
93 *
94 * Reports of success or failure would be greatly appreciated.
95 */
96 //#define dprintk printk
97 #define dprintk(x...) do { } while (0)
98
99 #include <linux/config.h>
100 #include <linux/module.h>
101 #include <linux/moduleparam.h>
102 #include <linux/types.h>
103 #include <linux/pci.h>
104 #include <linux/dma-mapping.h>
105 #include <linux/netdevice.h>
106 #include <linux/etherdevice.h>
107 #include <linux/delay.h>
108 #include <linux/smp_lock.h>
109 #include <linux/workqueue.h>
110 #include <linux/init.h>
111 #include <linux/ip.h> /* for iph */
112 #include <linux/in.h> /* for IPPROTO_... */
113 #include <linux/compiler.h>
114 #include <linux/prefetch.h>
115 #include <linux/ethtool.h>
116 #include <linux/timer.h>
117 #include <linux/if_vlan.h>
118
119 #include <asm/io.h>
120 #include <asm/uaccess.h>
121 #include <asm/system.h>
122
123 #define DRV_NAME "ns83820"
124
125 /* Global parameters. See module_param near the bottom. */
126 static int ihr = 2;
127 static int reset_phy = 0;
128 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
129
130 /* Dprintk is used for more interesting debug events */
131 #undef Dprintk
132 #define Dprintk dprintk
133
134 /* tunables */
135 #define RX_BUF_SIZE 1500 /* 8192 */
136 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
137 #define NS83820_VLAN_ACCEL_SUPPORT
138 #endif
139
140 /* Must not exceed ~65000. */
141 #define NR_RX_DESC 64
142 #define NR_TX_DESC 128
143
144 /* not tunable */
145 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
146
147 #define MIN_TX_DESC_FREE 8
148
149 /* register defines */
150 #define CFGCS 0x04
151
152 #define CR_TXE 0x00000001
153 #define CR_TXD 0x00000002
154 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
155 * The Receive engine skips one descriptor and moves
156 * onto the next one!! */
157 #define CR_RXE 0x00000004
158 #define CR_RXD 0x00000008
159 #define CR_TXR 0x00000010
160 #define CR_RXR 0x00000020
161 #define CR_SWI 0x00000080
162 #define CR_RST 0x00000100
163
164 #define PTSCR_EEBIST_FAIL 0x00000001
165 #define PTSCR_EEBIST_EN 0x00000002
166 #define PTSCR_EELOAD_EN 0x00000004
167 #define PTSCR_RBIST_FAIL 0x000001b8
168 #define PTSCR_RBIST_DONE 0x00000200
169 #define PTSCR_RBIST_EN 0x00000400
170 #define PTSCR_RBIST_RST 0x00002000
171
172 #define MEAR_EEDI 0x00000001
173 #define MEAR_EEDO 0x00000002
174 #define MEAR_EECLK 0x00000004
175 #define MEAR_EESEL 0x00000008
176 #define MEAR_MDIO 0x00000010
177 #define MEAR_MDDIR 0x00000020
178 #define MEAR_MDC 0x00000040
179
180 #define ISR_TXDESC3 0x40000000
181 #define ISR_TXDESC2 0x20000000
182 #define ISR_TXDESC1 0x10000000
183 #define ISR_TXDESC0 0x08000000
184 #define ISR_RXDESC3 0x04000000
185 #define ISR_RXDESC2 0x02000000
186 #define ISR_RXDESC1 0x01000000
187 #define ISR_RXDESC0 0x00800000
188 #define ISR_TXRCMP 0x00400000
189 #define ISR_RXRCMP 0x00200000
190 #define ISR_DPERR 0x00100000
191 #define ISR_SSERR 0x00080000
192 #define ISR_RMABT 0x00040000
193 #define ISR_RTABT 0x00020000
194 #define ISR_RXSOVR 0x00010000
195 #define ISR_HIBINT 0x00008000
196 #define ISR_PHY 0x00004000
197 #define ISR_PME 0x00002000
198 #define ISR_SWI 0x00001000
199 #define ISR_MIB 0x00000800
200 #define ISR_TXURN 0x00000400
201 #define ISR_TXIDLE 0x00000200
202 #define ISR_TXERR 0x00000100
203 #define ISR_TXDESC 0x00000080
204 #define ISR_TXOK 0x00000040
205 #define ISR_RXORN 0x00000020
206 #define ISR_RXIDLE 0x00000010
207 #define ISR_RXEARLY 0x00000008
208 #define ISR_RXERR 0x00000004
209 #define ISR_RXDESC 0x00000002
210 #define ISR_RXOK 0x00000001
211
212 #define TXCFG_CSI 0x80000000
213 #define TXCFG_HBI 0x40000000
214 #define TXCFG_MLB 0x20000000
215 #define TXCFG_ATP 0x10000000
216 #define TXCFG_ECRETRY 0x00800000
217 #define TXCFG_BRST_DIS 0x00080000
218 #define TXCFG_MXDMA1024 0x00000000
219 #define TXCFG_MXDMA512 0x00700000
220 #define TXCFG_MXDMA256 0x00600000
221 #define TXCFG_MXDMA128 0x00500000
222 #define TXCFG_MXDMA64 0x00400000
223 #define TXCFG_MXDMA32 0x00300000
224 #define TXCFG_MXDMA16 0x00200000
225 #define TXCFG_MXDMA8 0x00100000
226
227 #define CFG_LNKSTS 0x80000000
228 #define CFG_SPDSTS 0x60000000
229 #define CFG_SPDSTS1 0x40000000
230 #define CFG_SPDSTS0 0x20000000
231 #define CFG_DUPSTS 0x10000000
232 #define CFG_TBI_EN 0x01000000
233 #define CFG_MODE_1000 0x00400000
234 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
235 * Read the Phy response and then configure the MAC accordingly */
236 #define CFG_AUTO_1000 0x00200000
237 #define CFG_PINT_CTL 0x001c0000
238 #define CFG_PINT_DUPSTS 0x00100000
239 #define CFG_PINT_LNKSTS 0x00080000
240 #define CFG_PINT_SPDSTS 0x00040000
241 #define CFG_TMRTEST 0x00020000
242 #define CFG_MRM_DIS 0x00010000
243 #define CFG_MWI_DIS 0x00008000
244 #define CFG_T64ADDR 0x00004000
245 #define CFG_PCI64_DET 0x00002000
246 #define CFG_DATA64_EN 0x00001000
247 #define CFG_M64ADDR 0x00000800
248 #define CFG_PHY_RST 0x00000400
249 #define CFG_PHY_DIS 0x00000200
250 #define CFG_EXTSTS_EN 0x00000100
251 #define CFG_REQALG 0x00000080
252 #define CFG_SB 0x00000040
253 #define CFG_POW 0x00000020
254 #define CFG_EXD 0x00000010
255 #define CFG_PESEL 0x00000008
256 #define CFG_BROM_DIS 0x00000004
257 #define CFG_EXT_125 0x00000002
258 #define CFG_BEM 0x00000001
259
260 #define EXTSTS_UDPPKT 0x00200000
261 #define EXTSTS_TCPPKT 0x00080000
262 #define EXTSTS_IPPKT 0x00020000
263 #define EXTSTS_VPKT 0x00010000
264 #define EXTSTS_VTG_MASK 0x0000ffff
265
266 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
267
268 #define MIBC_MIBS 0x00000008
269 #define MIBC_ACLR 0x00000004
270 #define MIBC_FRZ 0x00000002
271 #define MIBC_WRN 0x00000001
272
273 #define PCR_PSEN (1 << 31)
274 #define PCR_PS_MCAST (1 << 30)
275 #define PCR_PS_DA (1 << 29)
276 #define PCR_STHI_8 (3 << 23)
277 #define PCR_STLO_4 (1 << 23)
278 #define PCR_FFHI_8K (3 << 21)
279 #define PCR_FFLO_4K (1 << 21)
280 #define PCR_PAUSE_CNT 0xFFFE
281
282 #define RXCFG_AEP 0x80000000
283 #define RXCFG_ARP 0x40000000
284 #define RXCFG_STRIPCRC 0x20000000
285 #define RXCFG_RX_FD 0x10000000
286 #define RXCFG_ALP 0x08000000
287 #define RXCFG_AIRL 0x04000000
288 #define RXCFG_MXDMA512 0x00700000
289 #define RXCFG_DRTH 0x0000003e
290 #define RXCFG_DRTH0 0x00000002
291
292 #define RFCR_RFEN 0x80000000
293 #define RFCR_AAB 0x40000000
294 #define RFCR_AAM 0x20000000
295 #define RFCR_AAU 0x10000000
296 #define RFCR_APM 0x08000000
297 #define RFCR_APAT 0x07800000
298 #define RFCR_APAT3 0x04000000
299 #define RFCR_APAT2 0x02000000
300 #define RFCR_APAT1 0x01000000
301 #define RFCR_APAT0 0x00800000
302 #define RFCR_AARP 0x00400000
303 #define RFCR_MHEN 0x00200000
304 #define RFCR_UHEN 0x00100000
305 #define RFCR_ULM 0x00080000
306
307 #define VRCR_RUDPE 0x00000080
308 #define VRCR_RTCPE 0x00000040
309 #define VRCR_RIPE 0x00000020
310 #define VRCR_IPEN 0x00000010
311 #define VRCR_DUTF 0x00000008
312 #define VRCR_DVTF 0x00000004
313 #define VRCR_VTREN 0x00000002
314 #define VRCR_VTDEN 0x00000001
315
316 #define VTCR_PPCHK 0x00000008
317 #define VTCR_GCHK 0x00000004
318 #define VTCR_VPPTI 0x00000002
319 #define VTCR_VGTI 0x00000001
320
321 #define CR 0x00
322 #define CFG 0x04
323 #define MEAR 0x08
324 #define PTSCR 0x0c
325 #define ISR 0x10
326 #define IMR 0x14
327 #define IER 0x18
328 #define IHR 0x1c
329 #define TXDP 0x20
330 #define TXDP_HI 0x24
331 #define TXCFG 0x28
332 #define GPIOR 0x2c
333 #define RXDP 0x30
334 #define RXDP_HI 0x34
335 #define RXCFG 0x38
336 #define PQCR 0x3c
337 #define WCSR 0x40
338 #define PCR 0x44
339 #define RFCR 0x48
340 #define RFDR 0x4c
341
342 #define SRR 0x58
343
344 #define VRCR 0xbc
345 #define VTCR 0xc0
346 #define VDR 0xc4
347 #define CCSR 0xcc
348
349 #define TBICR 0xe0
350 #define TBISR 0xe4
351 #define TANAR 0xe8
352 #define TANLPAR 0xec
353 #define TANER 0xf0
354 #define TESR 0xf4
355
356 #define TBICR_MR_AN_ENABLE 0x00001000
357 #define TBICR_MR_RESTART_AN 0x00000200
358
359 #define TBISR_MR_LINK_STATUS 0x00000020
360 #define TBISR_MR_AN_COMPLETE 0x00000004
361
362 #define TANAR_PS2 0x00000100
363 #define TANAR_PS1 0x00000080
364 #define TANAR_HALF_DUP 0x00000040
365 #define TANAR_FULL_DUP 0x00000020
366
367 #define GPIOR_GP5_OE 0x00000200
368 #define GPIOR_GP4_OE 0x00000100
369 #define GPIOR_GP3_OE 0x00000080
370 #define GPIOR_GP2_OE 0x00000040
371 #define GPIOR_GP1_OE 0x00000020
372 #define GPIOR_GP3_OUT 0x00000004
373 #define GPIOR_GP1_OUT 0x00000001
374
375 #define LINK_AUTONEGOTIATE 0x01
376 #define LINK_DOWN 0x02
377 #define LINK_UP 0x04
378
379 #define HW_ADDR_LEN sizeof(dma_addr_t)
380 #define desc_addr_set(desc, addr) \
381 do { \
382 ((desc)[0] = cpu_to_le32(addr)); \
383 if (HW_ADDR_LEN == 8) \
384 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
385 } while(0)
386 #define desc_addr_get(desc) \
387 (le32_to_cpu((desc)[0]) | \
388 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
389
390 #define DESC_LINK 0
391 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
392 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
393 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
394
395 #define CMDSTS_OWN 0x80000000
396 #define CMDSTS_MORE 0x40000000
397 #define CMDSTS_INTR 0x20000000
398 #define CMDSTS_ERR 0x10000000
399 #define CMDSTS_OK 0x08000000
400 #define CMDSTS_RUNT 0x00200000
401 #define CMDSTS_LEN_MASK 0x0000ffff
402
403 #define CMDSTS_DEST_MASK 0x01800000
404 #define CMDSTS_DEST_SELF 0x00800000
405 #define CMDSTS_DEST_MULTI 0x01000000
406
407 #define DESC_SIZE 8 /* Should be cache line sized */
408
409 struct rx_info {
410 spinlock_t lock;
411 int up;
412 long idle;
413
414 struct sk_buff *skbs[NR_RX_DESC];
415
416 u32 *next_rx_desc;
417 u16 next_rx, next_empty;
418
419 u32 *descs;
420 dma_addr_t phy_descs;
421 };
422
423
424 struct ns83820 {
425 struct net_device_stats stats;
426 u8 __iomem *base;
427
428 struct pci_dev *pci_dev;
429
430 #ifdef NS83820_VLAN_ACCEL_SUPPORT
431 struct vlan_group *vlgrp;
432 #endif
433
434 struct rx_info rx_info;
435 struct tasklet_struct rx_tasklet;
436
437 unsigned ihr;
438 struct work_struct tq_refill;
439
440 /* protects everything below. irqsave when using. */
441 spinlock_t misc_lock;
442
443 u32 CFG_cache;
444
445 u32 MEAR_cache;
446 u32 IMR_cache;
447
448 unsigned linkstate;
449
450 spinlock_t tx_lock;
451
452 u16 tx_done_idx;
453 u16 tx_idx;
454 volatile u16 tx_free_idx; /* idx of free desc chain */
455 u16 tx_intr_idx;
456
457 atomic_t nr_tx_skbs;
458 struct sk_buff *tx_skbs[NR_TX_DESC];
459
460 char pad[16] __attribute__((aligned(16)));
461 u32 *tx_descs;
462 dma_addr_t tx_phy_descs;
463
464 struct timer_list tx_watchdog;
465 };
466
467 static inline struct ns83820 *PRIV(struct net_device *dev)
468 {
469 return netdev_priv(dev);
470 }
471
472 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
473
474 static inline void kick_rx(struct net_device *ndev)
475 {
476 struct ns83820 *dev = PRIV(ndev);
477 dprintk("kick_rx: maybe kicking\n");
478 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
479 dprintk("actually kicking\n");
480 writel(dev->rx_info.phy_descs +
481 (4 * DESC_SIZE * dev->rx_info.next_rx),
482 dev->base + RXDP);
483 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
484 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
485 ndev->name);
486 __kick_rx(dev);
487 }
488 }
489
490 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
491 #define start_tx_okay(dev) \
492 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
493
494
495 #ifdef NS83820_VLAN_ACCEL_SUPPORT
496 static void ns83820_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
497 {
498 struct ns83820 *dev = PRIV(ndev);
499
500 spin_lock_irq(&dev->misc_lock);
501 spin_lock(&dev->tx_lock);
502
503 dev->vlgrp = grp;
504
505 spin_unlock(&dev->tx_lock);
506 spin_unlock_irq(&dev->misc_lock);
507 }
508
509 static void ns83820_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid)
510 {
511 struct ns83820 *dev = PRIV(ndev);
512
513 spin_lock_irq(&dev->misc_lock);
514 spin_lock(&dev->tx_lock);
515 if (dev->vlgrp)
516 dev->vlgrp->vlan_devices[vid] = NULL;
517 spin_unlock(&dev->tx_lock);
518 spin_unlock_irq(&dev->misc_lock);
519 }
520 #endif
521
522 /* Packet Receiver
523 *
524 * The hardware supports linked lists of receive descriptors for
525 * which ownership is transfered back and forth by means of an
526 * ownership bit. While the hardware does support the use of a
527 * ring for receive descriptors, we only make use of a chain in
528 * an attempt to reduce bus traffic under heavy load scenarios.
529 * This will also make bugs a bit more obvious. The current code
530 * only makes use of a single rx chain; I hope to implement
531 * priority based rx for version 1.0. Goal: even under overload
532 * conditions, still route realtime traffic with as low jitter as
533 * possible.
534 */
535 static inline void build_rx_desc(struct ns83820 *dev, u32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
536 {
537 desc_addr_set(desc + DESC_LINK, link);
538 desc_addr_set(desc + DESC_BUFPTR, buf);
539 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
540 mb();
541 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
542 }
543
544 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
545 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
546 {
547 unsigned next_empty;
548 u32 cmdsts;
549 u32 *sg;
550 dma_addr_t buf;
551
552 next_empty = dev->rx_info.next_empty;
553
554 /* don't overrun last rx marker */
555 if (unlikely(nr_rx_empty(dev) <= 2)) {
556 kfree_skb(skb);
557 return 1;
558 }
559
560 #if 0
561 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
562 dev->rx_info.next_empty,
563 dev->rx_info.nr_used,
564 dev->rx_info.next_rx
565 );
566 #endif
567
568 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
569 if (unlikely(NULL != dev->rx_info.skbs[next_empty]))
570 BUG();
571 dev->rx_info.skbs[next_empty] = skb;
572
573 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
574 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
575 buf = pci_map_single(dev->pci_dev, skb->data,
576 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
577 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
578 /* update link of previous rx */
579 if (likely(next_empty != dev->rx_info.next_rx))
580 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
581
582 return 0;
583 }
584
585 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
586 {
587 struct ns83820 *dev = PRIV(ndev);
588 unsigned i;
589 unsigned long flags = 0;
590
591 if (unlikely(nr_rx_empty(dev) <= 2))
592 return 0;
593
594 dprintk("rx_refill(%p)\n", ndev);
595 if (gfp == GFP_ATOMIC)
596 spin_lock_irqsave(&dev->rx_info.lock, flags);
597 for (i=0; i<NR_RX_DESC; i++) {
598 struct sk_buff *skb;
599 long res;
600 /* extra 16 bytes for alignment */
601 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp);
602 if (unlikely(!skb))
603 break;
604
605 res = (long)skb->data & 0xf;
606 res = 0x10 - res;
607 res &= 0xf;
608 skb_reserve(skb, res);
609
610 skb->dev = ndev;
611 if (gfp != GFP_ATOMIC)
612 spin_lock_irqsave(&dev->rx_info.lock, flags);
613 res = ns83820_add_rx_skb(dev, skb);
614 if (gfp != GFP_ATOMIC)
615 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
616 if (res) {
617 i = 1;
618 break;
619 }
620 }
621 if (gfp == GFP_ATOMIC)
622 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
623
624 return i ? 0 : -ENOMEM;
625 }
626
627 static void FASTCALL(rx_refill_atomic(struct net_device *ndev));
628 static void fastcall rx_refill_atomic(struct net_device *ndev)
629 {
630 rx_refill(ndev, GFP_ATOMIC);
631 }
632
633 /* REFILL */
634 static inline void queue_refill(void *_dev)
635 {
636 struct net_device *ndev = _dev;
637 struct ns83820 *dev = PRIV(ndev);
638
639 rx_refill(ndev, GFP_KERNEL);
640 if (dev->rx_info.up)
641 kick_rx(ndev);
642 }
643
644 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
645 {
646 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
647 }
648
649 static void FASTCALL(phy_intr(struct net_device *ndev));
650 static void fastcall phy_intr(struct net_device *ndev)
651 {
652 struct ns83820 *dev = PRIV(ndev);
653 static char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
654 u32 cfg, new_cfg;
655 u32 tbisr, tanar, tanlpar;
656 int speed, fullduplex, newlinkstate;
657
658 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
659
660 if (dev->CFG_cache & CFG_TBI_EN) {
661 /* we have an optical transceiver */
662 tbisr = readl(dev->base + TBISR);
663 tanar = readl(dev->base + TANAR);
664 tanlpar = readl(dev->base + TANLPAR);
665 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
666 tbisr, tanar, tanlpar);
667
668 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
669 && (tanar & TANAR_FULL_DUP)) ) {
670
671 /* both of us are full duplex */
672 writel(readl(dev->base + TXCFG)
673 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
674 dev->base + TXCFG);
675 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
676 dev->base + RXCFG);
677 /* Light up full duplex LED */
678 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
679 dev->base + GPIOR);
680
681 } else if(((tanlpar & TANAR_HALF_DUP)
682 && (tanar & TANAR_HALF_DUP))
683 || ((tanlpar & TANAR_FULL_DUP)
684 && (tanar & TANAR_HALF_DUP))
685 || ((tanlpar & TANAR_HALF_DUP)
686 && (tanar & TANAR_FULL_DUP))) {
687
688 /* one or both of us are half duplex */
689 writel((readl(dev->base + TXCFG)
690 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
691 dev->base + TXCFG);
692 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
693 dev->base + RXCFG);
694 /* Turn off full duplex LED */
695 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
696 dev->base + GPIOR);
697 }
698
699 speed = 4; /* 1000F */
700
701 } else {
702 /* we have a copper transceiver */
703 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
704
705 if (cfg & CFG_SPDSTS1)
706 new_cfg |= CFG_MODE_1000;
707 else
708 new_cfg &= ~CFG_MODE_1000;
709
710 speed = ((cfg / CFG_SPDSTS0) & 3);
711 fullduplex = (cfg & CFG_DUPSTS);
712
713 if (fullduplex) {
714 new_cfg |= CFG_SB;
715 writel(readl(dev->base + TXCFG)
716 | TXCFG_CSI | TXCFG_HBI,
717 dev->base + TXCFG);
718 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
719 dev->base + RXCFG);
720 } else {
721 writel(readl(dev->base + TXCFG)
722 & ~(TXCFG_CSI | TXCFG_HBI),
723 dev->base + TXCFG);
724 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
725 dev->base + RXCFG);
726 }
727
728 if ((cfg & CFG_LNKSTS) &&
729 ((new_cfg ^ dev->CFG_cache) != 0)) {
730 writel(new_cfg, dev->base + CFG);
731 dev->CFG_cache = new_cfg;
732 }
733
734 dev->CFG_cache &= ~CFG_SPDSTS;
735 dev->CFG_cache |= cfg & CFG_SPDSTS;
736 }
737
738 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
739
740 if (newlinkstate & LINK_UP
741 && dev->linkstate != newlinkstate) {
742 netif_start_queue(ndev);
743 netif_wake_queue(ndev);
744 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
745 ndev->name,
746 speeds[speed],
747 fullduplex ? "full" : "half");
748 } else if (newlinkstate & LINK_DOWN
749 && dev->linkstate != newlinkstate) {
750 netif_stop_queue(ndev);
751 printk(KERN_INFO "%s: link now down.\n", ndev->name);
752 }
753
754 dev->linkstate = newlinkstate;
755 }
756
757 static int ns83820_setup_rx(struct net_device *ndev)
758 {
759 struct ns83820 *dev = PRIV(ndev);
760 unsigned i;
761 int ret;
762
763 dprintk("ns83820_setup_rx(%p)\n", ndev);
764
765 dev->rx_info.idle = 1;
766 dev->rx_info.next_rx = 0;
767 dev->rx_info.next_rx_desc = dev->rx_info.descs;
768 dev->rx_info.next_empty = 0;
769
770 for (i=0; i<NR_RX_DESC; i++)
771 clear_rx_desc(dev, i);
772
773 writel(0, dev->base + RXDP_HI);
774 writel(dev->rx_info.phy_descs, dev->base + RXDP);
775
776 ret = rx_refill(ndev, GFP_KERNEL);
777 if (!ret) {
778 dprintk("starting receiver\n");
779 /* prevent the interrupt handler from stomping on us */
780 spin_lock_irq(&dev->rx_info.lock);
781
782 writel(0x0001, dev->base + CCSR);
783 writel(0, dev->base + RFCR);
784 writel(0x7fc00000, dev->base + RFCR);
785 writel(0xffc00000, dev->base + RFCR);
786
787 dev->rx_info.up = 1;
788
789 phy_intr(ndev);
790
791 /* Okay, let it rip */
792 spin_lock_irq(&dev->misc_lock);
793 dev->IMR_cache |= ISR_PHY;
794 dev->IMR_cache |= ISR_RXRCMP;
795 //dev->IMR_cache |= ISR_RXERR;
796 //dev->IMR_cache |= ISR_RXOK;
797 dev->IMR_cache |= ISR_RXORN;
798 dev->IMR_cache |= ISR_RXSOVR;
799 dev->IMR_cache |= ISR_RXDESC;
800 dev->IMR_cache |= ISR_RXIDLE;
801 dev->IMR_cache |= ISR_TXDESC;
802 dev->IMR_cache |= ISR_TXIDLE;
803
804 writel(dev->IMR_cache, dev->base + IMR);
805 writel(1, dev->base + IER);
806 spin_unlock_irq(&dev->misc_lock);
807
808 kick_rx(ndev);
809
810 spin_unlock_irq(&dev->rx_info.lock);
811 }
812 return ret;
813 }
814
815 static void ns83820_cleanup_rx(struct ns83820 *dev)
816 {
817 unsigned i;
818 unsigned long flags;
819
820 dprintk("ns83820_cleanup_rx(%p)\n", dev);
821
822 /* disable receive interrupts */
823 spin_lock_irqsave(&dev->misc_lock, flags);
824 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
825 writel(dev->IMR_cache, dev->base + IMR);
826 spin_unlock_irqrestore(&dev->misc_lock, flags);
827
828 /* synchronize with the interrupt handler and kill it */
829 dev->rx_info.up = 0;
830 synchronize_irq(dev->pci_dev->irq);
831
832 /* touch the pci bus... */
833 readl(dev->base + IMR);
834
835 /* assumes the transmitter is already disabled and reset */
836 writel(0, dev->base + RXDP_HI);
837 writel(0, dev->base + RXDP);
838
839 for (i=0; i<NR_RX_DESC; i++) {
840 struct sk_buff *skb = dev->rx_info.skbs[i];
841 dev->rx_info.skbs[i] = NULL;
842 clear_rx_desc(dev, i);
843 if (skb)
844 kfree_skb(skb);
845 }
846 }
847
848 static void FASTCALL(ns83820_rx_kick(struct net_device *ndev));
849 static void fastcall ns83820_rx_kick(struct net_device *ndev)
850 {
851 struct ns83820 *dev = PRIV(ndev);
852 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
853 if (dev->rx_info.up) {
854 rx_refill_atomic(ndev);
855 kick_rx(ndev);
856 }
857 }
858
859 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
860 schedule_work(&dev->tq_refill);
861 else
862 kick_rx(ndev);
863 if (dev->rx_info.idle)
864 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
865 }
866
867 /* rx_irq
868 *
869 */
870 static void FASTCALL(rx_irq(struct net_device *ndev));
871 static void fastcall rx_irq(struct net_device *ndev)
872 {
873 struct ns83820 *dev = PRIV(ndev);
874 struct rx_info *info = &dev->rx_info;
875 unsigned next_rx;
876 int rx_rc, len;
877 u32 cmdsts, *desc;
878 unsigned long flags;
879 int nr = 0;
880
881 dprintk("rx_irq(%p)\n", ndev);
882 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
883 readl(dev->base + RXDP),
884 (long)(dev->rx_info.phy_descs),
885 (int)dev->rx_info.next_rx,
886 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
887 (int)dev->rx_info.next_empty,
888 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
889 );
890
891 spin_lock_irqsave(&info->lock, flags);
892 if (!info->up)
893 goto out;
894
895 dprintk("walking descs\n");
896 next_rx = info->next_rx;
897 desc = info->next_rx_desc;
898 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
899 (cmdsts != CMDSTS_OWN)) {
900 struct sk_buff *skb;
901 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
902 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
903
904 dprintk("cmdsts: %08x\n", cmdsts);
905 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
906 dprintk("extsts: %08x\n", extsts);
907
908 skb = info->skbs[next_rx];
909 info->skbs[next_rx] = NULL;
910 info->next_rx = (next_rx + 1) % NR_RX_DESC;
911
912 mb();
913 clear_rx_desc(dev, next_rx);
914
915 pci_unmap_single(dev->pci_dev, bufptr,
916 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
917 len = cmdsts & CMDSTS_LEN_MASK;
918 #ifdef NS83820_VLAN_ACCEL_SUPPORT
919 /* NH: As was mentioned below, this chip is kinda
920 * brain dead about vlan tag stripping. Frames
921 * that are 64 bytes with a vlan header appended
922 * like arp frames, or pings, are flagged as Runts
923 * when the tag is stripped and hardware. This
924 * also means that the OK bit in the descriptor
925 * is cleared when the frame comes in so we have
926 * to do a specific length check here to make sure
927 * the frame would have been ok, had we not stripped
928 * the tag.
929 */
930 if (likely((CMDSTS_OK & cmdsts) ||
931 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
932 #else
933 if (likely(CMDSTS_OK & cmdsts)) {
934 #endif
935 skb_put(skb, len);
936 if (unlikely(!skb))
937 goto netdev_mangle_me_harder_failed;
938 if (cmdsts & CMDSTS_DEST_MULTI)
939 dev->stats.multicast ++;
940 dev->stats.rx_packets ++;
941 dev->stats.rx_bytes += len;
942 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
943 skb->ip_summed = CHECKSUM_UNNECESSARY;
944 } else {
945 skb->ip_summed = CHECKSUM_NONE;
946 }
947 skb->protocol = eth_type_trans(skb, ndev);
948 #ifdef NS83820_VLAN_ACCEL_SUPPORT
949 if(extsts & EXTSTS_VPKT) {
950 unsigned short tag;
951 tag = ntohs(extsts & EXTSTS_VTG_MASK);
952 rx_rc = vlan_hwaccel_rx(skb,dev->vlgrp,tag);
953 } else {
954 rx_rc = netif_rx(skb);
955 }
956 #else
957 rx_rc = netif_rx(skb);
958 #endif
959 if (NET_RX_DROP == rx_rc) {
960 netdev_mangle_me_harder_failed:
961 dev->stats.rx_dropped ++;
962 }
963 } else {
964 kfree_skb(skb);
965 }
966
967 nr++;
968 next_rx = info->next_rx;
969 desc = info->descs + (DESC_SIZE * next_rx);
970 }
971 info->next_rx = next_rx;
972 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
973
974 out:
975 if (0 && !nr) {
976 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
977 }
978
979 spin_unlock_irqrestore(&info->lock, flags);
980 }
981
982 static void rx_action(unsigned long _dev)
983 {
984 struct net_device *ndev = (void *)_dev;
985 struct ns83820 *dev = PRIV(ndev);
986 rx_irq(ndev);
987 writel(ihr, dev->base + IHR);
988
989 spin_lock_irq(&dev->misc_lock);
990 dev->IMR_cache |= ISR_RXDESC;
991 writel(dev->IMR_cache, dev->base + IMR);
992 spin_unlock_irq(&dev->misc_lock);
993
994 rx_irq(ndev);
995 ns83820_rx_kick(ndev);
996 }
997
998 /* Packet Transmit code
999 */
1000 static inline void kick_tx(struct ns83820 *dev)
1001 {
1002 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
1003 dev, dev->tx_idx, dev->tx_free_idx);
1004 writel(CR_TXE, dev->base + CR);
1005 }
1006
1007 /* No spinlock needed on the transmit irq path as the interrupt handler is
1008 * serialized.
1009 */
1010 static void do_tx_done(struct net_device *ndev)
1011 {
1012 struct ns83820 *dev = PRIV(ndev);
1013 u32 cmdsts, tx_done_idx, *desc;
1014
1015 spin_lock_irq(&dev->tx_lock);
1016
1017 dprintk("do_tx_done(%p)\n", ndev);
1018 tx_done_idx = dev->tx_done_idx;
1019 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1020
1021 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1022 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1023 while ((tx_done_idx != dev->tx_free_idx) &&
1024 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
1025 struct sk_buff *skb;
1026 unsigned len;
1027 dma_addr_t addr;
1028
1029 if (cmdsts & CMDSTS_ERR)
1030 dev->stats.tx_errors ++;
1031 if (cmdsts & CMDSTS_OK)
1032 dev->stats.tx_packets ++;
1033 if (cmdsts & CMDSTS_OK)
1034 dev->stats.tx_bytes += cmdsts & 0xffff;
1035
1036 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1037 tx_done_idx, dev->tx_free_idx, cmdsts);
1038 skb = dev->tx_skbs[tx_done_idx];
1039 dev->tx_skbs[tx_done_idx] = NULL;
1040 dprintk("done(%p)\n", skb);
1041
1042 len = cmdsts & CMDSTS_LEN_MASK;
1043 addr = desc_addr_get(desc + DESC_BUFPTR);
1044 if (skb) {
1045 pci_unmap_single(dev->pci_dev,
1046 addr,
1047 len,
1048 PCI_DMA_TODEVICE);
1049 dev_kfree_skb_irq(skb);
1050 atomic_dec(&dev->nr_tx_skbs);
1051 } else
1052 pci_unmap_page(dev->pci_dev,
1053 addr,
1054 len,
1055 PCI_DMA_TODEVICE);
1056
1057 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1058 dev->tx_done_idx = tx_done_idx;
1059 desc[DESC_CMDSTS] = cpu_to_le32(0);
1060 mb();
1061 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1062 }
1063
1064 /* Allow network stack to resume queueing packets after we've
1065 * finished transmitting at least 1/4 of the packets in the queue.
1066 */
1067 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1068 dprintk("start_queue(%p)\n", ndev);
1069 netif_start_queue(ndev);
1070 netif_wake_queue(ndev);
1071 }
1072 spin_unlock_irq(&dev->tx_lock);
1073 }
1074
1075 static void ns83820_cleanup_tx(struct ns83820 *dev)
1076 {
1077 unsigned i;
1078
1079 for (i=0; i<NR_TX_DESC; i++) {
1080 struct sk_buff *skb = dev->tx_skbs[i];
1081 dev->tx_skbs[i] = NULL;
1082 if (skb) {
1083 u32 *desc = dev->tx_descs + (i * DESC_SIZE);
1084 pci_unmap_single(dev->pci_dev,
1085 desc_addr_get(desc + DESC_BUFPTR),
1086 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1087 PCI_DMA_TODEVICE);
1088 dev_kfree_skb_irq(skb);
1089 atomic_dec(&dev->nr_tx_skbs);
1090 }
1091 }
1092
1093 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1094 }
1095
1096 /* transmit routine. This code relies on the network layer serializing
1097 * its calls in, but will run happily in parallel with the interrupt
1098 * handler. This code currently has provisions for fragmenting tx buffers
1099 * while trying to track down a bug in either the zero copy code or
1100 * the tx fifo (hence the MAX_FRAG_LEN).
1101 */
1102 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1103 {
1104 struct ns83820 *dev = PRIV(ndev);
1105 u32 free_idx, cmdsts, extsts;
1106 int nr_free, nr_frags;
1107 unsigned tx_done_idx, last_idx;
1108 dma_addr_t buf;
1109 unsigned len;
1110 skb_frag_t *frag;
1111 int stopped = 0;
1112 int do_intr = 0;
1113 volatile u32 *first_desc;
1114
1115 dprintk("ns83820_hard_start_xmit\n");
1116
1117 nr_frags = skb_shinfo(skb)->nr_frags;
1118 again:
1119 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1120 netif_stop_queue(ndev);
1121 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1122 return 1;
1123 netif_start_queue(ndev);
1124 }
1125
1126 last_idx = free_idx = dev->tx_free_idx;
1127 tx_done_idx = dev->tx_done_idx;
1128 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1129 nr_free -= 1;
1130 if (nr_free <= nr_frags) {
1131 dprintk("stop_queue - not enough(%p)\n", ndev);
1132 netif_stop_queue(ndev);
1133
1134 /* Check again: we may have raced with a tx done irq */
1135 if (dev->tx_done_idx != tx_done_idx) {
1136 dprintk("restart queue(%p)\n", ndev);
1137 netif_start_queue(ndev);
1138 goto again;
1139 }
1140 return 1;
1141 }
1142
1143 if (free_idx == dev->tx_intr_idx) {
1144 do_intr = 1;
1145 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1146 }
1147
1148 nr_free -= nr_frags;
1149 if (nr_free < MIN_TX_DESC_FREE) {
1150 dprintk("stop_queue - last entry(%p)\n", ndev);
1151 netif_stop_queue(ndev);
1152 stopped = 1;
1153 }
1154
1155 frag = skb_shinfo(skb)->frags;
1156 if (!nr_frags)
1157 frag = NULL;
1158 extsts = 0;
1159 if (skb->ip_summed == CHECKSUM_HW) {
1160 extsts |= EXTSTS_IPPKT;
1161 if (IPPROTO_TCP == skb->nh.iph->protocol)
1162 extsts |= EXTSTS_TCPPKT;
1163 else if (IPPROTO_UDP == skb->nh.iph->protocol)
1164 extsts |= EXTSTS_UDPPKT;
1165 }
1166
1167 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1168 if(vlan_tx_tag_present(skb)) {
1169 /* fetch the vlan tag info out of the
1170 * ancilliary data if the vlan code
1171 * is using hw vlan acceleration
1172 */
1173 short tag = vlan_tx_tag_get(skb);
1174 extsts |= (EXTSTS_VPKT | htons(tag));
1175 }
1176 #endif
1177
1178 len = skb->len;
1179 if (nr_frags)
1180 len -= skb->data_len;
1181 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1182
1183 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1184
1185 for (;;) {
1186 volatile u32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1187
1188 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1189 (unsigned long long)buf);
1190 last_idx = free_idx;
1191 free_idx = (free_idx + 1) % NR_TX_DESC;
1192 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1193 desc_addr_set(desc + DESC_BUFPTR, buf);
1194 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1195
1196 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1197 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1198 cmdsts |= len;
1199 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1200
1201 if (!nr_frags)
1202 break;
1203
1204 buf = pci_map_page(dev->pci_dev, frag->page,
1205 frag->page_offset,
1206 frag->size, PCI_DMA_TODEVICE);
1207 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1208 (long long)buf, (long) page_to_pfn(frag->page),
1209 frag->page_offset);
1210 len = frag->size;
1211 frag++;
1212 nr_frags--;
1213 }
1214 dprintk("done pkt\n");
1215
1216 spin_lock_irq(&dev->tx_lock);
1217 dev->tx_skbs[last_idx] = skb;
1218 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1219 dev->tx_free_idx = free_idx;
1220 atomic_inc(&dev->nr_tx_skbs);
1221 spin_unlock_irq(&dev->tx_lock);
1222
1223 kick_tx(dev);
1224
1225 /* Check again: we may have raced with a tx done irq */
1226 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1227 netif_start_queue(ndev);
1228
1229 /* set the transmit start time to catch transmit timeouts */
1230 ndev->trans_start = jiffies;
1231 return 0;
1232 }
1233
1234 static void ns83820_update_stats(struct ns83820 *dev)
1235 {
1236 u8 __iomem *base = dev->base;
1237
1238 /* the DP83820 will freeze counters, so we need to read all of them */
1239 dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1240 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1241 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1242 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1243 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1244 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1245 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1246 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1247 /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1248 /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1249 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1250 }
1251
1252 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1253 {
1254 struct ns83820 *dev = PRIV(ndev);
1255
1256 /* somewhat overkill */
1257 spin_lock_irq(&dev->misc_lock);
1258 ns83820_update_stats(dev);
1259 spin_unlock_irq(&dev->misc_lock);
1260
1261 return &dev->stats;
1262 }
1263
1264 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1265 {
1266 struct ns83820 *dev = PRIV(ndev);
1267 strcpy(info->driver, "ns83820");
1268 strcpy(info->version, VERSION);
1269 strcpy(info->bus_info, pci_name(dev->pci_dev));
1270 }
1271
1272 static u32 ns83820_get_link(struct net_device *ndev)
1273 {
1274 struct ns83820 *dev = PRIV(ndev);
1275 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1276 return cfg & CFG_LNKSTS ? 1 : 0;
1277 }
1278
1279 static struct ethtool_ops ops = {
1280 .get_drvinfo = ns83820_get_drvinfo,
1281 .get_link = ns83820_get_link
1282 };
1283
1284 static void ns83820_mib_isr(struct ns83820 *dev)
1285 {
1286 spin_lock(&dev->misc_lock);
1287 ns83820_update_stats(dev);
1288 spin_unlock(&dev->misc_lock);
1289 }
1290
1291 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1292 static irqreturn_t ns83820_irq(int foo, void *data, struct pt_regs *regs)
1293 {
1294 struct net_device *ndev = data;
1295 struct ns83820 *dev = PRIV(ndev);
1296 u32 isr;
1297 dprintk("ns83820_irq(%p)\n", ndev);
1298
1299 dev->ihr = 0;
1300
1301 isr = readl(dev->base + ISR);
1302 dprintk("irq: %08x\n", isr);
1303 ns83820_do_isr(ndev, isr);
1304 return IRQ_HANDLED;
1305 }
1306
1307 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1308 {
1309 struct ns83820 *dev = PRIV(ndev);
1310 #ifdef DEBUG
1311 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1312 Dprintk("odd isr? 0x%08x\n", isr);
1313 #endif
1314
1315 if (ISR_RXIDLE & isr) {
1316 dev->rx_info.idle = 1;
1317 Dprintk("oh dear, we are idle\n");
1318 ns83820_rx_kick(ndev);
1319 }
1320
1321 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1322 prefetch(dev->rx_info.next_rx_desc);
1323
1324 spin_lock_irq(&dev->misc_lock);
1325 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1326 writel(dev->IMR_cache, dev->base + IMR);
1327 spin_unlock_irq(&dev->misc_lock);
1328
1329 tasklet_schedule(&dev->rx_tasklet);
1330 //rx_irq(ndev);
1331 //writel(4, dev->base + IHR);
1332 }
1333
1334 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1335 ns83820_rx_kick(ndev);
1336
1337 if (unlikely(ISR_RXSOVR & isr)) {
1338 //printk("overrun: rxsovr\n");
1339 dev->stats.rx_fifo_errors ++;
1340 }
1341
1342 if (unlikely(ISR_RXORN & isr)) {
1343 //printk("overrun: rxorn\n");
1344 dev->stats.rx_fifo_errors ++;
1345 }
1346
1347 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1348 writel(CR_RXE, dev->base + CR);
1349
1350 if (ISR_TXIDLE & isr) {
1351 u32 txdp;
1352 txdp = readl(dev->base + TXDP);
1353 dprintk("txdp: %08x\n", txdp);
1354 txdp -= dev->tx_phy_descs;
1355 dev->tx_idx = txdp / (DESC_SIZE * 4);
1356 if (dev->tx_idx >= NR_TX_DESC) {
1357 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1358 dev->tx_idx = 0;
1359 }
1360 /* The may have been a race between a pci originated read
1361 * and the descriptor update from the cpu. Just in case,
1362 * kick the transmitter if the hardware thinks it is on a
1363 * different descriptor than we are.
1364 */
1365 if (dev->tx_idx != dev->tx_free_idx)
1366 kick_tx(dev);
1367 }
1368
1369 /* Defer tx ring processing until more than a minimum amount of
1370 * work has accumulated
1371 */
1372 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1373 do_tx_done(ndev);
1374
1375 /* Disable TxOk if there are no outstanding tx packets.
1376 */
1377 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1378 (dev->IMR_cache & ISR_TXOK)) {
1379 spin_lock_irq(&dev->misc_lock);
1380 dev->IMR_cache &= ~ISR_TXOK;
1381 writel(dev->IMR_cache, dev->base + IMR);
1382 spin_unlock_irq(&dev->misc_lock);
1383 }
1384 }
1385
1386 /* The TxIdle interrupt can come in before the transmit has
1387 * completed. Normally we reap packets off of the combination
1388 * of TxDesc and TxIdle and leave TxOk disabled (since it
1389 * occurs on every packet), but when no further irqs of this
1390 * nature are expected, we must enable TxOk.
1391 */
1392 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1393 spin_lock_irq(&dev->misc_lock);
1394 dev->IMR_cache |= ISR_TXOK;
1395 writel(dev->IMR_cache, dev->base + IMR);
1396 spin_unlock_irq(&dev->misc_lock);
1397 }
1398
1399 /* MIB interrupt: one of the statistics counters is about to overflow */
1400 if (unlikely(ISR_MIB & isr))
1401 ns83820_mib_isr(dev);
1402
1403 /* PHY: Link up/down/negotiation state change */
1404 if (unlikely(ISR_PHY & isr))
1405 phy_intr(ndev);
1406
1407 #if 0 /* Still working on the interrupt mitigation strategy */
1408 if (dev->ihr)
1409 writel(dev->ihr, dev->base + IHR);
1410 #endif
1411 }
1412
1413 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1414 {
1415 Dprintk("resetting chip...\n");
1416 writel(which, dev->base + CR);
1417 do {
1418 schedule();
1419 } while (readl(dev->base + CR) & which);
1420 Dprintk("okay!\n");
1421 }
1422
1423 static int ns83820_stop(struct net_device *ndev)
1424 {
1425 struct ns83820 *dev = PRIV(ndev);
1426
1427 /* FIXME: protect against interrupt handler? */
1428 del_timer_sync(&dev->tx_watchdog);
1429
1430 /* disable interrupts */
1431 writel(0, dev->base + IMR);
1432 writel(0, dev->base + IER);
1433 readl(dev->base + IER);
1434
1435 dev->rx_info.up = 0;
1436 synchronize_irq(dev->pci_dev->irq);
1437
1438 ns83820_do_reset(dev, CR_RST);
1439
1440 synchronize_irq(dev->pci_dev->irq);
1441
1442 spin_lock_irq(&dev->misc_lock);
1443 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1444 spin_unlock_irq(&dev->misc_lock);
1445
1446 ns83820_cleanup_rx(dev);
1447 ns83820_cleanup_tx(dev);
1448
1449 return 0;
1450 }
1451
1452 static void ns83820_tx_timeout(struct net_device *ndev)
1453 {
1454 struct ns83820 *dev = PRIV(ndev);
1455 u32 tx_done_idx, *desc;
1456 unsigned long flags;
1457
1458 local_irq_save(flags);
1459
1460 tx_done_idx = dev->tx_done_idx;
1461 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1462
1463 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1464 ndev->name,
1465 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1466
1467 #if defined(DEBUG)
1468 {
1469 u32 isr;
1470 isr = readl(dev->base + ISR);
1471 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1472 ns83820_do_isr(ndev, isr);
1473 }
1474 #endif
1475
1476 do_tx_done(ndev);
1477
1478 tx_done_idx = dev->tx_done_idx;
1479 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1480
1481 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1482 ndev->name,
1483 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1484
1485 local_irq_restore(flags);
1486 }
1487
1488 static void ns83820_tx_watch(unsigned long data)
1489 {
1490 struct net_device *ndev = (void *)data;
1491 struct ns83820 *dev = PRIV(ndev);
1492
1493 #if defined(DEBUG)
1494 printk("ns83820_tx_watch: %u %u %d\n",
1495 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1496 );
1497 #endif
1498
1499 if (time_after(jiffies, ndev->trans_start + 1*HZ) &&
1500 dev->tx_done_idx != dev->tx_free_idx) {
1501 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1502 ndev->name,
1503 dev->tx_done_idx, dev->tx_free_idx,
1504 atomic_read(&dev->nr_tx_skbs));
1505 ns83820_tx_timeout(ndev);
1506 }
1507
1508 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1509 }
1510
1511 static int ns83820_open(struct net_device *ndev)
1512 {
1513 struct ns83820 *dev = PRIV(ndev);
1514 unsigned i;
1515 u32 desc;
1516 int ret;
1517
1518 dprintk("ns83820_open\n");
1519
1520 writel(0, dev->base + PQCR);
1521
1522 ret = ns83820_setup_rx(ndev);
1523 if (ret)
1524 goto failed;
1525
1526 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1527 for (i=0; i<NR_TX_DESC; i++) {
1528 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1529 = cpu_to_le32(
1530 dev->tx_phy_descs
1531 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1532 }
1533
1534 dev->tx_idx = 0;
1535 dev->tx_done_idx = 0;
1536 desc = dev->tx_phy_descs;
1537 writel(0, dev->base + TXDP_HI);
1538 writel(desc, dev->base + TXDP);
1539
1540 init_timer(&dev->tx_watchdog);
1541 dev->tx_watchdog.data = (unsigned long)ndev;
1542 dev->tx_watchdog.function = ns83820_tx_watch;
1543 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1544
1545 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1546
1547 return 0;
1548
1549 failed:
1550 ns83820_stop(ndev);
1551 return ret;
1552 }
1553
1554 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1555 {
1556 unsigned i;
1557 for (i=0; i<3; i++) {
1558 u32 data;
1559
1560 /* Read from the perfect match memory: this is loaded by
1561 * the chip from the EEPROM via the EELOAD self test.
1562 */
1563 writel(i*2, dev->base + RFCR);
1564 data = readl(dev->base + RFDR);
1565
1566 *mac++ = data;
1567 *mac++ = data >> 8;
1568 }
1569 }
1570
1571 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1572 {
1573 if (new_mtu > RX_BUF_SIZE)
1574 return -EINVAL;
1575 ndev->mtu = new_mtu;
1576 return 0;
1577 }
1578
1579 static void ns83820_set_multicast(struct net_device *ndev)
1580 {
1581 struct ns83820 *dev = PRIV(ndev);
1582 u8 __iomem *rfcr = dev->base + RFCR;
1583 u32 and_mask = 0xffffffff;
1584 u32 or_mask = 0;
1585 u32 val;
1586
1587 if (ndev->flags & IFF_PROMISC)
1588 or_mask |= RFCR_AAU | RFCR_AAM;
1589 else
1590 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1591
1592 if (ndev->flags & IFF_ALLMULTI)
1593 or_mask |= RFCR_AAM;
1594 else
1595 and_mask &= ~RFCR_AAM;
1596
1597 spin_lock_irq(&dev->misc_lock);
1598 val = (readl(rfcr) & and_mask) | or_mask;
1599 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1600 writel(val & ~RFCR_RFEN, rfcr);
1601 writel(val, rfcr);
1602 spin_unlock_irq(&dev->misc_lock);
1603 }
1604
1605 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1606 {
1607 struct ns83820 *dev = PRIV(ndev);
1608 int timed_out = 0;
1609 long start;
1610 u32 status;
1611 int loops = 0;
1612
1613 dprintk("%s: start %s\n", ndev->name, name);
1614
1615 start = jiffies;
1616
1617 writel(enable, dev->base + PTSCR);
1618 for (;;) {
1619 loops++;
1620 status = readl(dev->base + PTSCR);
1621 if (!(status & enable))
1622 break;
1623 if (status & done)
1624 break;
1625 if (status & fail)
1626 break;
1627 if ((jiffies - start) >= HZ) {
1628 timed_out = 1;
1629 break;
1630 }
1631 schedule_timeout_uninterruptible(1);
1632 }
1633
1634 if (status & fail)
1635 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1636 ndev->name, name, status, fail);
1637 else if (timed_out)
1638 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1639 ndev->name, name, status);
1640
1641 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1642 }
1643
1644 #ifdef PHY_CODE_IS_FINISHED
1645 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1646 {
1647 /* drive MDC low */
1648 dev->MEAR_cache &= ~MEAR_MDC;
1649 writel(dev->MEAR_cache, dev->base + MEAR);
1650 readl(dev->base + MEAR);
1651
1652 /* enable output, set bit */
1653 dev->MEAR_cache |= MEAR_MDDIR;
1654 if (bit)
1655 dev->MEAR_cache |= MEAR_MDIO;
1656 else
1657 dev->MEAR_cache &= ~MEAR_MDIO;
1658
1659 /* set the output bit */
1660 writel(dev->MEAR_cache, dev->base + MEAR);
1661 readl(dev->base + MEAR);
1662
1663 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1664 udelay(1);
1665
1666 /* drive MDC high causing the data bit to be latched */
1667 dev->MEAR_cache |= MEAR_MDC;
1668 writel(dev->MEAR_cache, dev->base + MEAR);
1669 readl(dev->base + MEAR);
1670
1671 /* Wait again... */
1672 udelay(1);
1673 }
1674
1675 static int ns83820_mii_read_bit(struct ns83820 *dev)
1676 {
1677 int bit;
1678
1679 /* drive MDC low, disable output */
1680 dev->MEAR_cache &= ~MEAR_MDC;
1681 dev->MEAR_cache &= ~MEAR_MDDIR;
1682 writel(dev->MEAR_cache, dev->base + MEAR);
1683 readl(dev->base + MEAR);
1684
1685 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1686 udelay(1);
1687
1688 /* drive MDC high causing the data bit to be latched */
1689 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1690 dev->MEAR_cache |= MEAR_MDC;
1691 writel(dev->MEAR_cache, dev->base + MEAR);
1692
1693 /* Wait again... */
1694 udelay(1);
1695
1696 return bit;
1697 }
1698
1699 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1700 {
1701 unsigned data = 0;
1702 int i;
1703
1704 /* read some garbage so that we eventually sync up */
1705 for (i=0; i<64; i++)
1706 ns83820_mii_read_bit(dev);
1707
1708 ns83820_mii_write_bit(dev, 0); /* start */
1709 ns83820_mii_write_bit(dev, 1);
1710 ns83820_mii_write_bit(dev, 1); /* opcode read */
1711 ns83820_mii_write_bit(dev, 0);
1712
1713 /* write out the phy address: 5 bits, msb first */
1714 for (i=0; i<5; i++)
1715 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1716
1717 /* write out the register address, 5 bits, msb first */
1718 for (i=0; i<5; i++)
1719 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1720
1721 ns83820_mii_read_bit(dev); /* turn around cycles */
1722 ns83820_mii_read_bit(dev);
1723
1724 /* read in the register data, 16 bits msb first */
1725 for (i=0; i<16; i++) {
1726 data <<= 1;
1727 data |= ns83820_mii_read_bit(dev);
1728 }
1729
1730 return data;
1731 }
1732
1733 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1734 {
1735 int i;
1736
1737 /* read some garbage so that we eventually sync up */
1738 for (i=0; i<64; i++)
1739 ns83820_mii_read_bit(dev);
1740
1741 ns83820_mii_write_bit(dev, 0); /* start */
1742 ns83820_mii_write_bit(dev, 1);
1743 ns83820_mii_write_bit(dev, 0); /* opcode read */
1744 ns83820_mii_write_bit(dev, 1);
1745
1746 /* write out the phy address: 5 bits, msb first */
1747 for (i=0; i<5; i++)
1748 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1749
1750 /* write out the register address, 5 bits, msb first */
1751 for (i=0; i<5; i++)
1752 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1753
1754 ns83820_mii_read_bit(dev); /* turn around cycles */
1755 ns83820_mii_read_bit(dev);
1756
1757 /* read in the register data, 16 bits msb first */
1758 for (i=0; i<16; i++)
1759 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1760
1761 return data;
1762 }
1763
1764 static void ns83820_probe_phy(struct net_device *ndev)
1765 {
1766 struct ns83820 *dev = PRIV(ndev);
1767 static int first;
1768 int i;
1769 #define MII_PHYIDR1 0x02
1770 #define MII_PHYIDR2 0x03
1771
1772 #if 0
1773 if (!first) {
1774 unsigned tmp;
1775 ns83820_mii_read_reg(dev, 1, 0x09);
1776 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1777
1778 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1779 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1780 udelay(1300);
1781 ns83820_mii_read_reg(dev, 1, 0x09);
1782 }
1783 #endif
1784 first = 1;
1785
1786 for (i=1; i<2; i++) {
1787 int j;
1788 unsigned a, b;
1789 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1790 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1791
1792 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1793 // ndev->name, i, a, b);
1794
1795 for (j=0; j<0x16; j+=4) {
1796 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1797 ndev->name, j,
1798 ns83820_mii_read_reg(dev, i, 0 + j),
1799 ns83820_mii_read_reg(dev, i, 1 + j),
1800 ns83820_mii_read_reg(dev, i, 2 + j),
1801 ns83820_mii_read_reg(dev, i, 3 + j)
1802 );
1803 }
1804 }
1805 {
1806 unsigned a, b;
1807 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1808 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1809 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1810 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1811
1812 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1813 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1814 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1815 dprintk("version: 0x%04x 0x%04x\n", a, b);
1816 }
1817 }
1818 #endif
1819
1820 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
1821 {
1822 struct net_device *ndev;
1823 struct ns83820 *dev;
1824 long addr;
1825 int err;
1826 int using_dac = 0;
1827
1828 /* See if we can set the dma mask early on; failure is fatal. */
1829 if (sizeof(dma_addr_t) == 8 &&
1830 !pci_set_dma_mask(pci_dev, 0xffffffffffffffffULL)) {
1831 using_dac = 1;
1832 } else if (!pci_set_dma_mask(pci_dev, 0xffffffff)) {
1833 using_dac = 0;
1834 } else {
1835 printk(KERN_WARNING "ns83820.c: pci_set_dma_mask failed!\n");
1836 return -ENODEV;
1837 }
1838
1839 ndev = alloc_etherdev(sizeof(struct ns83820));
1840 dev = PRIV(ndev);
1841 err = -ENOMEM;
1842 if (!dev)
1843 goto out;
1844
1845 spin_lock_init(&dev->rx_info.lock);
1846 spin_lock_init(&dev->tx_lock);
1847 spin_lock_init(&dev->misc_lock);
1848 dev->pci_dev = pci_dev;
1849
1850 SET_MODULE_OWNER(ndev);
1851 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1852
1853 INIT_WORK(&dev->tq_refill, queue_refill, ndev);
1854 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1855
1856 err = pci_enable_device(pci_dev);
1857 if (err) {
1858 printk(KERN_INFO "ns83820: pci_enable_dev failed: %d\n", err);
1859 goto out_free;
1860 }
1861
1862 pci_set_master(pci_dev);
1863 addr = pci_resource_start(pci_dev, 1);
1864 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1865 dev->tx_descs = pci_alloc_consistent(pci_dev,
1866 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1867 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
1868 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
1869 err = -ENOMEM;
1870 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1871 goto out_disable;
1872
1873 dprintk("%p: %08lx %p: %08lx\n",
1874 dev->tx_descs, (long)dev->tx_phy_descs,
1875 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1876
1877 /* disable interrupts */
1878 writel(0, dev->base + IMR);
1879 writel(0, dev->base + IER);
1880 readl(dev->base + IER);
1881
1882 dev->IMR_cache = 0;
1883
1884 err = request_irq(pci_dev->irq, ns83820_irq, SA_SHIRQ,
1885 DRV_NAME, ndev);
1886 if (err) {
1887 printk(KERN_INFO "ns83820: unable to register irq %d\n",
1888 pci_dev->irq);
1889 goto out_disable;
1890 }
1891
1892 /*
1893 * FIXME: we are holding rtnl_lock() over obscenely long area only
1894 * because some of the setup code uses dev->name. It's Wrong(tm) -
1895 * we should be using driver-specific names for all that stuff.
1896 * For now that will do, but we really need to come back and kill
1897 * most of the dev_alloc_name() users later.
1898 */
1899 rtnl_lock();
1900 err = dev_alloc_name(ndev, ndev->name);
1901 if (err < 0) {
1902 printk(KERN_INFO "ns83820: unable to get netdev name: %d\n", err);
1903 goto out_free_irq;
1904 }
1905
1906 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1907 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1908 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1909
1910 ndev->open = ns83820_open;
1911 ndev->stop = ns83820_stop;
1912 ndev->hard_start_xmit = ns83820_hard_start_xmit;
1913 ndev->get_stats = ns83820_get_stats;
1914 ndev->change_mtu = ns83820_change_mtu;
1915 ndev->set_multicast_list = ns83820_set_multicast;
1916 SET_ETHTOOL_OPS(ndev, &ops);
1917 ndev->tx_timeout = ns83820_tx_timeout;
1918 ndev->watchdog_timeo = 5 * HZ;
1919 pci_set_drvdata(pci_dev, ndev);
1920
1921 ns83820_do_reset(dev, CR_RST);
1922
1923 /* Must reset the ram bist before running it */
1924 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1925 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
1926 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1927 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1928 PTSCR_EEBIST_FAIL);
1929 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
1930
1931 /* I love config registers */
1932 dev->CFG_cache = readl(dev->base + CFG);
1933
1934 if ((dev->CFG_cache & CFG_PCI64_DET)) {
1935 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
1936 ndev->name);
1937 /*dev->CFG_cache |= CFG_DATA64_EN;*/
1938 if (!(dev->CFG_cache & CFG_DATA64_EN))
1939 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
1940 ndev->name);
1941 } else
1942 dev->CFG_cache &= ~(CFG_DATA64_EN);
1943
1944 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
1945 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
1946 CFG_M64ADDR);
1947 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
1948 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
1949 dev->CFG_cache |= CFG_REQALG;
1950 dev->CFG_cache |= CFG_POW;
1951 dev->CFG_cache |= CFG_TMRTEST;
1952
1953 /* When compiled with 64 bit addressing, we must always enable
1954 * the 64 bit descriptor format.
1955 */
1956 if (sizeof(dma_addr_t) == 8)
1957 dev->CFG_cache |= CFG_M64ADDR;
1958 if (using_dac)
1959 dev->CFG_cache |= CFG_T64ADDR;
1960
1961 /* Big endian mode does not seem to do what the docs suggest */
1962 dev->CFG_cache &= ~CFG_BEM;
1963
1964 /* setup optical transceiver if we have one */
1965 if (dev->CFG_cache & CFG_TBI_EN) {
1966 printk(KERN_INFO "%s: enabling optical transceiver\n",
1967 ndev->name);
1968 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
1969
1970 /* setup auto negotiation feature advertisement */
1971 writel(readl(dev->base + TANAR)
1972 | TANAR_HALF_DUP | TANAR_FULL_DUP,
1973 dev->base + TANAR);
1974
1975 /* start auto negotiation */
1976 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1977 dev->base + TBICR);
1978 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1979 dev->linkstate = LINK_AUTONEGOTIATE;
1980
1981 dev->CFG_cache |= CFG_MODE_1000;
1982 }
1983
1984 writel(dev->CFG_cache, dev->base + CFG);
1985 dprintk("CFG: %08x\n", dev->CFG_cache);
1986
1987 if (reset_phy) {
1988 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
1989 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
1990 msleep(10);
1991 writel(dev->CFG_cache, dev->base + CFG);
1992 }
1993
1994 #if 0 /* Huh? This sets the PCI latency register. Should be done via
1995 * the PCI layer. FIXME.
1996 */
1997 if (readl(dev->base + SRR))
1998 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
1999 #endif
2000
2001 /* Note! The DMA burst size interacts with packet
2002 * transmission, such that the largest packet that
2003 * can be transmitted is 8192 - FLTH - burst size.
2004 * If only the transmit fifo was larger...
2005 */
2006 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2007 * some DELL and COMPAQ SMP systems */
2008 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2009 | ((1600 / 32) * 0x100),
2010 dev->base + TXCFG);
2011
2012 /* Flush the interrupt holdoff timer */
2013 writel(0x000, dev->base + IHR);
2014 writel(0x100, dev->base + IHR);
2015 writel(0x000, dev->base + IHR);
2016
2017 /* Set Rx to full duplex, don't accept runt, errored, long or length
2018 * range errored packets. Use 512 byte DMA.
2019 */
2020 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2021 * some DELL and COMPAQ SMP systems
2022 * Turn on ALP, only we are accpeting Jumbo Packets */
2023 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2024 | RXCFG_STRIPCRC
2025 //| RXCFG_ALP
2026 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2027
2028 /* Disable priority queueing */
2029 writel(0, dev->base + PQCR);
2030
2031 /* Enable IP checksum validation and detetion of VLAN headers.
2032 * Note: do not set the reject options as at least the 0x102
2033 * revision of the chip does not properly accept IP fragments
2034 * at least for UDP.
2035 */
2036 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2037 * the MAC it calculates the packetsize AFTER stripping the VLAN
2038 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2039 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2040 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2041 * it discrards it!. These guys......
2042 * also turn on tag stripping if hardware acceleration is enabled
2043 */
2044 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2045 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2046 #else
2047 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2048 #endif
2049 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2050
2051 /* Enable per-packet TCP/UDP/IP checksumming
2052 * and per packet vlan tag insertion if
2053 * vlan hardware acceleration is enabled
2054 */
2055 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2056 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2057 #else
2058 #define VTCR_INIT_VALUE VTCR_PPCHK
2059 #endif
2060 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2061
2062 /* Ramit : Enable async and sync pause frames */
2063 /* writel(0, dev->base + PCR); */
2064 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2065 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2066 dev->base + PCR);
2067
2068 /* Disable Wake On Lan */
2069 writel(0, dev->base + WCSR);
2070
2071 ns83820_getmac(dev, ndev->dev_addr);
2072
2073 /* Yes, we support dumb IP checksum on transmit */
2074 ndev->features |= NETIF_F_SG;
2075 ndev->features |= NETIF_F_IP_CSUM;
2076
2077 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2078 /* We also support hardware vlan acceleration */
2079 ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2080 ndev->vlan_rx_register = ns83820_vlan_rx_register;
2081 ndev->vlan_rx_kill_vid = ns83820_vlan_rx_kill_vid;
2082 #endif
2083
2084 if (using_dac) {
2085 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2086 ndev->name);
2087 ndev->features |= NETIF_F_HIGHDMA;
2088 }
2089
2090 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n",
2091 ndev->name,
2092 (unsigned)readl(dev->base + SRR) >> 8,
2093 (unsigned)readl(dev->base + SRR) & 0xff,
2094 ndev->dev_addr[0], ndev->dev_addr[1],
2095 ndev->dev_addr[2], ndev->dev_addr[3],
2096 ndev->dev_addr[4], ndev->dev_addr[5],
2097 addr, pci_dev->irq,
2098 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2099 );
2100
2101 #ifdef PHY_CODE_IS_FINISHED
2102 ns83820_probe_phy(ndev);
2103 #endif
2104
2105 err = register_netdevice(ndev);
2106 if (err) {
2107 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2108 goto out_cleanup;
2109 }
2110 rtnl_unlock();
2111
2112 return 0;
2113
2114 out_cleanup:
2115 writel(0, dev->base + IMR); /* paranoia */
2116 writel(0, dev->base + IER);
2117 readl(dev->base + IER);
2118 out_free_irq:
2119 rtnl_unlock();
2120 free_irq(pci_dev->irq, ndev);
2121 out_disable:
2122 if (dev->base)
2123 iounmap(dev->base);
2124 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2125 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2126 pci_disable_device(pci_dev);
2127 out_free:
2128 free_netdev(ndev);
2129 pci_set_drvdata(pci_dev, NULL);
2130 out:
2131 return err;
2132 }
2133
2134 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2135 {
2136 struct net_device *ndev = pci_get_drvdata(pci_dev);
2137 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2138
2139 if (!ndev) /* paranoia */
2140 return;
2141
2142 writel(0, dev->base + IMR); /* paranoia */
2143 writel(0, dev->base + IER);
2144 readl(dev->base + IER);
2145
2146 unregister_netdev(ndev);
2147 free_irq(dev->pci_dev->irq, ndev);
2148 iounmap(dev->base);
2149 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2150 dev->tx_descs, dev->tx_phy_descs);
2151 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2152 dev->rx_info.descs, dev->rx_info.phy_descs);
2153 pci_disable_device(dev->pci_dev);
2154 free_netdev(ndev);
2155 pci_set_drvdata(pci_dev, NULL);
2156 }
2157
2158 static struct pci_device_id ns83820_pci_tbl[] = {
2159 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2160 { 0, },
2161 };
2162
2163 static struct pci_driver driver = {
2164 .name = "ns83820",
2165 .id_table = ns83820_pci_tbl,
2166 .probe = ns83820_init_one,
2167 .remove = __devexit_p(ns83820_remove_one),
2168 #if 0 /* FIXME: implement */
2169 .suspend = ,
2170 .resume = ,
2171 #endif
2172 };
2173
2174
2175 static int __init ns83820_init(void)
2176 {
2177 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2178 return pci_module_init(&driver);
2179 }
2180
2181 static void __exit ns83820_exit(void)
2182 {
2183 pci_unregister_driver(&driver);
2184 }
2185
2186 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2187 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2188 MODULE_LICENSE("GPL");
2189
2190 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2191
2192 module_param(lnksts, int, 0);
2193 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2194
2195 module_param(ihr, int, 0);
2196 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2197
2198 module_param(reset_phy, int, 0);
2199 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2200
2201 module_init(ns83820_init);
2202 module_exit(ns83820_exit);
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