1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/percpu.h>
27 #include <linux/lmb.h>
30 #include <asm/system.h>
32 #include <asm/pgalloc.h>
33 #include <asm/pgtable.h>
34 #include <asm/oplib.h>
35 #include <asm/iommu.h>
37 #include <asm/uaccess.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
41 #include <asm/starfire.h>
43 #include <asm/spitfire.h>
44 #include <asm/sections.h>
46 #include <asm/hypervisor.h>
48 #include <asm/sstate.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
52 #define MAX_PHYS_ADDRESS (1UL << 42UL)
53 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
54 #define KPTE_BITMAP_BYTES \
55 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
57 unsigned long kern_linear_pte_xor
[2] __read_mostly
;
59 /* A bitmap, one bit for every 256MB of physical memory. If the bit
60 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
61 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
63 unsigned long kpte_linear_bitmap
[KPTE_BITMAP_BYTES
/ sizeof(unsigned long)];
65 #ifndef CONFIG_DEBUG_PAGEALLOC
66 /* A special kernel TSB for 4MB and 256MB linear mappings.
67 * Space is allocated for this right after the trap table
68 * in arch/sparc64/kernel/head.S
70 extern struct tsb swapper_4m_tsb
[KERNEL_TSB4M_NENTRIES
];
75 static struct linux_prom64_registers pavail
[MAX_BANKS
] __initdata
;
76 static struct linux_prom64_registers pavail_rescan
[MAX_BANKS
] __initdata
;
77 static int pavail_ents __initdata
;
78 static int pavail_rescan_ents __initdata
;
80 static int cmp_p64(const void *a
, const void *b
)
82 const struct linux_prom64_registers
*x
= a
, *y
= b
;
84 if (x
->phys_addr
> y
->phys_addr
)
86 if (x
->phys_addr
< y
->phys_addr
)
91 static void __init
read_obp_memory(const char *property
,
92 struct linux_prom64_registers
*regs
,
95 int node
= prom_finddevice("/memory");
96 int prop_size
= prom_getproplen(node
, property
);
99 ents
= prop_size
/ sizeof(struct linux_prom64_registers
);
100 if (ents
> MAX_BANKS
) {
101 prom_printf("The machine has more %s property entries than "
102 "this kernel can support (%d).\n",
103 property
, MAX_BANKS
);
107 ret
= prom_getproperty(node
, property
, (char *) regs
, prop_size
);
109 prom_printf("Couldn't get %s property from /memory.\n");
113 /* Sanitize what we got from the firmware, by page aligning
116 for (i
= 0; i
< ents
; i
++) {
117 unsigned long base
, size
;
119 base
= regs
[i
].phys_addr
;
120 size
= regs
[i
].reg_size
;
123 if (base
& ~PAGE_MASK
) {
124 unsigned long new_base
= PAGE_ALIGN(base
);
126 size
-= new_base
- base
;
127 if ((long) size
< 0L)
132 /* If it is empty, simply get rid of it.
133 * This simplifies the logic of the other
134 * functions that process these arrays.
136 memmove(®s
[i
], ®s
[i
+ 1],
137 (ents
- i
- 1) * sizeof(regs
[0]));
142 regs
[i
].phys_addr
= base
;
143 regs
[i
].reg_size
= size
;
148 sort(regs
, ents
, sizeof(struct linux_prom64_registers
),
152 unsigned long *sparc64_valid_addr_bitmap __read_mostly
;
154 /* Kernel physical address base and size in bytes. */
155 unsigned long kern_base __read_mostly
;
156 unsigned long kern_size __read_mostly
;
158 /* Initial ramdisk setup */
159 extern unsigned long sparc_ramdisk_image64
;
160 extern unsigned int sparc_ramdisk_image
;
161 extern unsigned int sparc_ramdisk_size
;
163 struct page
*mem_map_zero __read_mostly
;
165 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly
;
167 unsigned long sparc64_kern_pri_context __read_mostly
;
168 unsigned long sparc64_kern_pri_nuc_bits __read_mostly
;
169 unsigned long sparc64_kern_sec_context __read_mostly
;
171 int num_kernel_image_mappings
;
173 #ifdef CONFIG_DEBUG_DCFLUSH
174 atomic_t dcpage_flushes
= ATOMIC_INIT(0);
176 atomic_t dcpage_flushes_xcall
= ATOMIC_INIT(0);
180 inline void flush_dcache_page_impl(struct page
*page
)
182 BUG_ON(tlb_type
== hypervisor
);
183 #ifdef CONFIG_DEBUG_DCFLUSH
184 atomic_inc(&dcpage_flushes
);
187 #ifdef DCACHE_ALIASING_POSSIBLE
188 __flush_dcache_page(page_address(page
),
189 ((tlb_type
== spitfire
) &&
190 page_mapping(page
) != NULL
));
192 if (page_mapping(page
) != NULL
&&
193 tlb_type
== spitfire
)
194 __flush_icache_page(__pa(page_address(page
)));
198 #define PG_dcache_dirty PG_arch_1
199 #define PG_dcache_cpu_shift 32UL
200 #define PG_dcache_cpu_mask \
201 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
203 #define dcache_dirty_cpu(page) \
204 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
206 static inline void set_dcache_dirty(struct page
*page
, int this_cpu
)
208 unsigned long mask
= this_cpu
;
209 unsigned long non_cpu_bits
;
211 non_cpu_bits
= ~(PG_dcache_cpu_mask
<< PG_dcache_cpu_shift
);
212 mask
= (mask
<< PG_dcache_cpu_shift
) | (1UL << PG_dcache_dirty
);
214 __asm__
__volatile__("1:\n\t"
216 "and %%g7, %1, %%g1\n\t"
217 "or %%g1, %0, %%g1\n\t"
218 "casx [%2], %%g7, %%g1\n\t"
220 "membar #StoreLoad | #StoreStore\n\t"
221 "bne,pn %%xcc, 1b\n\t"
224 : "r" (mask
), "r" (non_cpu_bits
), "r" (&page
->flags
)
228 static inline void clear_dcache_dirty_cpu(struct page
*page
, unsigned long cpu
)
230 unsigned long mask
= (1UL << PG_dcache_dirty
);
232 __asm__
__volatile__("! test_and_clear_dcache_dirty\n"
235 "srlx %%g7, %4, %%g1\n\t"
236 "and %%g1, %3, %%g1\n\t"
238 "bne,pn %%icc, 2f\n\t"
239 " andn %%g7, %1, %%g1\n\t"
240 "casx [%2], %%g7, %%g1\n\t"
242 "membar #StoreLoad | #StoreStore\n\t"
243 "bne,pn %%xcc, 1b\n\t"
247 : "r" (cpu
), "r" (mask
), "r" (&page
->flags
),
248 "i" (PG_dcache_cpu_mask
),
249 "i" (PG_dcache_cpu_shift
)
253 static inline void tsb_insert(struct tsb
*ent
, unsigned long tag
, unsigned long pte
)
255 unsigned long tsb_addr
= (unsigned long) ent
;
257 if (tlb_type
== cheetah_plus
|| tlb_type
== hypervisor
)
258 tsb_addr
= __pa(tsb_addr
);
260 __tsb_insert(tsb_addr
, tag
, pte
);
263 unsigned long _PAGE_ALL_SZ_BITS __read_mostly
;
264 unsigned long _PAGE_SZBITS __read_mostly
;
266 void update_mmu_cache(struct vm_area_struct
*vma
, unsigned long address
, pte_t pte
)
268 struct mm_struct
*mm
;
270 unsigned long tag
, flags
;
271 unsigned long tsb_index
, tsb_hash_shift
;
273 if (tlb_type
!= hypervisor
) {
274 unsigned long pfn
= pte_pfn(pte
);
275 unsigned long pg_flags
;
278 if (pfn_valid(pfn
) &&
279 (page
= pfn_to_page(pfn
), page_mapping(page
)) &&
280 ((pg_flags
= page
->flags
) & (1UL << PG_dcache_dirty
))) {
281 int cpu
= ((pg_flags
>> PG_dcache_cpu_shift
) &
283 int this_cpu
= get_cpu();
285 /* This is just to optimize away some function calls
289 flush_dcache_page_impl(page
);
291 smp_flush_dcache_page_impl(page
, cpu
);
293 clear_dcache_dirty_cpu(page
, cpu
);
301 tsb_index
= MM_TSB_BASE
;
302 tsb_hash_shift
= PAGE_SHIFT
;
304 spin_lock_irqsave(&mm
->context
.lock
, flags
);
306 #ifdef CONFIG_HUGETLB_PAGE
307 if (mm
->context
.tsb_block
[MM_TSB_HUGE
].tsb
!= NULL
) {
308 if ((tlb_type
== hypervisor
&&
309 (pte_val(pte
) & _PAGE_SZALL_4V
) == _PAGE_SZHUGE_4V
) ||
310 (tlb_type
!= hypervisor
&&
311 (pte_val(pte
) & _PAGE_SZALL_4U
) == _PAGE_SZHUGE_4U
)) {
312 tsb_index
= MM_TSB_HUGE
;
313 tsb_hash_shift
= HPAGE_SHIFT
;
318 tsb
= mm
->context
.tsb_block
[tsb_index
].tsb
;
319 tsb
+= ((address
>> tsb_hash_shift
) &
320 (mm
->context
.tsb_block
[tsb_index
].tsb_nentries
- 1UL));
321 tag
= (address
>> 22UL);
322 tsb_insert(tsb
, tag
, pte_val(pte
));
324 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
327 void flush_dcache_page(struct page
*page
)
329 struct address_space
*mapping
;
332 if (tlb_type
== hypervisor
)
335 /* Do not bother with the expensive D-cache flush if it
336 * is merely the zero page. The 'bigcore' testcase in GDB
337 * causes this case to run millions of times.
339 if (page
== ZERO_PAGE(0))
342 this_cpu
= get_cpu();
344 mapping
= page_mapping(page
);
345 if (mapping
&& !mapping_mapped(mapping
)) {
346 int dirty
= test_bit(PG_dcache_dirty
, &page
->flags
);
348 int dirty_cpu
= dcache_dirty_cpu(page
);
350 if (dirty_cpu
== this_cpu
)
352 smp_flush_dcache_page_impl(page
, dirty_cpu
);
354 set_dcache_dirty(page
, this_cpu
);
356 /* We could delay the flush for the !page_mapping
357 * case too. But that case is for exec env/arg
358 * pages and those are %99 certainly going to get
359 * faulted into the tlb (and thus flushed) anyways.
361 flush_dcache_page_impl(page
);
368 void __kprobes
flush_icache_range(unsigned long start
, unsigned long end
)
370 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
371 if (tlb_type
== spitfire
) {
374 /* This code only runs on Spitfire cpus so this is
375 * why we can assume _PAGE_PADDR_4U.
377 for (kaddr
= start
; kaddr
< end
; kaddr
+= PAGE_SIZE
) {
378 unsigned long paddr
, mask
= _PAGE_PADDR_4U
;
380 if (kaddr
>= PAGE_OFFSET
)
381 paddr
= kaddr
& mask
;
383 pgd_t
*pgdp
= pgd_offset_k(kaddr
);
384 pud_t
*pudp
= pud_offset(pgdp
, kaddr
);
385 pmd_t
*pmdp
= pmd_offset(pudp
, kaddr
);
386 pte_t
*ptep
= pte_offset_kernel(pmdp
, kaddr
);
388 paddr
= pte_val(*ptep
) & mask
;
390 __flush_icache_page(paddr
);
397 unsigned long total
= 0, reserved
= 0;
398 unsigned long shared
= 0, cached
= 0;
401 printk(KERN_INFO
"Mem-info:\n");
403 printk(KERN_INFO
"Free swap: %6ldkB\n",
404 nr_swap_pages
<< (PAGE_SHIFT
-10));
405 for_each_online_pgdat(pgdat
) {
406 unsigned long i
, flags
;
408 pgdat_resize_lock(pgdat
, &flags
);
409 for (i
= 0; i
< pgdat
->node_spanned_pages
; i
++) {
410 struct page
*page
= pgdat_page_nr(pgdat
, i
);
412 if (PageReserved(page
))
414 else if (PageSwapCache(page
))
416 else if (page_count(page
))
417 shared
+= page_count(page
) - 1;
419 pgdat_resize_unlock(pgdat
, &flags
);
422 printk(KERN_INFO
"%lu pages of RAM\n", total
);
423 printk(KERN_INFO
"%lu reserved pages\n", reserved
);
424 printk(KERN_INFO
"%lu pages shared\n", shared
);
425 printk(KERN_INFO
"%lu pages swap cached\n", cached
);
427 printk(KERN_INFO
"%lu pages dirty\n",
428 global_page_state(NR_FILE_DIRTY
));
429 printk(KERN_INFO
"%lu pages writeback\n",
430 global_page_state(NR_WRITEBACK
));
431 printk(KERN_INFO
"%lu pages mapped\n",
432 global_page_state(NR_FILE_MAPPED
));
433 printk(KERN_INFO
"%lu pages slab\n",
434 global_page_state(NR_SLAB_RECLAIMABLE
) +
435 global_page_state(NR_SLAB_UNRECLAIMABLE
));
436 printk(KERN_INFO
"%lu pages pagetables\n",
437 global_page_state(NR_PAGETABLE
));
440 void mmu_info(struct seq_file
*m
)
442 if (tlb_type
== cheetah
)
443 seq_printf(m
, "MMU Type\t: Cheetah\n");
444 else if (tlb_type
== cheetah_plus
)
445 seq_printf(m
, "MMU Type\t: Cheetah+\n");
446 else if (tlb_type
== spitfire
)
447 seq_printf(m
, "MMU Type\t: Spitfire\n");
448 else if (tlb_type
== hypervisor
)
449 seq_printf(m
, "MMU Type\t: Hypervisor (sun4v)\n");
451 seq_printf(m
, "MMU Type\t: ???\n");
453 #ifdef CONFIG_DEBUG_DCFLUSH
454 seq_printf(m
, "DCPageFlushes\t: %d\n",
455 atomic_read(&dcpage_flushes
));
457 seq_printf(m
, "DCPageFlushesXC\t: %d\n",
458 atomic_read(&dcpage_flushes_xcall
));
459 #endif /* CONFIG_SMP */
460 #endif /* CONFIG_DEBUG_DCFLUSH */
463 struct linux_prom_translation
{
469 /* Exported for kernel TLB miss handling in ktlb.S */
470 struct linux_prom_translation prom_trans
[512] __read_mostly
;
471 unsigned int prom_trans_ents __read_mostly
;
473 /* Exported for SMP bootup purposes. */
474 unsigned long kern_locked_tte_data
;
476 /* The obp translations are saved based on 8k pagesize, since obp can
477 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
478 * HI_OBP_ADDRESS range are handled in ktlb.S.
480 static inline int in_obp_range(unsigned long vaddr
)
482 return (vaddr
>= LOW_OBP_ADDRESS
&&
483 vaddr
< HI_OBP_ADDRESS
);
486 static int cmp_ptrans(const void *a
, const void *b
)
488 const struct linux_prom_translation
*x
= a
, *y
= b
;
490 if (x
->virt
> y
->virt
)
492 if (x
->virt
< y
->virt
)
497 /* Read OBP translations property into 'prom_trans[]'. */
498 static void __init
read_obp_translations(void)
500 int n
, node
, ents
, first
, last
, i
;
502 node
= prom_finddevice("/virtual-memory");
503 n
= prom_getproplen(node
, "translations");
504 if (unlikely(n
== 0 || n
== -1)) {
505 prom_printf("prom_mappings: Couldn't get size.\n");
508 if (unlikely(n
> sizeof(prom_trans
))) {
509 prom_printf("prom_mappings: Size %Zd is too big.\n", n
);
513 if ((n
= prom_getproperty(node
, "translations",
514 (char *)&prom_trans
[0],
515 sizeof(prom_trans
))) == -1) {
516 prom_printf("prom_mappings: Couldn't get property.\n");
520 n
= n
/ sizeof(struct linux_prom_translation
);
524 sort(prom_trans
, ents
, sizeof(struct linux_prom_translation
),
527 /* Now kick out all the non-OBP entries. */
528 for (i
= 0; i
< ents
; i
++) {
529 if (in_obp_range(prom_trans
[i
].virt
))
533 for (; i
< ents
; i
++) {
534 if (!in_obp_range(prom_trans
[i
].virt
))
539 for (i
= 0; i
< (last
- first
); i
++) {
540 struct linux_prom_translation
*src
= &prom_trans
[i
+ first
];
541 struct linux_prom_translation
*dest
= &prom_trans
[i
];
545 for (; i
< ents
; i
++) {
546 struct linux_prom_translation
*dest
= &prom_trans
[i
];
547 dest
->virt
= dest
->size
= dest
->data
= 0x0UL
;
550 prom_trans_ents
= last
- first
;
552 if (tlb_type
== spitfire
) {
553 /* Clear diag TTE bits. */
554 for (i
= 0; i
< prom_trans_ents
; i
++)
555 prom_trans
[i
].data
&= ~0x0003fe0000000000UL
;
559 static void __init
hypervisor_tlb_lock(unsigned long vaddr
,
563 unsigned long ret
= sun4v_mmu_map_perm_addr(vaddr
, 0, pte
, mmu
);
566 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
567 "errors with %lx\n", vaddr
, 0, pte
, mmu
, ret
);
572 static unsigned long kern_large_tte(unsigned long paddr
);
574 static void __init
remap_kernel(void)
576 unsigned long phys_page
, tte_vaddr
, tte_data
;
577 int i
, tlb_ent
= sparc64_highest_locked_tlbent();
579 tte_vaddr
= (unsigned long) KERNBASE
;
580 phys_page
= (prom_boot_mapping_phys_low
>> 22UL) << 22UL;
581 tte_data
= kern_large_tte(phys_page
);
583 kern_locked_tte_data
= tte_data
;
585 /* Now lock us into the TLBs via Hypervisor or OBP. */
586 if (tlb_type
== hypervisor
) {
587 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
588 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_DMMU
);
589 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_IMMU
);
590 tte_vaddr
+= 0x400000;
591 tte_data
+= 0x400000;
594 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
595 prom_dtlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
596 prom_itlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
597 tte_vaddr
+= 0x400000;
598 tte_data
+= 0x400000;
600 sparc64_highest_unlocked_tlb_ent
= tlb_ent
- i
;
602 if (tlb_type
== cheetah_plus
) {
603 sparc64_kern_pri_context
= (CTX_CHEETAH_PLUS_CTX0
|
604 CTX_CHEETAH_PLUS_NUC
);
605 sparc64_kern_pri_nuc_bits
= CTX_CHEETAH_PLUS_NUC
;
606 sparc64_kern_sec_context
= CTX_CHEETAH_PLUS_CTX0
;
611 static void __init
inherit_prom_mappings(void)
613 read_obp_translations();
615 /* Now fixup OBP's idea about where we really are mapped. */
616 printk("Remapping the kernel... ");
621 void prom_world(int enter
)
624 set_fs((mm_segment_t
) { get_thread_current_ds() });
626 __asm__
__volatile__("flushw");
629 void __flush_dcache_range(unsigned long start
, unsigned long end
)
633 if (tlb_type
== spitfire
) {
636 for (va
= start
; va
< end
; va
+= 32) {
637 spitfire_put_dcache_tag(va
& 0x3fe0, 0x0);
641 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
644 for (va
= start
; va
< end
; va
+= 32)
645 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
649 "i" (ASI_DCACHE_INVALIDATE
));
653 /* get_new_mmu_context() uses "cache + 1". */
654 DEFINE_SPINLOCK(ctx_alloc_lock
);
655 unsigned long tlb_context_cache
= CTX_FIRST_VERSION
- 1;
656 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
657 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
658 DECLARE_BITMAP(mmu_context_bmap
, MAX_CTX_NR
);
660 /* Caller does TLB context flushing on local CPU if necessary.
661 * The caller also ensures that CTX_VALID(mm->context) is false.
663 * We must be careful about boundary cases so that we never
664 * let the user have CTX 0 (nucleus) or we ever use a CTX
665 * version of zero (and thus NO_CONTEXT would not be caught
666 * by version mis-match tests in mmu_context.h).
668 * Always invoked with interrupts disabled.
670 void get_new_mmu_context(struct mm_struct
*mm
)
672 unsigned long ctx
, new_ctx
;
673 unsigned long orig_pgsz_bits
;
677 spin_lock_irqsave(&ctx_alloc_lock
, flags
);
678 orig_pgsz_bits
= (mm
->context
.sparc64_ctx_val
& CTX_PGSZ_MASK
);
679 ctx
= (tlb_context_cache
+ 1) & CTX_NR_MASK
;
680 new_ctx
= find_next_zero_bit(mmu_context_bmap
, 1 << CTX_NR_BITS
, ctx
);
682 if (new_ctx
>= (1 << CTX_NR_BITS
)) {
683 new_ctx
= find_next_zero_bit(mmu_context_bmap
, ctx
, 1);
684 if (new_ctx
>= ctx
) {
686 new_ctx
= (tlb_context_cache
& CTX_VERSION_MASK
) +
689 new_ctx
= CTX_FIRST_VERSION
;
691 /* Don't call memset, for 16 entries that's just
694 mmu_context_bmap
[0] = 3;
695 mmu_context_bmap
[1] = 0;
696 mmu_context_bmap
[2] = 0;
697 mmu_context_bmap
[3] = 0;
698 for (i
= 4; i
< CTX_BMAP_SLOTS
; i
+= 4) {
699 mmu_context_bmap
[i
+ 0] = 0;
700 mmu_context_bmap
[i
+ 1] = 0;
701 mmu_context_bmap
[i
+ 2] = 0;
702 mmu_context_bmap
[i
+ 3] = 0;
708 mmu_context_bmap
[new_ctx
>>6] |= (1UL << (new_ctx
& 63));
709 new_ctx
|= (tlb_context_cache
& CTX_VERSION_MASK
);
711 tlb_context_cache
= new_ctx
;
712 mm
->context
.sparc64_ctx_val
= new_ctx
| orig_pgsz_bits
;
713 spin_unlock_irqrestore(&ctx_alloc_lock
, flags
);
715 if (unlikely(new_version
))
716 smp_new_mmu_context_version();
719 /* Find a free area for the bootmem map, avoiding the kernel image
720 * and the initial ramdisk.
722 static unsigned long __init
choose_bootmap_pfn(unsigned long start_pfn
,
723 unsigned long end_pfn
)
725 unsigned long bootmap_size
;
727 bootmap_size
= bootmem_bootmap_pages(end_pfn
- start_pfn
);
728 bootmap_size
<<= PAGE_SHIFT
;
730 return lmb_alloc(bootmap_size
, PAGE_SIZE
) >> PAGE_SHIFT
;
733 static void __init
find_ramdisk(unsigned long phys_base
)
735 #ifdef CONFIG_BLK_DEV_INITRD
736 if (sparc_ramdisk_image
|| sparc_ramdisk_image64
) {
737 unsigned long ramdisk_image
;
739 /* Older versions of the bootloader only supported a
740 * 32-bit physical address for the ramdisk image
741 * location, stored at sparc_ramdisk_image. Newer
742 * SILO versions set sparc_ramdisk_image to zero and
743 * provide a full 64-bit physical address at
744 * sparc_ramdisk_image64.
746 ramdisk_image
= sparc_ramdisk_image
;
748 ramdisk_image
= sparc_ramdisk_image64
;
750 /* Another bootloader quirk. The bootloader normalizes
751 * the physical address to KERNBASE, so we have to
752 * factor that back out and add in the lowest valid
753 * physical page address to get the true physical address.
755 ramdisk_image
-= KERNBASE
;
756 ramdisk_image
+= phys_base
;
758 initrd_start
= ramdisk_image
;
759 initrd_end
= ramdisk_image
+ sparc_ramdisk_size
;
761 lmb_reserve(initrd_start
, initrd_end
);
766 /* About pages_avail, this is the value we will use to calculate
767 * the zholes_size[] argument given to free_area_init_node(). The
768 * page allocator uses this to calculate nr_kernel_pages,
769 * nr_all_pages and zone->present_pages. On NUMA it is used
770 * to calculate zone->min_unmapped_pages and zone->min_slab_pages.
772 * So this number should really be set to what the page allocator
773 * actually ends up with. This means:
774 * 1) It should include bootmem map pages, we'll release those.
775 * 2) It should not include the kernel image, except for the
776 * __init sections which we will also release.
777 * 3) It should include the initrd image, since we'll release
780 static unsigned long __init
bootmem_init(unsigned long *pages_avail
,
781 unsigned long phys_base
)
783 unsigned long end_pfn
;
786 *pages_avail
= lmb_phys_mem_size() >> PAGE_SHIFT
;
787 end_pfn
= lmb_end_of_DRAM() >> PAGE_SHIFT
;
789 /* Initialize the boot-time allocator. */
790 max_pfn
= max_low_pfn
= end_pfn
;
791 min_low_pfn
= (phys_base
>> PAGE_SHIFT
);
793 init_bootmem_node(NODE_DATA(0),
794 choose_bootmap_pfn(min_low_pfn
, end_pfn
),
795 min_low_pfn
, end_pfn
);
797 /* Now register the available physical memory with the
800 for (i
= 0; i
< lmb
.memory
.cnt
; i
++)
801 free_bootmem(lmb
.memory
.region
[i
].base
,
802 lmb_size_bytes(&lmb
.memory
, i
));
804 for (i
= 0; i
< lmb
.reserved
.cnt
; i
++)
805 reserve_bootmem(lmb
.reserved
.region
[i
].base
,
806 lmb_size_bytes(&lmb
.reserved
, i
),
809 *pages_avail
-= PAGE_ALIGN(kern_size
) >> PAGE_SHIFT
;
811 for (i
= 0; i
< lmb
.memory
.cnt
; ++i
) {
812 unsigned long start_pfn
, end_pfn
, pages
;
814 pages
= lmb_size_pages(&lmb
.memory
, i
);
815 start_pfn
= lmb
.memory
.region
[i
].base
>> PAGE_SHIFT
;
816 end_pfn
= start_pfn
+ pages
;
818 memory_present(0, start_pfn
, end_pfn
);
826 static struct linux_prom64_registers pall
[MAX_BANKS
] __initdata
;
827 static int pall_ents __initdata
;
829 #ifdef CONFIG_DEBUG_PAGEALLOC
830 static unsigned long __ref
kernel_map_range(unsigned long pstart
,
831 unsigned long pend
, pgprot_t prot
)
833 unsigned long vstart
= PAGE_OFFSET
+ pstart
;
834 unsigned long vend
= PAGE_OFFSET
+ pend
;
835 unsigned long alloc_bytes
= 0UL;
837 if ((vstart
& ~PAGE_MASK
) || (vend
& ~PAGE_MASK
)) {
838 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
843 while (vstart
< vend
) {
844 unsigned long this_end
, paddr
= __pa(vstart
);
845 pgd_t
*pgd
= pgd_offset_k(vstart
);
850 pud
= pud_offset(pgd
, vstart
);
851 if (pud_none(*pud
)) {
854 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
855 alloc_bytes
+= PAGE_SIZE
;
856 pud_populate(&init_mm
, pud
, new);
859 pmd
= pmd_offset(pud
, vstart
);
860 if (!pmd_present(*pmd
)) {
863 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
864 alloc_bytes
+= PAGE_SIZE
;
865 pmd_populate_kernel(&init_mm
, pmd
, new);
868 pte
= pte_offset_kernel(pmd
, vstart
);
869 this_end
= (vstart
+ PMD_SIZE
) & PMD_MASK
;
873 while (vstart
< this_end
) {
874 pte_val(*pte
) = (paddr
| pgprot_val(prot
));
885 extern unsigned int kvmap_linear_patch
[1];
886 #endif /* CONFIG_DEBUG_PAGEALLOC */
888 static void __init
mark_kpte_bitmap(unsigned long start
, unsigned long end
)
890 const unsigned long shift_256MB
= 28;
891 const unsigned long mask_256MB
= ((1UL << shift_256MB
) - 1UL);
892 const unsigned long size_256MB
= (1UL << shift_256MB
);
894 while (start
< end
) {
897 remains
= end
- start
;
898 if (remains
< size_256MB
)
901 if (start
& mask_256MB
) {
902 start
= (start
+ size_256MB
) & ~mask_256MB
;
906 while (remains
>= size_256MB
) {
907 unsigned long index
= start
>> shift_256MB
;
909 __set_bit(index
, kpte_linear_bitmap
);
912 remains
-= size_256MB
;
917 static void __init
init_kpte_bitmap(void)
921 for (i
= 0; i
< pall_ents
; i
++) {
922 unsigned long phys_start
, phys_end
;
924 phys_start
= pall
[i
].phys_addr
;
925 phys_end
= phys_start
+ pall
[i
].reg_size
;
927 mark_kpte_bitmap(phys_start
, phys_end
);
931 static void __init
kernel_physical_mapping_init(void)
933 #ifdef CONFIG_DEBUG_PAGEALLOC
934 unsigned long i
, mem_alloced
= 0UL;
936 for (i
= 0; i
< pall_ents
; i
++) {
937 unsigned long phys_start
, phys_end
;
939 phys_start
= pall
[i
].phys_addr
;
940 phys_end
= phys_start
+ pall
[i
].reg_size
;
942 mem_alloced
+= kernel_map_range(phys_start
, phys_end
,
946 printk("Allocated %ld bytes for kernel page tables.\n",
949 kvmap_linear_patch
[0] = 0x01000000; /* nop */
950 flushi(&kvmap_linear_patch
[0]);
956 #ifdef CONFIG_DEBUG_PAGEALLOC
957 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
959 unsigned long phys_start
= page_to_pfn(page
) << PAGE_SHIFT
;
960 unsigned long phys_end
= phys_start
+ (numpages
* PAGE_SIZE
);
962 kernel_map_range(phys_start
, phys_end
,
963 (enable
? PAGE_KERNEL
: __pgprot(0)));
965 flush_tsb_kernel_range(PAGE_OFFSET
+ phys_start
,
966 PAGE_OFFSET
+ phys_end
);
968 /* we should perform an IPI and flush all tlbs,
969 * but that can deadlock->flush only current cpu.
971 __flush_tlb_kernel_range(PAGE_OFFSET
+ phys_start
,
972 PAGE_OFFSET
+ phys_end
);
976 unsigned long __init
find_ecache_flush_span(unsigned long size
)
980 for (i
= 0; i
< pavail_ents
; i
++) {
981 if (pavail
[i
].reg_size
>= size
)
982 return pavail
[i
].phys_addr
;
988 static void __init
tsb_phys_patch(void)
990 struct tsb_ldquad_phys_patch_entry
*pquad
;
991 struct tsb_phys_patch_entry
*p
;
993 pquad
= &__tsb_ldquad_phys_patch
;
994 while (pquad
< &__tsb_ldquad_phys_patch_end
) {
995 unsigned long addr
= pquad
->addr
;
997 if (tlb_type
== hypervisor
)
998 *(unsigned int *) addr
= pquad
->sun4v_insn
;
1000 *(unsigned int *) addr
= pquad
->sun4u_insn
;
1002 __asm__
__volatile__("flush %0"
1009 p
= &__tsb_phys_patch
;
1010 while (p
< &__tsb_phys_patch_end
) {
1011 unsigned long addr
= p
->addr
;
1013 *(unsigned int *) addr
= p
->insn
;
1015 __asm__
__volatile__("flush %0"
1023 /* Don't mark as init, we give this to the Hypervisor. */
1024 #ifndef CONFIG_DEBUG_PAGEALLOC
1025 #define NUM_KTSB_DESCR 2
1027 #define NUM_KTSB_DESCR 1
1029 static struct hv_tsb_descr ktsb_descr
[NUM_KTSB_DESCR
];
1030 extern struct tsb swapper_tsb
[KERNEL_TSB_NENTRIES
];
1032 static void __init
sun4v_ktsb_init(void)
1034 unsigned long ktsb_pa
;
1036 /* First KTSB for PAGE_SIZE mappings. */
1037 ktsb_pa
= kern_base
+ ((unsigned long)&swapper_tsb
[0] - KERNBASE
);
1039 switch (PAGE_SIZE
) {
1042 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_8K
;
1043 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_8K
;
1047 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_64K
;
1048 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_64K
;
1052 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_512K
;
1053 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_512K
;
1056 case 4 * 1024 * 1024:
1057 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1058 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_4MB
;
1062 ktsb_descr
[0].assoc
= 1;
1063 ktsb_descr
[0].num_ttes
= KERNEL_TSB_NENTRIES
;
1064 ktsb_descr
[0].ctx_idx
= 0;
1065 ktsb_descr
[0].tsb_base
= ktsb_pa
;
1066 ktsb_descr
[0].resv
= 0;
1068 #ifndef CONFIG_DEBUG_PAGEALLOC
1069 /* Second KTSB for 4MB/256MB mappings. */
1070 ktsb_pa
= (kern_base
+
1071 ((unsigned long)&swapper_4m_tsb
[0] - KERNBASE
));
1073 ktsb_descr
[1].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1074 ktsb_descr
[1].pgsz_mask
= (HV_PGSZ_MASK_4MB
|
1075 HV_PGSZ_MASK_256MB
);
1076 ktsb_descr
[1].assoc
= 1;
1077 ktsb_descr
[1].num_ttes
= KERNEL_TSB4M_NENTRIES
;
1078 ktsb_descr
[1].ctx_idx
= 0;
1079 ktsb_descr
[1].tsb_base
= ktsb_pa
;
1080 ktsb_descr
[1].resv
= 0;
1084 void __cpuinit
sun4v_ktsb_register(void)
1086 unsigned long pa
, ret
;
1088 pa
= kern_base
+ ((unsigned long)&ktsb_descr
[0] - KERNBASE
);
1090 ret
= sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR
, pa
);
1092 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1093 "errors with %lx\n", pa
, ret
);
1098 /* paging_init() sets up the page tables */
1100 extern void central_probe(void);
1102 static unsigned long last_valid_pfn
;
1103 pgd_t swapper_pg_dir
[2048];
1105 static void sun4u_pgprot_init(void);
1106 static void sun4v_pgprot_init(void);
1108 /* Dummy function */
1109 void __init
setup_per_cpu_areas(void)
1113 void __init
paging_init(void)
1115 unsigned long end_pfn
, pages_avail
, shift
, phys_base
;
1116 unsigned long real_end
, i
;
1118 /* These build time checkes make sure that the dcache_dirty_cpu()
1119 * page->flags usage will work.
1121 * When a page gets marked as dcache-dirty, we store the
1122 * cpu number starting at bit 32 in the page->flags. Also,
1123 * functions like clear_dcache_dirty_cpu use the cpu mask
1124 * in 13-bit signed-immediate instruction fields.
1126 BUILD_BUG_ON(FLAGS_RESERVED
!= 32);
1127 BUILD_BUG_ON(SECTIONS_WIDTH
+ NODES_WIDTH
+ ZONES_WIDTH
+
1128 ilog2(roundup_pow_of_two(NR_CPUS
)) > FLAGS_RESERVED
);
1129 BUILD_BUG_ON(NR_CPUS
> 4096);
1131 kern_base
= (prom_boot_mapping_phys_low
>> 22UL) << 22UL;
1132 kern_size
= (unsigned long)&_end
- (unsigned long)KERNBASE
;
1136 /* Invalidate both kernel TSBs. */
1137 memset(swapper_tsb
, 0x40, sizeof(swapper_tsb
));
1138 #ifndef CONFIG_DEBUG_PAGEALLOC
1139 memset(swapper_4m_tsb
, 0x40, sizeof(swapper_4m_tsb
));
1142 if (tlb_type
== hypervisor
)
1143 sun4v_pgprot_init();
1145 sun4u_pgprot_init();
1147 if (tlb_type
== cheetah_plus
||
1148 tlb_type
== hypervisor
)
1151 if (tlb_type
== hypervisor
) {
1152 sun4v_patch_tlb_handlers();
1158 /* Find available physical memory... */
1159 read_obp_memory("available", &pavail
[0], &pavail_ents
);
1161 phys_base
= 0xffffffffffffffffUL
;
1162 for (i
= 0; i
< pavail_ents
; i
++) {
1163 phys_base
= min(phys_base
, pavail
[i
].phys_addr
);
1164 lmb_add(pavail
[i
].phys_addr
, pavail
[i
].reg_size
);
1167 lmb_reserve(kern_base
, kern_size
);
1169 find_ramdisk(phys_base
);
1171 if (cmdline_memory_size
)
1172 lmb_enforce_memory_limit(phys_base
+ cmdline_memory_size
);
1177 set_bit(0, mmu_context_bmap
);
1179 shift
= kern_base
+ PAGE_OFFSET
- ((unsigned long)KERNBASE
);
1181 real_end
= (unsigned long)_end
;
1182 num_kernel_image_mappings
= DIV_ROUND_UP(real_end
- KERNBASE
, 1 << 22);
1183 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1184 num_kernel_image_mappings
);
1186 /* Set kernel pgd to upper alias so physical page computations
1189 init_mm
.pgd
+= ((shift
) / (sizeof(pgd_t
)));
1191 memset(swapper_low_pmd_dir
, 0, sizeof(swapper_low_pmd_dir
));
1193 /* Now can init the kernel/bad page tables. */
1194 pud_set(pud_offset(&swapper_pg_dir
[0], 0),
1195 swapper_low_pmd_dir
+ (shift
/ sizeof(pgd_t
)));
1197 inherit_prom_mappings();
1199 read_obp_memory("reg", &pall
[0], &pall_ents
);
1203 /* Ok, we can use our TLB miss and window trap handlers safely. */
1208 if (tlb_type
== hypervisor
)
1209 sun4v_ktsb_register();
1211 /* We must setup the per-cpu areas before we pull in the
1212 * PROM and the MDESC. The code there fills in cpu and
1213 * other information into per-cpu data structures.
1215 real_setup_per_cpu_areas();
1217 prom_build_devicetree();
1219 /* Setup bootmem... */
1221 last_valid_pfn
= end_pfn
= bootmem_init(&pages_avail
, phys_base
);
1223 max_mapnr
= last_valid_pfn
;
1225 kernel_physical_mapping_init();
1227 if (tlb_type
== hypervisor
)
1231 unsigned long zones_size
[MAX_NR_ZONES
];
1232 unsigned long zholes_size
[MAX_NR_ZONES
];
1235 for (znum
= 0; znum
< MAX_NR_ZONES
; znum
++)
1236 zones_size
[znum
] = zholes_size
[znum
] = 0;
1238 zones_size
[ZONE_NORMAL
] = end_pfn
;
1239 zholes_size
[ZONE_NORMAL
] = end_pfn
- pages_avail
;
1241 free_area_init_node(0, &contig_page_data
, zones_size
,
1242 __pa(PAGE_OFFSET
) >> PAGE_SHIFT
,
1246 printk("Booting Linux...\n");
1252 static void __init
taint_real_pages(void)
1256 read_obp_memory("available", &pavail_rescan
[0], &pavail_rescan_ents
);
1258 /* Find changes discovered in the physmem available rescan and
1259 * reserve the lost portions in the bootmem maps.
1261 for (i
= 0; i
< pavail_ents
; i
++) {
1262 unsigned long old_start
, old_end
;
1264 old_start
= pavail
[i
].phys_addr
;
1265 old_end
= old_start
+
1267 while (old_start
< old_end
) {
1270 for (n
= 0; n
< pavail_rescan_ents
; n
++) {
1271 unsigned long new_start
, new_end
;
1273 new_start
= pavail_rescan
[n
].phys_addr
;
1274 new_end
= new_start
+
1275 pavail_rescan
[n
].reg_size
;
1277 if (new_start
<= old_start
&&
1278 new_end
>= (old_start
+ PAGE_SIZE
)) {
1279 set_bit(old_start
>> 22,
1280 sparc64_valid_addr_bitmap
);
1284 reserve_bootmem(old_start
, PAGE_SIZE
, BOOTMEM_DEFAULT
);
1287 old_start
+= PAGE_SIZE
;
1292 int __init
page_in_phys_avail(unsigned long paddr
)
1298 for (i
= 0; i
< pavail_rescan_ents
; i
++) {
1299 unsigned long start
, end
;
1301 start
= pavail_rescan
[i
].phys_addr
;
1302 end
= start
+ pavail_rescan
[i
].reg_size
;
1304 if (paddr
>= start
&& paddr
< end
)
1307 if (paddr
>= kern_base
&& paddr
< (kern_base
+ kern_size
))
1309 #ifdef CONFIG_BLK_DEV_INITRD
1310 if (paddr
>= __pa(initrd_start
) &&
1311 paddr
< __pa(PAGE_ALIGN(initrd_end
)))
1318 void __init
mem_init(void)
1320 unsigned long codepages
, datapages
, initpages
;
1321 unsigned long addr
, last
;
1324 i
= last_valid_pfn
>> ((22 - PAGE_SHIFT
) + 6);
1326 sparc64_valid_addr_bitmap
= (unsigned long *) alloc_bootmem(i
<< 3);
1327 if (sparc64_valid_addr_bitmap
== NULL
) {
1328 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1331 memset(sparc64_valid_addr_bitmap
, 0, i
<< 3);
1333 addr
= PAGE_OFFSET
+ kern_base
;
1334 last
= PAGE_ALIGN(kern_size
) + addr
;
1335 while (addr
< last
) {
1336 set_bit(__pa(addr
) >> 22, sparc64_valid_addr_bitmap
);
1342 high_memory
= __va(last_valid_pfn
<< PAGE_SHIFT
);
1344 /* We subtract one to account for the mem_map_zero page
1347 totalram_pages
= num_physpages
= free_all_bootmem() - 1;
1350 * Set up the zero page, mark it reserved, so that page count
1351 * is not manipulated when freeing the page from user ptes.
1353 mem_map_zero
= alloc_pages(GFP_KERNEL
|__GFP_ZERO
, 0);
1354 if (mem_map_zero
== NULL
) {
1355 prom_printf("paging_init: Cannot alloc zero page.\n");
1358 SetPageReserved(mem_map_zero
);
1360 codepages
= (((unsigned long) _etext
) - ((unsigned long) _start
));
1361 codepages
= PAGE_ALIGN(codepages
) >> PAGE_SHIFT
;
1362 datapages
= (((unsigned long) _edata
) - ((unsigned long) _etext
));
1363 datapages
= PAGE_ALIGN(datapages
) >> PAGE_SHIFT
;
1364 initpages
= (((unsigned long) __init_end
) - ((unsigned long) __init_begin
));
1365 initpages
= PAGE_ALIGN(initpages
) >> PAGE_SHIFT
;
1367 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1368 nr_free_pages() << (PAGE_SHIFT
-10),
1369 codepages
<< (PAGE_SHIFT
-10),
1370 datapages
<< (PAGE_SHIFT
-10),
1371 initpages
<< (PAGE_SHIFT
-10),
1372 PAGE_OFFSET
, (last_valid_pfn
<< PAGE_SHIFT
));
1374 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
1375 cheetah_ecache_flush_init();
1378 void free_initmem(void)
1380 unsigned long addr
, initend
;
1383 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1385 addr
= PAGE_ALIGN((unsigned long)(__init_begin
));
1386 initend
= (unsigned long)(__init_end
) & PAGE_MASK
;
1387 for (; addr
< initend
; addr
+= PAGE_SIZE
) {
1392 ((unsigned long) __va(kern_base
)) -
1393 ((unsigned long) KERNBASE
));
1394 memset((void *)addr
, POISON_FREE_INITMEM
, PAGE_SIZE
);
1395 p
= virt_to_page(page
);
1397 ClearPageReserved(p
);
1405 #ifdef CONFIG_BLK_DEV_INITRD
1406 void free_initrd_mem(unsigned long start
, unsigned long end
)
1409 printk ("Freeing initrd memory: %ldk freed\n", (end
- start
) >> 10);
1410 for (; start
< end
; start
+= PAGE_SIZE
) {
1411 struct page
*p
= virt_to_page(start
);
1413 ClearPageReserved(p
);
1422 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1423 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1424 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1425 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1426 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1427 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1429 pgprot_t PAGE_KERNEL __read_mostly
;
1430 EXPORT_SYMBOL(PAGE_KERNEL
);
1432 pgprot_t PAGE_KERNEL_LOCKED __read_mostly
;
1433 pgprot_t PAGE_COPY __read_mostly
;
1435 pgprot_t PAGE_SHARED __read_mostly
;
1436 EXPORT_SYMBOL(PAGE_SHARED
);
1438 pgprot_t PAGE_EXEC __read_mostly
;
1439 unsigned long pg_iobits __read_mostly
;
1441 unsigned long _PAGE_IE __read_mostly
;
1442 EXPORT_SYMBOL(_PAGE_IE
);
1444 unsigned long _PAGE_E __read_mostly
;
1445 EXPORT_SYMBOL(_PAGE_E
);
1447 unsigned long _PAGE_CACHE __read_mostly
;
1448 EXPORT_SYMBOL(_PAGE_CACHE
);
1450 #ifdef CONFIG_SPARSEMEM_VMEMMAP
1452 #define VMEMMAP_CHUNK_SHIFT 22
1453 #define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
1454 #define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
1455 #define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
1457 #define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
1458 sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
1459 unsigned long vmemmap_table
[VMEMMAP_SIZE
];
1461 int __meminit
vmemmap_populate(struct page
*start
, unsigned long nr
, int node
)
1463 unsigned long vstart
= (unsigned long) start
;
1464 unsigned long vend
= (unsigned long) (start
+ nr
);
1465 unsigned long phys_start
= (vstart
- VMEMMAP_BASE
);
1466 unsigned long phys_end
= (vend
- VMEMMAP_BASE
);
1467 unsigned long addr
= phys_start
& VMEMMAP_CHUNK_MASK
;
1468 unsigned long end
= VMEMMAP_ALIGN(phys_end
);
1469 unsigned long pte_base
;
1471 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
1472 _PAGE_CP_4U
| _PAGE_CV_4U
|
1473 _PAGE_P_4U
| _PAGE_W_4U
);
1474 if (tlb_type
== hypervisor
)
1475 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
1476 _PAGE_CP_4V
| _PAGE_CV_4V
|
1477 _PAGE_P_4V
| _PAGE_W_4V
);
1479 for (; addr
< end
; addr
+= VMEMMAP_CHUNK
) {
1480 unsigned long *vmem_pp
=
1481 vmemmap_table
+ (addr
>> VMEMMAP_CHUNK_SHIFT
);
1484 if (!(*vmem_pp
& _PAGE_VALID
)) {
1485 block
= vmemmap_alloc_block(1UL << 22, node
);
1489 *vmem_pp
= pte_base
| __pa(block
);
1491 printk(KERN_INFO
"[%p-%p] page_structs=%lu "
1492 "node=%d entry=%lu/%lu\n", start
, block
, nr
,
1494 addr
>> VMEMMAP_CHUNK_SHIFT
,
1495 VMEMMAP_SIZE
>> VMEMMAP_CHUNK_SHIFT
);
1500 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
1502 static void prot_init_common(unsigned long page_none
,
1503 unsigned long page_shared
,
1504 unsigned long page_copy
,
1505 unsigned long page_readonly
,
1506 unsigned long page_exec_bit
)
1508 PAGE_COPY
= __pgprot(page_copy
);
1509 PAGE_SHARED
= __pgprot(page_shared
);
1511 protection_map
[0x0] = __pgprot(page_none
);
1512 protection_map
[0x1] = __pgprot(page_readonly
& ~page_exec_bit
);
1513 protection_map
[0x2] = __pgprot(page_copy
& ~page_exec_bit
);
1514 protection_map
[0x3] = __pgprot(page_copy
& ~page_exec_bit
);
1515 protection_map
[0x4] = __pgprot(page_readonly
);
1516 protection_map
[0x5] = __pgprot(page_readonly
);
1517 protection_map
[0x6] = __pgprot(page_copy
);
1518 protection_map
[0x7] = __pgprot(page_copy
);
1519 protection_map
[0x8] = __pgprot(page_none
);
1520 protection_map
[0x9] = __pgprot(page_readonly
& ~page_exec_bit
);
1521 protection_map
[0xa] = __pgprot(page_shared
& ~page_exec_bit
);
1522 protection_map
[0xb] = __pgprot(page_shared
& ~page_exec_bit
);
1523 protection_map
[0xc] = __pgprot(page_readonly
);
1524 protection_map
[0xd] = __pgprot(page_readonly
);
1525 protection_map
[0xe] = __pgprot(page_shared
);
1526 protection_map
[0xf] = __pgprot(page_shared
);
1529 static void __init
sun4u_pgprot_init(void)
1531 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
1532 unsigned long page_exec_bit
;
1534 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
1535 _PAGE_CACHE_4U
| _PAGE_P_4U
|
1536 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
1538 PAGE_KERNEL_LOCKED
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
1539 _PAGE_CACHE_4U
| _PAGE_P_4U
|
1540 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
1541 _PAGE_EXEC_4U
| _PAGE_L_4U
);
1542 PAGE_EXEC
= __pgprot(_PAGE_EXEC_4U
);
1544 _PAGE_IE
= _PAGE_IE_4U
;
1545 _PAGE_E
= _PAGE_E_4U
;
1546 _PAGE_CACHE
= _PAGE_CACHE_4U
;
1548 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| __DIRTY_BITS_4U
|
1549 __ACCESS_BITS_4U
| _PAGE_E_4U
);
1551 #ifdef CONFIG_DEBUG_PAGEALLOC
1552 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZBITS_4U
) ^
1555 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4U
) ^
1558 kern_linear_pte_xor
[0] |= (_PAGE_CP_4U
| _PAGE_CV_4U
|
1559 _PAGE_P_4U
| _PAGE_W_4U
);
1561 /* XXX Should use 256MB on Panther. XXX */
1562 kern_linear_pte_xor
[1] = kern_linear_pte_xor
[0];
1564 _PAGE_SZBITS
= _PAGE_SZBITS_4U
;
1565 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ4MB_4U
| _PAGE_SZ512K_4U
|
1566 _PAGE_SZ64K_4U
| _PAGE_SZ8K_4U
|
1567 _PAGE_SZ32MB_4U
| _PAGE_SZ256MB_4U
);
1570 page_none
= _PAGE_PRESENT_4U
| _PAGE_ACCESSED_4U
| _PAGE_CACHE_4U
;
1571 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
1572 __ACCESS_BITS_4U
| _PAGE_WRITE_4U
| _PAGE_EXEC_4U
);
1573 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
1574 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
1575 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
1576 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
1578 page_exec_bit
= _PAGE_EXEC_4U
;
1580 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
1584 static void __init
sun4v_pgprot_init(void)
1586 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
1587 unsigned long page_exec_bit
;
1589 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4V
| _PAGE_VALID
|
1590 _PAGE_CACHE_4V
| _PAGE_P_4V
|
1591 __ACCESS_BITS_4V
| __DIRTY_BITS_4V
|
1593 PAGE_KERNEL_LOCKED
= PAGE_KERNEL
;
1594 PAGE_EXEC
= __pgprot(_PAGE_EXEC_4V
);
1596 _PAGE_IE
= _PAGE_IE_4V
;
1597 _PAGE_E
= _PAGE_E_4V
;
1598 _PAGE_CACHE
= _PAGE_CACHE_4V
;
1600 #ifdef CONFIG_DEBUG_PAGEALLOC
1601 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZBITS_4V
) ^
1604 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4V
) ^
1607 kern_linear_pte_xor
[0] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
1608 _PAGE_P_4V
| _PAGE_W_4V
);
1610 #ifdef CONFIG_DEBUG_PAGEALLOC
1611 kern_linear_pte_xor
[1] = (_PAGE_VALID
| _PAGE_SZBITS_4V
) ^
1614 kern_linear_pte_xor
[1] = (_PAGE_VALID
| _PAGE_SZ256MB_4V
) ^
1617 kern_linear_pte_xor
[1] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
1618 _PAGE_P_4V
| _PAGE_W_4V
);
1620 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| __DIRTY_BITS_4V
|
1621 __ACCESS_BITS_4V
| _PAGE_E_4V
);
1623 _PAGE_SZBITS
= _PAGE_SZBITS_4V
;
1624 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ16GB_4V
| _PAGE_SZ2GB_4V
|
1625 _PAGE_SZ256MB_4V
| _PAGE_SZ32MB_4V
|
1626 _PAGE_SZ4MB_4V
| _PAGE_SZ512K_4V
|
1627 _PAGE_SZ64K_4V
| _PAGE_SZ8K_4V
);
1629 page_none
= _PAGE_PRESENT_4V
| _PAGE_ACCESSED_4V
| _PAGE_CACHE_4V
;
1630 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
1631 __ACCESS_BITS_4V
| _PAGE_WRITE_4V
| _PAGE_EXEC_4V
);
1632 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
1633 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
1634 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
1635 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
1637 page_exec_bit
= _PAGE_EXEC_4V
;
1639 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
1643 unsigned long pte_sz_bits(unsigned long sz
)
1645 if (tlb_type
== hypervisor
) {
1649 return _PAGE_SZ8K_4V
;
1651 return _PAGE_SZ64K_4V
;
1653 return _PAGE_SZ512K_4V
;
1654 case 4 * 1024 * 1024:
1655 return _PAGE_SZ4MB_4V
;
1661 return _PAGE_SZ8K_4U
;
1663 return _PAGE_SZ64K_4U
;
1665 return _PAGE_SZ512K_4U
;
1666 case 4 * 1024 * 1024:
1667 return _PAGE_SZ4MB_4U
;
1672 pte_t
mk_pte_io(unsigned long page
, pgprot_t prot
, int space
, unsigned long page_size
)
1676 pte_val(pte
) = page
| pgprot_val(pgprot_noncached(prot
));
1677 pte_val(pte
) |= (((unsigned long)space
) << 32);
1678 pte_val(pte
) |= pte_sz_bits(page_size
);
1683 static unsigned long kern_large_tte(unsigned long paddr
)
1687 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
1688 _PAGE_CP_4U
| _PAGE_CV_4U
| _PAGE_P_4U
|
1689 _PAGE_EXEC_4U
| _PAGE_L_4U
| _PAGE_W_4U
);
1690 if (tlb_type
== hypervisor
)
1691 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
1692 _PAGE_CP_4V
| _PAGE_CV_4V
| _PAGE_P_4V
|
1693 _PAGE_EXEC_4V
| _PAGE_W_4V
);
1698 /* If not locked, zap it. */
1699 void __flush_tlb_all(void)
1701 unsigned long pstate
;
1704 __asm__
__volatile__("flushw\n\t"
1705 "rdpr %%pstate, %0\n\t"
1706 "wrpr %0, %1, %%pstate"
1709 if (tlb_type
== hypervisor
) {
1710 sun4v_mmu_demap_all();
1711 } else if (tlb_type
== spitfire
) {
1712 for (i
= 0; i
< 64; i
++) {
1713 /* Spitfire Errata #32 workaround */
1714 /* NOTE: Always runs on spitfire, so no
1715 * cheetah+ page size encodings.
1717 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
1721 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
1723 if (!(spitfire_get_dtlb_data(i
) & _PAGE_L_4U
)) {
1724 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
1727 : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
1728 spitfire_put_dtlb_data(i
, 0x0UL
);
1731 /* Spitfire Errata #32 workaround */
1732 /* NOTE: Always runs on spitfire, so no
1733 * cheetah+ page size encodings.
1735 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
1739 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
1741 if (!(spitfire_get_itlb_data(i
) & _PAGE_L_4U
)) {
1742 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
1745 : "r" (TLB_TAG_ACCESS
), "i" (ASI_IMMU
));
1746 spitfire_put_itlb_data(i
, 0x0UL
);
1749 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1750 cheetah_flush_dtlb_all();
1751 cheetah_flush_itlb_all();
1753 __asm__
__volatile__("wrpr %0, 0, %%pstate"
1757 #ifdef CONFIG_MEMORY_HOTPLUG
1759 void online_page(struct page
*page
)
1761 ClearPageReserved(page
);
1762 init_page_count(page
);
1768 #endif /* CONFIG_MEMORY_HOTPLUG */