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Linux 2.6.26-rc5
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / spi / spi_imx.c
blobc730d05bfeb68b8db4cc2f3943e3c199821d1d97
1 /*
2 * drivers/spi/spi_imx.c
3 *
4 * Copyright (C) 2006 SWAPP
5 * Andrea Paterniani <a.paterniani@swapp-eng.it>
6 *
7 * Initial version inspired by:
8 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/device.h>
24 #include <linux/ioport.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/spi/spi.h>
30 #include <linux/workqueue.h>
31 #include <linux/delay.h>
32
33 #include <asm/io.h>
34 #include <asm/irq.h>
35 #include <asm/hardware.h>
36 #include <asm/delay.h>
37
38 #include <asm/arch/hardware.h>
39 #include <asm/arch/imx-dma.h>
40 #include <asm/arch/spi_imx.h>
41
42 /*-------------------------------------------------------------------------*/
43 /* SPI Registers offsets from peripheral base address */
44 #define SPI_RXDATA (0x00)
45 #define SPI_TXDATA (0x04)
46 #define SPI_CONTROL (0x08)
47 #define SPI_INT_STATUS (0x0C)
48 #define SPI_TEST (0x10)
49 #define SPI_PERIOD (0x14)
50 #define SPI_DMA (0x18)
51 #define SPI_RESET (0x1C)
52
53 /* SPI Control Register Bit Fields & Masks */
54 #define SPI_CONTROL_BITCOUNT_MASK (0xF) /* Bit Count Mask */
55 #define SPI_CONTROL_BITCOUNT(n) (((n) - 1) & SPI_CONTROL_BITCOUNT_MASK)
56 #define SPI_CONTROL_POL (0x1 << 4) /* Clock Polarity Mask */
57 #define SPI_CONTROL_POL_ACT_HIGH (0x0 << 4) /* Active high pol. (0=idle) */
58 #define SPI_CONTROL_POL_ACT_LOW (0x1 << 4) /* Active low pol. (1=idle) */
59 #define SPI_CONTROL_PHA (0x1 << 5) /* Clock Phase Mask */
60 #define SPI_CONTROL_PHA_0 (0x0 << 5) /* Clock Phase 0 */
61 #define SPI_CONTROL_PHA_1 (0x1 << 5) /* Clock Phase 1 */
62 #define SPI_CONTROL_SSCTL (0x1 << 6) /* /SS Waveform Select Mask */
63 #define SPI_CONTROL_SSCTL_0 (0x0 << 6) /* Master: /SS stays low between SPI burst
64 Slave: RXFIFO advanced by BIT_COUNT */
65 #define SPI_CONTROL_SSCTL_1 (0x1 << 6) /* Master: /SS insert pulse between SPI burst
66 Slave: RXFIFO advanced by /SS rising edge */
67 #define SPI_CONTROL_SSPOL (0x1 << 7) /* /SS Polarity Select Mask */
68 #define SPI_CONTROL_SSPOL_ACT_LOW (0x0 << 7) /* /SS Active low */
69 #define SPI_CONTROL_SSPOL_ACT_HIGH (0x1 << 7) /* /SS Active high */
70 #define SPI_CONTROL_XCH (0x1 << 8) /* Exchange */
71 #define SPI_CONTROL_SPIEN (0x1 << 9) /* SPI Module Enable */
72 #define SPI_CONTROL_MODE (0x1 << 10) /* SPI Mode Select Mask */
73 #define SPI_CONTROL_MODE_SLAVE (0x0 << 10) /* SPI Mode Slave */
74 #define SPI_CONTROL_MODE_MASTER (0x1 << 10) /* SPI Mode Master */
75 #define SPI_CONTROL_DRCTL (0x3 << 11) /* /SPI_RDY Control Mask */
76 #define SPI_CONTROL_DRCTL_0 (0x0 << 11) /* Ignore /SPI_RDY */
77 #define SPI_CONTROL_DRCTL_1 (0x1 << 11) /* /SPI_RDY falling edge triggers input */
78 #define SPI_CONTROL_DRCTL_2 (0x2 << 11) /* /SPI_RDY active low level triggers input */
79 #define SPI_CONTROL_DATARATE (0x7 << 13) /* Data Rate Mask */
80 #define SPI_PERCLK2_DIV_MIN (0) /* PERCLK2:4 */
81 #define SPI_PERCLK2_DIV_MAX (7) /* PERCLK2:512 */
82 #define SPI_CONTROL_DATARATE_MIN (SPI_PERCLK2_DIV_MAX << 13)
83 #define SPI_CONTROL_DATARATE_MAX (SPI_PERCLK2_DIV_MIN << 13)
84 #define SPI_CONTROL_DATARATE_BAD (SPI_CONTROL_DATARATE_MIN + 1)
85
86 /* SPI Interrupt/Status Register Bit Fields & Masks */
87 #define SPI_STATUS_TE (0x1 << 0) /* TXFIFO Empty Status */
88 #define SPI_STATUS_TH (0x1 << 1) /* TXFIFO Half Status */
89 #define SPI_STATUS_TF (0x1 << 2) /* TXFIFO Full Status */
90 #define SPI_STATUS_RR (0x1 << 3) /* RXFIFO Data Ready Status */
91 #define SPI_STATUS_RH (0x1 << 4) /* RXFIFO Half Status */
92 #define SPI_STATUS_RF (0x1 << 5) /* RXFIFO Full Status */
93 #define SPI_STATUS_RO (0x1 << 6) /* RXFIFO Overflow */
94 #define SPI_STATUS_BO (0x1 << 7) /* Bit Count Overflow */
95 #define SPI_STATUS (0xFF) /* SPI Status Mask */
96 #define SPI_INTEN_TE (0x1 << 8) /* TXFIFO Empty Interrupt Enable */
97 #define SPI_INTEN_TH (0x1 << 9) /* TXFIFO Half Interrupt Enable */
98 #define SPI_INTEN_TF (0x1 << 10) /* TXFIFO Full Interrupt Enable */
99 #define SPI_INTEN_RE (0x1 << 11) /* RXFIFO Data Ready Interrupt Enable */
100 #define SPI_INTEN_RH (0x1 << 12) /* RXFIFO Half Interrupt Enable */
101 #define SPI_INTEN_RF (0x1 << 13) /* RXFIFO Full Interrupt Enable */
102 #define SPI_INTEN_RO (0x1 << 14) /* RXFIFO Overflow Interrupt Enable */
103 #define SPI_INTEN_BO (0x1 << 15) /* Bit Count Overflow Interrupt Enable */
104 #define SPI_INTEN (0xFF << 8) /* SPI Interrupt Enable Mask */
105
106 /* SPI Test Register Bit Fields & Masks */
107 #define SPI_TEST_TXCNT (0xF << 0) /* TXFIFO Counter */
108 #define SPI_TEST_RXCNT_LSB (4) /* RXFIFO Counter LSB */
109 #define SPI_TEST_RXCNT (0xF << 4) /* RXFIFO Counter */
110 #define SPI_TEST_SSTATUS (0xF << 8) /* State Machine Status */
111 #define SPI_TEST_LBC (0x1 << 14) /* Loop Back Control */
112
113 /* SPI Period Register Bit Fields & Masks */
114 #define SPI_PERIOD_WAIT (0x7FFF << 0) /* Wait Between Transactions */
115 #define SPI_PERIOD_MAX_WAIT (0x7FFF) /* Max Wait Between
116 Transactions */
117 #define SPI_PERIOD_CSRC (0x1 << 15) /* Period Clock Source Mask */
118 #define SPI_PERIOD_CSRC_BCLK (0x0 << 15) /* Period Clock Source is
119 Bit Clock */
120 #define SPI_PERIOD_CSRC_32768 (0x1 << 15) /* Period Clock Source is
121 32.768 KHz Clock */
122
123 /* SPI DMA Register Bit Fields & Masks */
124 #define SPI_DMA_RHDMA (0x1 << 4) /* RXFIFO Half Status */
125 #define SPI_DMA_RFDMA (0x1 << 5) /* RXFIFO Full Status */
126 #define SPI_DMA_TEDMA (0x1 << 6) /* TXFIFO Empty Status */
127 #define SPI_DMA_THDMA (0x1 << 7) /* TXFIFO Half Status */
128 #define SPI_DMA_RHDEN (0x1 << 12) /* RXFIFO Half DMA Request Enable */
129 #define SPI_DMA_RFDEN (0x1 << 13) /* RXFIFO Full DMA Request Enable */
130 #define SPI_DMA_TEDEN (0x1 << 14) /* TXFIFO Empty DMA Request Enable */
131 #define SPI_DMA_THDEN (0x1 << 15) /* TXFIFO Half DMA Request Enable */
132
133 /* SPI Soft Reset Register Bit Fields & Masks */
134 #define SPI_RESET_START (0x1) /* Start */
135
136 /* Default SPI configuration values */
137 #define SPI_DEFAULT_CONTROL \
138 ( \
139 SPI_CONTROL_BITCOUNT(16) | \
140 SPI_CONTROL_POL_ACT_HIGH | \
141 SPI_CONTROL_PHA_0 | \
142 SPI_CONTROL_SPIEN | \
143 SPI_CONTROL_SSCTL_1 | \
144 SPI_CONTROL_MODE_MASTER | \
145 SPI_CONTROL_DRCTL_0 | \
146 SPI_CONTROL_DATARATE_MIN \
147 )
148 #define SPI_DEFAULT_ENABLE_LOOPBACK (0)
149 #define SPI_DEFAULT_ENABLE_DMA (0)
150 #define SPI_DEFAULT_PERIOD_WAIT (8)
151 /*-------------------------------------------------------------------------*/
152
153
154 /*-------------------------------------------------------------------------*/
155 /* TX/RX SPI FIFO size */
156 #define SPI_FIFO_DEPTH (8)
157 #define SPI_FIFO_BYTE_WIDTH (2)
158 #define SPI_FIFO_OVERFLOW_MARGIN (2)
159
160 /* DMA burst length for half full/empty request trigger */
161 #define SPI_DMA_BLR (SPI_FIFO_DEPTH * SPI_FIFO_BYTE_WIDTH / 2)
162
163 /* Dummy char output to achieve reads.
164 Choosing something different from all zeroes may help pattern recogition
165 for oscilloscope analysis, but may break some drivers. */
166 #define SPI_DUMMY_u8 0
167 #define SPI_DUMMY_u16 ((SPI_DUMMY_u8 << 8) | SPI_DUMMY_u8)
168 #define SPI_DUMMY_u32 ((SPI_DUMMY_u16 << 16) | SPI_DUMMY_u16)
169
170 /**
171 * Macro to change a u32 field:
172 * @r : register to edit
173 * @m : bit mask
174 * @v : new value for the field correctly bit-alligned
175 */
176 #define u32_EDIT(r, m, v) r = (r & ~(m)) | (v)
177
178 /* Message state */
179 #define START_STATE ((void*)0)
180 #define RUNNING_STATE ((void*)1)
181 #define DONE_STATE ((void*)2)
182 #define ERROR_STATE ((void*)-1)
183
184 /* Queue state */
185 #define QUEUE_RUNNING (0)
186 #define QUEUE_STOPPED (1)
187
188 #define IS_DMA_ALIGNED(x) (((u32)(x) & 0x03) == 0)
189 /*-------------------------------------------------------------------------*/
190
191
192 /*-------------------------------------------------------------------------*/
193 /* Driver data structs */
194
195 /* Context */
196 struct driver_data {
197 /* Driver model hookup */
198 struct platform_device *pdev;
199
200 /* SPI framework hookup */
201 struct spi_master *master;
202
203 /* IMX hookup */
204 struct spi_imx_master *master_info;
205
206 /* Memory resources and SPI regs virtual address */
207 struct resource *ioarea;
208 void __iomem *regs;
209
210 /* SPI RX_DATA physical address */
211 dma_addr_t rd_data_phys;
212
213 /* Driver message queue */
214 struct workqueue_struct *workqueue;
215 struct work_struct work;
216 spinlock_t lock;
217 struct list_head queue;
218 int busy;
219 int run;
220
221 /* Message Transfer pump */
222 struct tasklet_struct pump_transfers;
223
224 /* Current message, transfer and state */
225 struct spi_message *cur_msg;
226 struct spi_transfer *cur_transfer;
227 struct chip_data *cur_chip;
228
229 /* Rd / Wr buffers pointers */
230 size_t len;
231 void *tx;
232 void *tx_end;
233 void *rx;
234 void *rx_end;
235
236 u8 rd_only;
237 u8 n_bytes;
238 int cs_change;
239
240 /* Function pointers */
241 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
242 void (*cs_control)(u32 command);
243
244 /* DMA setup */
245 int rx_channel;
246 int tx_channel;
247 dma_addr_t rx_dma;
248 dma_addr_t tx_dma;
249 int rx_dma_needs_unmap;
250 int tx_dma_needs_unmap;
251 size_t tx_map_len;
252 u32 dummy_dma_buf ____cacheline_aligned;
253 };
254
255 /* Runtime state */
256 struct chip_data {
257 u32 control;
258 u32 period;
259 u32 test;
260
261 u8 enable_dma:1;
262 u8 bits_per_word;
263 u8 n_bytes;
264 u32 max_speed_hz;
265
266 void (*cs_control)(u32 command);
267 };
268 /*-------------------------------------------------------------------------*/
269
270
271 static void pump_messages(struct work_struct *work);
272
273 static void flush(struct driver_data *drv_data)
274 {
275 void __iomem *regs = drv_data->regs;
276 u32 control;
277
278 dev_dbg(&drv_data->pdev->dev, "flush\n");
279
280 /* Wait for end of transaction */
281 do {
282 control = readl(regs + SPI_CONTROL);
283 } while (control & SPI_CONTROL_XCH);
284
285 /* Release chip select if requested, transfer delays are
286 handled in pump_transfers */
287 if (drv_data->cs_change)
288 drv_data->cs_control(SPI_CS_DEASSERT);
289
290 /* Disable SPI to flush FIFOs */
291 writel(control & ~SPI_CONTROL_SPIEN, regs + SPI_CONTROL);
292 writel(control, regs + SPI_CONTROL);
293 }
294
295 static void restore_state(struct driver_data *drv_data)
296 {
297 void __iomem *regs = drv_data->regs;
298 struct chip_data *chip = drv_data->cur_chip;
299
300 /* Load chip registers */
301 dev_dbg(&drv_data->pdev->dev,
302 "restore_state\n"
303 " test = 0x%08X\n"
304 " control = 0x%08X\n",
305 chip->test,
306 chip->control);
307 writel(chip->test, regs + SPI_TEST);
308 writel(chip->period, regs + SPI_PERIOD);
309 writel(0, regs + SPI_INT_STATUS);
310 writel(chip->control, regs + SPI_CONTROL);
311 }
312
313 static void null_cs_control(u32 command)
314 {
315 }
316
317 static inline u32 data_to_write(struct driver_data *drv_data)
318 {
319 return ((u32)(drv_data->tx_end - drv_data->tx)) / drv_data->n_bytes;
320 }
321
322 static inline u32 data_to_read(struct driver_data *drv_data)
323 {
324 return ((u32)(drv_data->rx_end - drv_data->rx)) / drv_data->n_bytes;
325 }
326
327 static int write(struct driver_data *drv_data)
328 {
329 void __iomem *regs = drv_data->regs;
330 void *tx = drv_data->tx;
331 void *tx_end = drv_data->tx_end;
332 u8 n_bytes = drv_data->n_bytes;
333 u32 remaining_writes;
334 u32 fifo_avail_space;
335 u32 n;
336 u16 d;
337
338 /* Compute how many fifo writes to do */
339 remaining_writes = (u32)(tx_end - tx) / n_bytes;
340 fifo_avail_space = SPI_FIFO_DEPTH -
341 (readl(regs + SPI_TEST) & SPI_TEST_TXCNT);
342 if (drv_data->rx && (fifo_avail_space > SPI_FIFO_OVERFLOW_MARGIN))
343 /* Fix misunderstood receive overflow */
344 fifo_avail_space -= SPI_FIFO_OVERFLOW_MARGIN;
345 n = min(remaining_writes, fifo_avail_space);
346
347 dev_dbg(&drv_data->pdev->dev,
348 "write type %s\n"
349 " remaining writes = %d\n"
350 " fifo avail space = %d\n"
351 " fifo writes = %d\n",
352 (n_bytes == 1) ? "u8" : "u16",
353 remaining_writes,
354 fifo_avail_space,
355 n);
356
357 if (n > 0) {
358 /* Fill SPI TXFIFO */
359 if (drv_data->rd_only) {
360 tx += n * n_bytes;
361 while (n--)
362 writel(SPI_DUMMY_u16, regs + SPI_TXDATA);
363 } else {
364 if (n_bytes == 1) {
365 while (n--) {
366 d = *(u8*)tx;
367 writel(d, regs + SPI_TXDATA);
368 tx += 1;
369 }
370 } else {
371 while (n--) {
372 d = *(u16*)tx;
373 writel(d, regs + SPI_TXDATA);
374 tx += 2;
375 }
376 }
377 }
378
379 /* Trigger transfer */
380 writel(readl(regs + SPI_CONTROL) | SPI_CONTROL_XCH,
381 regs + SPI_CONTROL);
382
383 /* Update tx pointer */
384 drv_data->tx = tx;
385 }
386
387 return (tx >= tx_end);
388 }
389
390 static int read(struct driver_data *drv_data)
391 {
392 void __iomem *regs = drv_data->regs;
393 void *rx = drv_data->rx;
394 void *rx_end = drv_data->rx_end;
395 u8 n_bytes = drv_data->n_bytes;
396 u32 remaining_reads;
397 u32 fifo_rxcnt;
398 u32 n;
399 u16 d;
400
401 /* Compute how many fifo reads to do */
402 remaining_reads = (u32)(rx_end - rx) / n_bytes;
403 fifo_rxcnt = (readl(regs + SPI_TEST) & SPI_TEST_RXCNT) >>
404 SPI_TEST_RXCNT_LSB;
405 n = min(remaining_reads, fifo_rxcnt);
406
407 dev_dbg(&drv_data->pdev->dev,
408 "read type %s\n"
409 " remaining reads = %d\n"
410 " fifo rx count = %d\n"
411 " fifo reads = %d\n",
412 (n_bytes == 1) ? "u8" : "u16",
413 remaining_reads,
414 fifo_rxcnt,
415 n);
416
417 if (n > 0) {
418 /* Read SPI RXFIFO */
419 if (n_bytes == 1) {
420 while (n--) {
421 d = readl(regs + SPI_RXDATA);
422 *((u8*)rx) = d;
423 rx += 1;
424 }
425 } else {
426 while (n--) {
427 d = readl(regs + SPI_RXDATA);
428 *((u16*)rx) = d;
429 rx += 2;
430 }
431 }
432
433 /* Update rx pointer */
434 drv_data->rx = rx;
435 }
436
437 return (rx >= rx_end);
438 }
439
440 static void *next_transfer(struct driver_data *drv_data)
441 {
442 struct spi_message *msg = drv_data->cur_msg;
443 struct spi_transfer *trans = drv_data->cur_transfer;
444
445 /* Move to next transfer */
446 if (trans->transfer_list.next != &msg->transfers) {
447 drv_data->cur_transfer =
448 list_entry(trans->transfer_list.next,
449 struct spi_transfer,
450 transfer_list);
451 return RUNNING_STATE;
452 }
453
454 return DONE_STATE;
455 }
456
457 static int map_dma_buffers(struct driver_data *drv_data)
458 {
459 struct spi_message *msg;
460 struct device *dev;
461 void *buf;
462
463 drv_data->rx_dma_needs_unmap = 0;
464 drv_data->tx_dma_needs_unmap = 0;
465
466 if (!drv_data->master_info->enable_dma ||
467 !drv_data->cur_chip->enable_dma)
468 return -1;
469
470 msg = drv_data->cur_msg;
471 dev = &msg->spi->dev;
472 if (msg->is_dma_mapped) {
473 if (drv_data->tx_dma)
474 /* The caller provided at least dma and cpu virtual
475 address for write; pump_transfers() will consider the
476 transfer as write only if cpu rx virtual address is
477 NULL */
478 return 0;
479
480 if (drv_data->rx_dma) {
481 /* The caller provided dma and cpu virtual address to
482 performe read only transfer -->
483 use drv_data->dummy_dma_buf for dummy writes to
484 achive reads */
485 buf = &drv_data->dummy_dma_buf;
486 drv_data->tx_map_len = sizeof(drv_data->dummy_dma_buf);
487 drv_data->tx_dma = dma_map_single(dev,
488 buf,
489 drv_data->tx_map_len,
490 DMA_TO_DEVICE);
491 if (dma_mapping_error(drv_data->tx_dma))
492 return -1;
493
494 drv_data->tx_dma_needs_unmap = 1;
495
496 /* Flags transfer as rd_only for pump_transfers() DMA
497 regs programming (should be redundant) */
498 drv_data->tx = NULL;
499
500 return 0;
501 }
502 }
503
504 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
505 return -1;
506
507 /* NULL rx means write-only transfer and no map needed
508 since rx DMA will not be used */
509 if (drv_data->rx) {
510 buf = drv_data->rx;
511 drv_data->rx_dma = dma_map_single(
512 dev,
513 buf,
514 drv_data->len,
515 DMA_FROM_DEVICE);
516 if (dma_mapping_error(drv_data->rx_dma))
517 return -1;
518 drv_data->rx_dma_needs_unmap = 1;
519 }
520
521 if (drv_data->tx == NULL) {
522 /* Read only message --> use drv_data->dummy_dma_buf for dummy
523 writes to achive reads */
524 buf = &drv_data->dummy_dma_buf;
525 drv_data->tx_map_len = sizeof(drv_data->dummy_dma_buf);
526 } else {
527 buf = drv_data->tx;
528 drv_data->tx_map_len = drv_data->len;
529 }
530 drv_data->tx_dma = dma_map_single(dev,
531 buf,
532 drv_data->tx_map_len,
533 DMA_TO_DEVICE);
534 if (dma_mapping_error(drv_data->tx_dma)) {
535 if (drv_data->rx_dma) {
536 dma_unmap_single(dev,
537 drv_data->rx_dma,
538 drv_data->len,
539 DMA_FROM_DEVICE);
540 drv_data->rx_dma_needs_unmap = 0;
541 }
542 return -1;
543 }
544 drv_data->tx_dma_needs_unmap = 1;
545
546 return 0;
547 }
548
549 static void unmap_dma_buffers(struct driver_data *drv_data)
550 {
551 struct spi_message *msg = drv_data->cur_msg;
552 struct device *dev = &msg->spi->dev;
553
554 if (drv_data->rx_dma_needs_unmap) {
555 dma_unmap_single(dev,
556 drv_data->rx_dma,
557 drv_data->len,
558 DMA_FROM_DEVICE);
559 drv_data->rx_dma_needs_unmap = 0;
560 }
561 if (drv_data->tx_dma_needs_unmap) {
562 dma_unmap_single(dev,
563 drv_data->tx_dma,
564 drv_data->tx_map_len,
565 DMA_TO_DEVICE);
566 drv_data->tx_dma_needs_unmap = 0;
567 }
568 }
569
570 /* Caller already set message->status (dma is already blocked) */
571 static void giveback(struct spi_message *message, struct driver_data *drv_data)
572 {
573 void __iomem *regs = drv_data->regs;
574
575 /* Bring SPI to sleep; restore_state() and pump_transfer()
576 will do new setup */
577 writel(0, regs + SPI_INT_STATUS);
578 writel(0, regs + SPI_DMA);
579
580 /* Unconditioned deselct */
581 drv_data->cs_control(SPI_CS_DEASSERT);
582
583 message->state = NULL;
584 if (message->complete)
585 message->complete(message->context);
586
587 drv_data->cur_msg = NULL;
588 drv_data->cur_transfer = NULL;
589 drv_data->cur_chip = NULL;
590 queue_work(drv_data->workqueue, &drv_data->work);
591 }
592
593 static void dma_err_handler(int channel, void *data, int errcode)
594 {
595 struct driver_data *drv_data = data;
596 struct spi_message *msg = drv_data->cur_msg;
597
598 dev_dbg(&drv_data->pdev->dev, "dma_err_handler\n");
599
600 /* Disable both rx and tx dma channels */
601 imx_dma_disable(drv_data->rx_channel);
602 imx_dma_disable(drv_data->tx_channel);
603 unmap_dma_buffers(drv_data);
604
605 flush(drv_data);
606
607 msg->state = ERROR_STATE;
608 tasklet_schedule(&drv_data->pump_transfers);
609 }
610
611 static void dma_tx_handler(int channel, void *data)
612 {
613 struct driver_data *drv_data = data;
614
615 dev_dbg(&drv_data->pdev->dev, "dma_tx_handler\n");
616
617 imx_dma_disable(channel);
618
619 /* Now waits for TX FIFO empty */
620 writel(SPI_INTEN_TE, drv_data->regs + SPI_INT_STATUS);
621 }
622
623 static irqreturn_t dma_transfer(struct driver_data *drv_data)
624 {
625 u32 status;
626 struct spi_message *msg = drv_data->cur_msg;
627 void __iomem *regs = drv_data->regs;
628
629 status = readl(regs + SPI_INT_STATUS);
630
631 if ((status & (SPI_INTEN_RO | SPI_STATUS_RO))
632 == (SPI_INTEN_RO | SPI_STATUS_RO)) {
633 writel(status & ~SPI_INTEN, regs + SPI_INT_STATUS);
634
635 imx_dma_disable(drv_data->tx_channel);
636 imx_dma_disable(drv_data->rx_channel);
637 unmap_dma_buffers(drv_data);
638
639 flush(drv_data);
640
641 dev_warn(&drv_data->pdev->dev,
642 "dma_transfer - fifo overun\n");
643
644 msg->state = ERROR_STATE;
645 tasklet_schedule(&drv_data->pump_transfers);
646
647 return IRQ_HANDLED;
648 }
649
650 if (status & SPI_STATUS_TE) {
651 writel(status & ~SPI_INTEN_TE, regs + SPI_INT_STATUS);
652
653 if (drv_data->rx) {
654 /* Wait end of transfer before read trailing data */
655 while (readl(regs + SPI_CONTROL) & SPI_CONTROL_XCH)
656 cpu_relax();
657
658 imx_dma_disable(drv_data->rx_channel);
659 unmap_dma_buffers(drv_data);
660
661 /* Release chip select if requested, transfer delays are
662 handled in pump_transfers() */
663 if (drv_data->cs_change)
664 drv_data->cs_control(SPI_CS_DEASSERT);
665
666 /* Calculate number of trailing data and read them */
667 dev_dbg(&drv_data->pdev->dev,
668 "dma_transfer - test = 0x%08X\n",
669 readl(regs + SPI_TEST));
670 drv_data->rx = drv_data->rx_end -
671 ((readl(regs + SPI_TEST) &
672 SPI_TEST_RXCNT) >>
673 SPI_TEST_RXCNT_LSB)*drv_data->n_bytes;
674 read(drv_data);
675 } else {
676 /* Write only transfer */
677 unmap_dma_buffers(drv_data);
678
679 flush(drv_data);
680 }
681
682 /* End of transfer, update total byte transfered */
683 msg->actual_length += drv_data->len;
684
685 /* Move to next transfer */
686 msg->state = next_transfer(drv_data);
687
688 /* Schedule transfer tasklet */
689 tasklet_schedule(&drv_data->pump_transfers);
690
691 return IRQ_HANDLED;
692 }
693
694 /* Opps problem detected */
695 return IRQ_NONE;
696 }
697
698 static irqreturn_t interrupt_wronly_transfer(struct driver_data *drv_data)
699 {
700 struct spi_message *msg = drv_data->cur_msg;
701 void __iomem *regs = drv_data->regs;
702 u32 status;
703 irqreturn_t handled = IRQ_NONE;
704
705 status = readl(regs + SPI_INT_STATUS);
706
707 if (status & SPI_INTEN_TE) {
708 /* TXFIFO Empty Interrupt on the last transfered word */
709 writel(status & ~SPI_INTEN, regs + SPI_INT_STATUS);
710 dev_dbg(&drv_data->pdev->dev,
711 "interrupt_wronly_transfer - end of tx\n");
712
713 flush(drv_data);
714
715 /* Update total byte transfered */
716 msg->actual_length += drv_data->len;
717
718 /* Move to next transfer */
719 msg->state = next_transfer(drv_data);
720
721 /* Schedule transfer tasklet */
722 tasklet_schedule(&drv_data->pump_transfers);
723
724 return IRQ_HANDLED;
725 } else {
726 while (status & SPI_STATUS_TH) {
727 dev_dbg(&drv_data->pdev->dev,
728 "interrupt_wronly_transfer - status = 0x%08X\n",
729 status);
730
731 /* Pump data */
732 if (write(drv_data)) {
733 /* End of TXFIFO writes,
734 now wait until TXFIFO is empty */
735 writel(SPI_INTEN_TE, regs + SPI_INT_STATUS);
736 return IRQ_HANDLED;
737 }
738
739 status = readl(regs + SPI_INT_STATUS);
740
741 /* We did something */
742 handled = IRQ_HANDLED;
743 }
744 }
745
746 return handled;
747 }
748
749 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
750 {
751 struct spi_message *msg = drv_data->cur_msg;
752 void __iomem *regs = drv_data->regs;
753 u32 status, control;
754 irqreturn_t handled = IRQ_NONE;
755 unsigned long limit;
756
757 status = readl(regs + SPI_INT_STATUS);
758
759 if (status & SPI_INTEN_TE) {
760 /* TXFIFO Empty Interrupt on the last transfered word */
761 writel(status & ~SPI_INTEN, regs + SPI_INT_STATUS);
762 dev_dbg(&drv_data->pdev->dev,
763 "interrupt_transfer - end of tx\n");
764
765 if (msg->state == ERROR_STATE) {
766 /* RXFIFO overrun was detected and message aborted */
767 flush(drv_data);
768 } else {
769 /* Wait for end of transaction */
770 do {
771 control = readl(regs + SPI_CONTROL);
772 } while (control & SPI_CONTROL_XCH);
773
774 /* Release chip select if requested, transfer delays are
775 handled in pump_transfers */
776 if (drv_data->cs_change)
777 drv_data->cs_control(SPI_CS_DEASSERT);
778
779 /* Read trailing bytes */
780 limit = loops_per_jiffy << 1;
781 while ((read(drv_data) == 0) && limit--);
782
783 if (limit == 0)
784 dev_err(&drv_data->pdev->dev,
785 "interrupt_transfer - "
786 "trailing byte read failed\n");
787 else
788 dev_dbg(&drv_data->pdev->dev,
789 "interrupt_transfer - end of rx\n");
790
791 /* Update total byte transfered */
792 msg->actual_length += drv_data->len;
793
794 /* Move to next transfer */
795 msg->state = next_transfer(drv_data);
796 }
797
798 /* Schedule transfer tasklet */
799 tasklet_schedule(&drv_data->pump_transfers);
800
801 return IRQ_HANDLED;
802 } else {
803 while (status & (SPI_STATUS_TH | SPI_STATUS_RO)) {
804 dev_dbg(&drv_data->pdev->dev,
805 "interrupt_transfer - status = 0x%08X\n",
806 status);
807
808 if (status & SPI_STATUS_RO) {
809 /* RXFIFO overrun, abort message end wait
810 until TXFIFO is empty */
811 writel(SPI_INTEN_TE, regs + SPI_INT_STATUS);
812
813 dev_warn(&drv_data->pdev->dev,
814 "interrupt_transfer - fifo overun\n"
815 " data not yet written = %d\n"
816 " data not yet read = %d\n",
817 data_to_write(drv_data),
818 data_to_read(drv_data));
819
820 msg->state = ERROR_STATE;
821
822 return IRQ_HANDLED;
823 }
824
825 /* Pump data */
826 read(drv_data);
827 if (write(drv_data)) {
828 /* End of TXFIFO writes,
829 now wait until TXFIFO is empty */
830 writel(SPI_INTEN_TE, regs + SPI_INT_STATUS);
831 return IRQ_HANDLED;
832 }
833
834 status = readl(regs + SPI_INT_STATUS);
835
836 /* We did something */
837 handled = IRQ_HANDLED;
838 }
839 }
840
841 return handled;
842 }
843
844 static irqreturn_t spi_int(int irq, void *dev_id)
845 {
846 struct driver_data *drv_data = (struct driver_data *)dev_id;
847
848 if (!drv_data->cur_msg) {
849 dev_err(&drv_data->pdev->dev,
850 "spi_int - bad message state\n");
851 /* Never fail */
852 return IRQ_HANDLED;
853 }
854
855 return drv_data->transfer_handler(drv_data);
856 }
857
858 static inline u32 spi_speed_hz(u32 data_rate)
859 {
860 return imx_get_perclk2() / (4 << ((data_rate) >> 13));
861 }
862
863 static u32 spi_data_rate(u32 speed_hz)
864 {
865 u32 div;
866 u32 quantized_hz = imx_get_perclk2() >> 2;
867
868 for (div = SPI_PERCLK2_DIV_MIN;
869 div <= SPI_PERCLK2_DIV_MAX;
870 div++, quantized_hz >>= 1) {
871 if (quantized_hz <= speed_hz)
872 /* Max available speed LEQ required speed */
873 return div << 13;
874 }
875 return SPI_CONTROL_DATARATE_BAD;
876 }
877
878 static void pump_transfers(unsigned long data)
879 {
880 struct driver_data *drv_data = (struct driver_data *)data;
881 struct spi_message *message;
882 struct spi_transfer *transfer, *previous;
883 struct chip_data *chip;
884 void __iomem *regs;
885 u32 tmp, control;
886
887 dev_dbg(&drv_data->pdev->dev, "pump_transfer\n");
888
889 message = drv_data->cur_msg;
890
891 /* Handle for abort */
892 if (message->state == ERROR_STATE) {
893 message->status = -EIO;
894 giveback(message, drv_data);
895 return;
896 }
897
898 /* Handle end of message */
899 if (message->state == DONE_STATE) {
900 message->status = 0;
901 giveback(message, drv_data);
902 return;
903 }
904
905 chip = drv_data->cur_chip;
906
907 /* Delay if requested at end of transfer*/
908 transfer = drv_data->cur_transfer;
909 if (message->state == RUNNING_STATE) {
910 previous = list_entry(transfer->transfer_list.prev,
911 struct spi_transfer,
912 transfer_list);
913 if (previous->delay_usecs)
914 udelay(previous->delay_usecs);
915 } else {
916 /* START_STATE */
917 message->state = RUNNING_STATE;
918 drv_data->cs_control = chip->cs_control;
919 }
920
921 transfer = drv_data->cur_transfer;
922 drv_data->tx = (void *)transfer->tx_buf;
923 drv_data->tx_end = drv_data->tx + transfer->len;
924 drv_data->rx = transfer->rx_buf;
925 drv_data->rx_end = drv_data->rx + transfer->len;
926 drv_data->rx_dma = transfer->rx_dma;
927 drv_data->tx_dma = transfer->tx_dma;
928 drv_data->len = transfer->len;
929 drv_data->cs_change = transfer->cs_change;
930 drv_data->rd_only = (drv_data->tx == NULL);
931
932 regs = drv_data->regs;
933 control = readl(regs + SPI_CONTROL);
934
935 /* Bits per word setup */
936 tmp = transfer->bits_per_word;
937 if (tmp == 0) {
938 /* Use device setup */
939 tmp = chip->bits_per_word;
940 drv_data->n_bytes = chip->n_bytes;
941 } else
942 /* Use per-transfer setup */
943 drv_data->n_bytes = (tmp <= 8) ? 1 : 2;
944 u32_EDIT(control, SPI_CONTROL_BITCOUNT_MASK, tmp - 1);
945
946 /* Speed setup (surely valid because already checked) */
947 tmp = transfer->speed_hz;
948 if (tmp == 0)
949 tmp = chip->max_speed_hz;
950 tmp = spi_data_rate(tmp);
951 u32_EDIT(control, SPI_CONTROL_DATARATE, tmp);
952
953 writel(control, regs + SPI_CONTROL);
954
955 /* Assert device chip-select */
956 drv_data->cs_control(SPI_CS_ASSERT);
957
958 /* DMA cannot read/write SPI FIFOs other than 16 bits at a time; hence
959 if bits_per_word is less or equal 8 PIO transfers are performed.
960 Moreover DMA is convinient for transfer length bigger than FIFOs
961 byte size. */
962 if ((drv_data->n_bytes == 2) &&
963 (drv_data->len > SPI_FIFO_DEPTH*SPI_FIFO_BYTE_WIDTH) &&
964 (map_dma_buffers(drv_data) == 0)) {
965 dev_dbg(&drv_data->pdev->dev,
966 "pump dma transfer\n"
967 " tx = %p\n"
968 " tx_dma = %08X\n"
969 " rx = %p\n"
970 " rx_dma = %08X\n"
971 " len = %d\n",
972 drv_data->tx,
973 (unsigned int)drv_data->tx_dma,
974 drv_data->rx,
975 (unsigned int)drv_data->rx_dma,
976 drv_data->len);
977
978 /* Ensure we have the correct interrupt handler */
979 drv_data->transfer_handler = dma_transfer;
980
981 /* Trigger transfer */
982 writel(readl(regs + SPI_CONTROL) | SPI_CONTROL_XCH,
983 regs + SPI_CONTROL);
984
985 /* Setup tx DMA */
986 if (drv_data->tx)
987 /* Linear source address */
988 CCR(drv_data->tx_channel) =
989 CCR_DMOD_FIFO |
990 CCR_SMOD_LINEAR |
991 CCR_SSIZ_32 | CCR_DSIZ_16 |
992 CCR_REN;
993 else
994 /* Read only transfer -> fixed source address for
995 dummy write to achive read */
996 CCR(drv_data->tx_channel) =
997 CCR_DMOD_FIFO |
998 CCR_SMOD_FIFO |
999 CCR_SSIZ_32 | CCR_DSIZ_16 |
1000 CCR_REN;
1001
1002 imx_dma_setup_single(
1003 drv_data->tx_channel,
1004 drv_data->tx_dma,
1005 drv_data->len,
1006 drv_data->rd_data_phys + 4,
1007 DMA_MODE_WRITE);
1008
1009 if (drv_data->rx) {
1010 /* Setup rx DMA for linear destination address */
1011 CCR(drv_data->rx_channel) =
1012 CCR_DMOD_LINEAR |
1013 CCR_SMOD_FIFO |
1014 CCR_DSIZ_32 | CCR_SSIZ_16 |
1015 CCR_REN;
1016 imx_dma_setup_single(
1017 drv_data->rx_channel,
1018 drv_data->rx_dma,
1019 drv_data->len,
1020 drv_data->rd_data_phys,
1021 DMA_MODE_READ);
1022 imx_dma_enable(drv_data->rx_channel);
1023
1024 /* Enable SPI interrupt */
1025 writel(SPI_INTEN_RO, regs + SPI_INT_STATUS);
1026
1027 /* Set SPI to request DMA service on both
1028 Rx and Tx half fifo watermark */
1029 writel(SPI_DMA_RHDEN | SPI_DMA_THDEN, regs + SPI_DMA);
1030 } else
1031 /* Write only access -> set SPI to request DMA
1032 service on Tx half fifo watermark */
1033 writel(SPI_DMA_THDEN, regs + SPI_DMA);
1034
1035 imx_dma_enable(drv_data->tx_channel);
1036 } else {
1037 dev_dbg(&drv_data->pdev->dev,
1038 "pump pio transfer\n"
1039 " tx = %p\n"
1040 " rx = %p\n"
1041 " len = %d\n",
1042 drv_data->tx,
1043 drv_data->rx,
1044 drv_data->len);
1045
1046 /* Ensure we have the correct interrupt handler */
1047 if (drv_data->rx)
1048 drv_data->transfer_handler = interrupt_transfer;
1049 else
1050 drv_data->transfer_handler = interrupt_wronly_transfer;
1051
1052 /* Enable SPI interrupt */
1053 if (drv_data->rx)
1054 writel(SPI_INTEN_TH | SPI_INTEN_RO,
1055 regs + SPI_INT_STATUS);
1056 else
1057 writel(SPI_INTEN_TH, regs + SPI_INT_STATUS);
1058 }
1059 }
1060
1061 static void pump_messages(struct work_struct *work)
1062 {
1063 struct driver_data *drv_data =
1064 container_of(work, struct driver_data, work);
1065 unsigned long flags;
1066
1067 /* Lock queue and check for queue work */
1068 spin_lock_irqsave(&drv_data->lock, flags);
1069 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1070 drv_data->busy = 0;
1071 spin_unlock_irqrestore(&drv_data->lock, flags);
1072 return;
1073 }
1074
1075 /* Make sure we are not already running a message */
1076 if (drv_data->cur_msg) {
1077 spin_unlock_irqrestore(&drv_data->lock, flags);
1078 return;
1079 }
1080
1081 /* Extract head of queue */
1082 drv_data->cur_msg = list_entry(drv_data->queue.next,
1083 struct spi_message, queue);
1084 list_del_init(&drv_data->cur_msg->queue);
1085 drv_data->busy = 1;
1086 spin_unlock_irqrestore(&drv_data->lock, flags);
1087
1088 /* Initial message state */
1089 drv_data->cur_msg->state = START_STATE;
1090 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1091 struct spi_transfer,
1092 transfer_list);
1093
1094 /* Setup the SPI using the per chip configuration */
1095 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1096 restore_state(drv_data);
1097
1098 /* Mark as busy and launch transfers */
1099 tasklet_schedule(&drv_data->pump_transfers);
1100 }
1101
1102 static int transfer(struct spi_device *spi, struct spi_message *msg)
1103 {
1104 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1105 u32 min_speed_hz, max_speed_hz, tmp;
1106 struct spi_transfer *trans;
1107 unsigned long flags;
1108
1109 msg->actual_length = 0;
1110
1111 /* Per transfer setup check */
1112 min_speed_hz = spi_speed_hz(SPI_CONTROL_DATARATE_MIN);
1113 max_speed_hz = spi->max_speed_hz;
1114 list_for_each_entry(trans, &msg->transfers, transfer_list) {
1115 tmp = trans->bits_per_word;
1116 if (tmp > 16) {
1117 dev_err(&drv_data->pdev->dev,
1118 "message rejected : "
1119 "invalid transfer bits_per_word (%d bits)\n",
1120 tmp);
1121 goto msg_rejected;
1122 }
1123 tmp = trans->speed_hz;
1124 if (tmp) {
1125 if (tmp < min_speed_hz) {
1126 dev_err(&drv_data->pdev->dev,
1127 "message rejected : "
1128 "device min speed (%d Hz) exceeds "
1129 "required transfer speed (%d Hz)\n",
1130 min_speed_hz,
1131 tmp);
1132 goto msg_rejected;
1133 } else if (tmp > max_speed_hz) {
1134 dev_err(&drv_data->pdev->dev,
1135 "message rejected : "
1136 "transfer speed (%d Hz) exceeds "
1137 "device max speed (%d Hz)\n",
1138 tmp,
1139 max_speed_hz);
1140 goto msg_rejected;
1141 }
1142 }
1143 }
1144
1145 /* Message accepted */
1146 msg->status = -EINPROGRESS;
1147 msg->state = START_STATE;
1148
1149 spin_lock_irqsave(&drv_data->lock, flags);
1150 if (drv_data->run == QUEUE_STOPPED) {
1151 spin_unlock_irqrestore(&drv_data->lock, flags);
1152 return -ESHUTDOWN;
1153 }
1154
1155 list_add_tail(&msg->queue, &drv_data->queue);
1156 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1157 queue_work(drv_data->workqueue, &drv_data->work);
1158
1159 spin_unlock_irqrestore(&drv_data->lock, flags);
1160 return 0;
1161
1162 msg_rejected:
1163 /* Message rejected and not queued */
1164 msg->status = -EINVAL;
1165 msg->state = ERROR_STATE;
1166 if (msg->complete)
1167 msg->complete(msg->context);
1168 return -EINVAL;
1169 }
1170
1171 /* the spi->mode bits understood by this driver: */
1172 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
1173
1174 /* On first setup bad values must free chip_data memory since will cause
1175 spi_new_device to fail. Bad value setup from protocol driver are simply not
1176 applied and notified to the calling driver. */
1177 static int setup(struct spi_device *spi)
1178 {
1179 struct spi_imx_chip *chip_info;
1180 struct chip_data *chip;
1181 int first_setup = 0;
1182 u32 tmp;
1183 int status = 0;
1184
1185 if (spi->mode & ~MODEBITS) {
1186 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
1187 spi->mode & ~MODEBITS);
1188 return -EINVAL;
1189 }
1190
1191 /* Get controller data */
1192 chip_info = spi->controller_data;
1193
1194 /* Get controller_state */
1195 chip = spi_get_ctldata(spi);
1196 if (chip == NULL) {
1197 first_setup = 1;
1198
1199 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1200 if (!chip) {
1201 dev_err(&spi->dev,
1202 "setup - cannot allocate controller state\n");
1203 return -ENOMEM;
1204 }
1205 chip->control = SPI_DEFAULT_CONTROL;
1206
1207 if (chip_info == NULL) {
1208 /* spi_board_info.controller_data not is supplied */
1209 chip_info = kzalloc(sizeof(struct spi_imx_chip),
1210 GFP_KERNEL);
1211 if (!chip_info) {
1212 dev_err(&spi->dev,
1213 "setup - "
1214 "cannot allocate controller data\n");
1215 status = -ENOMEM;
1216 goto err_first_setup;
1217 }
1218 /* Set controller data default value */
1219 chip_info->enable_loopback =
1220 SPI_DEFAULT_ENABLE_LOOPBACK;
1221 chip_info->enable_dma = SPI_DEFAULT_ENABLE_DMA;
1222 chip_info->ins_ss_pulse = 1;
1223 chip_info->bclk_wait = SPI_DEFAULT_PERIOD_WAIT;
1224 chip_info->cs_control = null_cs_control;
1225 }
1226 }
1227
1228 /* Now set controller state based on controller data */
1229
1230 if (first_setup) {
1231 /* SPI loopback */
1232 if (chip_info->enable_loopback)
1233 chip->test = SPI_TEST_LBC;
1234 else
1235 chip->test = 0;
1236
1237 /* SPI dma driven */
1238 chip->enable_dma = chip_info->enable_dma;
1239
1240 /* SPI /SS pulse between spi burst */
1241 if (chip_info->ins_ss_pulse)
1242 u32_EDIT(chip->control,
1243 SPI_CONTROL_SSCTL, SPI_CONTROL_SSCTL_1);
1244 else
1245 u32_EDIT(chip->control,
1246 SPI_CONTROL_SSCTL, SPI_CONTROL_SSCTL_0);
1247
1248 /* SPI bclk waits between each bits_per_word spi burst */
1249 if (chip_info->bclk_wait > SPI_PERIOD_MAX_WAIT) {
1250 dev_err(&spi->dev,
1251 "setup - "
1252 "bclk_wait exceeds max allowed (%d)\n",
1253 SPI_PERIOD_MAX_WAIT);
1254 goto err_first_setup;
1255 }
1256 chip->period = SPI_PERIOD_CSRC_BCLK |
1257 (chip_info->bclk_wait & SPI_PERIOD_WAIT);
1258 }
1259
1260 /* SPI mode */
1261 tmp = spi->mode;
1262 if (tmp & SPI_CS_HIGH) {
1263 u32_EDIT(chip->control,
1264 SPI_CONTROL_SSPOL, SPI_CONTROL_SSPOL_ACT_HIGH);
1265 }
1266 switch (tmp & SPI_MODE_3) {
1267 case SPI_MODE_0:
1268 tmp = 0;
1269 break;
1270 case SPI_MODE_1:
1271 tmp = SPI_CONTROL_PHA_1;
1272 break;
1273 case SPI_MODE_2:
1274 tmp = SPI_CONTROL_POL_ACT_LOW;
1275 break;
1276 default:
1277 /* SPI_MODE_3 */
1278 tmp = SPI_CONTROL_PHA_1 | SPI_CONTROL_POL_ACT_LOW;
1279 break;
1280 }
1281 u32_EDIT(chip->control, SPI_CONTROL_POL | SPI_CONTROL_PHA, tmp);
1282
1283 /* SPI word width */
1284 tmp = spi->bits_per_word;
1285 if (tmp == 0) {
1286 tmp = 8;
1287 spi->bits_per_word = 8;
1288 } else if (tmp > 16) {
1289 status = -EINVAL;
1290 dev_err(&spi->dev,
1291 "setup - "
1292 "invalid bits_per_word (%d)\n",
1293 tmp);
1294 if (first_setup)
1295 goto err_first_setup;
1296 else {
1297 /* Undo setup using chip as backup copy */
1298 tmp = chip->bits_per_word;
1299 spi->bits_per_word = tmp;
1300 }
1301 }
1302 chip->bits_per_word = tmp;
1303 u32_EDIT(chip->control, SPI_CONTROL_BITCOUNT_MASK, tmp - 1);
1304 chip->n_bytes = (tmp <= 8) ? 1 : 2;
1305
1306 /* SPI datarate */
1307 tmp = spi_data_rate(spi->max_speed_hz);
1308 if (tmp == SPI_CONTROL_DATARATE_BAD) {
1309 status = -EINVAL;
1310 dev_err(&spi->dev,
1311 "setup - "
1312 "HW min speed (%d Hz) exceeds required "
1313 "max speed (%d Hz)\n",
1314 spi_speed_hz(SPI_CONTROL_DATARATE_MIN),
1315 spi->max_speed_hz);
1316 if (first_setup)
1317 goto err_first_setup;
1318 else
1319 /* Undo setup using chip as backup copy */
1320 spi->max_speed_hz = chip->max_speed_hz;
1321 } else {
1322 u32_EDIT(chip->control, SPI_CONTROL_DATARATE, tmp);
1323 /* Actual rounded max_speed_hz */
1324 tmp = spi_speed_hz(tmp);
1325 spi->max_speed_hz = tmp;
1326 chip->max_speed_hz = tmp;
1327 }
1328
1329 /* SPI chip-select management */
1330 if (chip_info->cs_control)
1331 chip->cs_control = chip_info->cs_control;
1332 else
1333 chip->cs_control = null_cs_control;
1334
1335 /* Save controller_state */
1336 spi_set_ctldata(spi, chip);
1337
1338 /* Summary */
1339 dev_dbg(&spi->dev,
1340 "setup succeded\n"
1341 " loopback enable = %s\n"
1342 " dma enable = %s\n"
1343 " insert /ss pulse = %s\n"
1344 " period wait = %d\n"
1345 " mode = %d\n"
1346 " bits per word = %d\n"
1347 " min speed = %d Hz\n"
1348 " rounded max speed = %d Hz\n",
1349 chip->test & SPI_TEST_LBC ? "Yes" : "No",
1350 chip->enable_dma ? "Yes" : "No",
1351 chip->control & SPI_CONTROL_SSCTL ? "Yes" : "No",
1352 chip->period & SPI_PERIOD_WAIT,
1353 spi->mode,
1354 spi->bits_per_word,
1355 spi_speed_hz(SPI_CONTROL_DATARATE_MIN),
1356 spi->max_speed_hz);
1357 return status;
1358
1359 err_first_setup:
1360 kfree(chip);
1361 return status;
1362 }
1363
1364 static void cleanup(struct spi_device *spi)
1365 {
1366 kfree(spi_get_ctldata(spi));
1367 }
1368
1369 static int __init init_queue(struct driver_data *drv_data)
1370 {
1371 INIT_LIST_HEAD(&drv_data->queue);
1372 spin_lock_init(&drv_data->lock);
1373
1374 drv_data->run = QUEUE_STOPPED;
1375 drv_data->busy = 0;
1376
1377 tasklet_init(&drv_data->pump_transfers,
1378 pump_transfers, (unsigned long)drv_data);
1379
1380 INIT_WORK(&drv_data->work, pump_messages);
1381 drv_data->workqueue = create_singlethread_workqueue(
1382 drv_data->master->dev.parent->bus_id);
1383 if (drv_data->workqueue == NULL)
1384 return -EBUSY;
1385
1386 return 0;
1387 }
1388
1389 static int start_queue(struct driver_data *drv_data)
1390 {
1391 unsigned long flags;
1392
1393 spin_lock_irqsave(&drv_data->lock, flags);
1394
1395 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1396 spin_unlock_irqrestore(&drv_data->lock, flags);
1397 return -EBUSY;
1398 }
1399
1400 drv_data->run = QUEUE_RUNNING;
1401 drv_data->cur_msg = NULL;
1402 drv_data->cur_transfer = NULL;
1403 drv_data->cur_chip = NULL;
1404 spin_unlock_irqrestore(&drv_data->lock, flags);
1405
1406 queue_work(drv_data->workqueue, &drv_data->work);
1407
1408 return 0;
1409 }
1410
1411 static int stop_queue(struct driver_data *drv_data)
1412 {
1413 unsigned long flags;
1414 unsigned limit = 500;
1415 int status = 0;
1416
1417 spin_lock_irqsave(&drv_data->lock, flags);
1418
1419 /* This is a bit lame, but is optimized for the common execution path.
1420 * A wait_queue on the drv_data->busy could be used, but then the common
1421 * execution path (pump_messages) would be required to call wake_up or
1422 * friends on every SPI message. Do this instead */
1423 drv_data->run = QUEUE_STOPPED;
1424 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1425 spin_unlock_irqrestore(&drv_data->lock, flags);
1426 msleep(10);
1427 spin_lock_irqsave(&drv_data->lock, flags);
1428 }
1429
1430 if (!list_empty(&drv_data->queue) || drv_data->busy)
1431 status = -EBUSY;
1432
1433 spin_unlock_irqrestore(&drv_data->lock, flags);
1434
1435 return status;
1436 }
1437
1438 static int destroy_queue(struct driver_data *drv_data)
1439 {
1440 int status;
1441
1442 status = stop_queue(drv_data);
1443 if (status != 0)
1444 return status;
1445
1446 if (drv_data->workqueue)
1447 destroy_workqueue(drv_data->workqueue);
1448
1449 return 0;
1450 }
1451
1452 static int __init spi_imx_probe(struct platform_device *pdev)
1453 {
1454 struct device *dev = &pdev->dev;
1455 struct spi_imx_master *platform_info;
1456 struct spi_master *master;
1457 struct driver_data *drv_data = NULL;
1458 struct resource *res;
1459 int irq, status = 0;
1460
1461 platform_info = dev->platform_data;
1462 if (platform_info == NULL) {
1463 dev_err(&pdev->dev, "probe - no platform data supplied\n");
1464 status = -ENODEV;
1465 goto err_no_pdata;
1466 }
1467
1468 /* Allocate master with space for drv_data */
1469 master = spi_alloc_master(dev, sizeof(struct driver_data));
1470 if (!master) {
1471 dev_err(&pdev->dev, "probe - cannot alloc spi_master\n");
1472 status = -ENOMEM;
1473 goto err_no_mem;
1474 }
1475 drv_data = spi_master_get_devdata(master);
1476 drv_data->master = master;
1477 drv_data->master_info = platform_info;
1478 drv_data->pdev = pdev;
1479
1480 master->bus_num = pdev->id;
1481 master->num_chipselect = platform_info->num_chipselect;
1482 master->cleanup = cleanup;
1483 master->setup = setup;
1484 master->transfer = transfer;
1485
1486 drv_data->dummy_dma_buf = SPI_DUMMY_u32;
1487
1488 /* Find and map resources */
1489 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1490 if (!res) {
1491 dev_err(&pdev->dev, "probe - MEM resources not defined\n");
1492 status = -ENODEV;
1493 goto err_no_iores;
1494 }
1495 drv_data->ioarea = request_mem_region(res->start,
1496 res->end - res->start + 1,
1497 pdev->name);
1498 if (drv_data->ioarea == NULL) {
1499 dev_err(&pdev->dev, "probe - cannot reserve region\n");
1500 status = -ENXIO;
1501 goto err_no_iores;
1502 }
1503 drv_data->regs = ioremap(res->start, res->end - res->start + 1);
1504 if (drv_data->regs == NULL) {
1505 dev_err(&pdev->dev, "probe - cannot map IO\n");
1506 status = -ENXIO;
1507 goto err_no_iomap;
1508 }
1509 drv_data->rd_data_phys = (dma_addr_t)res->start;
1510
1511 /* Attach to IRQ */
1512 irq = platform_get_irq(pdev, 0);
1513 if (irq < 0) {
1514 dev_err(&pdev->dev, "probe - IRQ resource not defined\n");
1515 status = -ENODEV;
1516 goto err_no_irqres;
1517 }
1518 status = request_irq(irq, spi_int, IRQF_DISABLED, dev->bus_id, drv_data);
1519 if (status < 0) {
1520 dev_err(&pdev->dev, "probe - cannot get IRQ (%d)\n", status);
1521 goto err_no_irqres;
1522 }
1523
1524 /* Setup DMA if requested */
1525 drv_data->tx_channel = -1;
1526 drv_data->rx_channel = -1;
1527 if (platform_info->enable_dma) {
1528 /* Get rx DMA channel */
1529 status = imx_dma_request_by_prio(&drv_data->rx_channel,
1530 "spi_imx_rx", DMA_PRIO_HIGH);
1531 if (status < 0) {
1532 dev_err(dev,
1533 "probe - problem (%d) requesting rx channel\n",
1534 status);
1535 goto err_no_rxdma;
1536 } else
1537 imx_dma_setup_handlers(drv_data->rx_channel, NULL,
1538 dma_err_handler, drv_data);
1539
1540 /* Get tx DMA channel */
1541 status = imx_dma_request_by_prio(&drv_data->tx_channel,
1542 "spi_imx_tx", DMA_PRIO_MEDIUM);
1543 if (status < 0) {
1544 dev_err(dev,
1545 "probe - problem (%d) requesting tx channel\n",
1546 status);
1547 imx_dma_free(drv_data->rx_channel);
1548 goto err_no_txdma;
1549 } else
1550 imx_dma_setup_handlers(drv_data->tx_channel,
1551 dma_tx_handler, dma_err_handler,
1552 drv_data);
1553
1554 /* Set request source and burst length for allocated channels */
1555 switch (drv_data->pdev->id) {
1556 case 1:
1557 /* Using SPI1 */
1558 RSSR(drv_data->rx_channel) = DMA_REQ_SPI1_R;
1559 RSSR(drv_data->tx_channel) = DMA_REQ_SPI1_T;
1560 break;
1561 case 2:
1562 /* Using SPI2 */
1563 RSSR(drv_data->rx_channel) = DMA_REQ_SPI2_R;
1564 RSSR(drv_data->tx_channel) = DMA_REQ_SPI2_T;
1565 break;
1566 default:
1567 dev_err(dev, "probe - bad SPI Id\n");
1568 imx_dma_free(drv_data->rx_channel);
1569 imx_dma_free(drv_data->tx_channel);
1570 status = -ENODEV;
1571 goto err_no_devid;
1572 }
1573 BLR(drv_data->rx_channel) = SPI_DMA_BLR;
1574 BLR(drv_data->tx_channel) = SPI_DMA_BLR;
1575 }
1576
1577 /* Load default SPI configuration */
1578 writel(SPI_RESET_START, drv_data->regs + SPI_RESET);
1579 writel(0, drv_data->regs + SPI_RESET);
1580 writel(SPI_DEFAULT_CONTROL, drv_data->regs + SPI_CONTROL);
1581
1582 /* Initial and start queue */
1583 status = init_queue(drv_data);
1584 if (status != 0) {
1585 dev_err(&pdev->dev, "probe - problem initializing queue\n");
1586 goto err_init_queue;
1587 }
1588 status = start_queue(drv_data);
1589 if (status != 0) {
1590 dev_err(&pdev->dev, "probe - problem starting queue\n");
1591 goto err_start_queue;
1592 }
1593
1594 /* Register with the SPI framework */
1595 platform_set_drvdata(pdev, drv_data);
1596 status = spi_register_master(master);
1597 if (status != 0) {
1598 dev_err(&pdev->dev, "probe - problem registering spi master\n");
1599 goto err_spi_register;
1600 }
1601
1602 dev_dbg(dev, "probe succeded\n");
1603 return 0;
1604
1605 err_init_queue:
1606 err_start_queue:
1607 err_spi_register:
1608 destroy_queue(drv_data);
1609
1610 err_no_rxdma:
1611 err_no_txdma:
1612 err_no_devid:
1613 free_irq(irq, drv_data);
1614
1615 err_no_irqres:
1616 iounmap(drv_data->regs);
1617
1618 err_no_iomap:
1619 release_resource(drv_data->ioarea);
1620 kfree(drv_data->ioarea);
1621
1622 err_no_iores:
1623 spi_master_put(master);
1624
1625 err_no_pdata:
1626 err_no_mem:
1627 return status;
1628 }
1629
1630 static int __exit spi_imx_remove(struct platform_device *pdev)
1631 {
1632 struct driver_data *drv_data = platform_get_drvdata(pdev);
1633 int irq;
1634 int status = 0;
1635
1636 if (!drv_data)
1637 return 0;
1638
1639 tasklet_kill(&drv_data->pump_transfers);
1640
1641 /* Remove the queue */
1642 status = destroy_queue(drv_data);
1643 if (status != 0) {
1644 dev_err(&pdev->dev, "queue remove failed (%d)\n", status);
1645 return status;
1646 }
1647
1648 /* Reset SPI */
1649 writel(SPI_RESET_START, drv_data->regs + SPI_RESET);
1650 writel(0, drv_data->regs + SPI_RESET);
1651
1652 /* Release DMA */
1653 if (drv_data->master_info->enable_dma) {
1654 RSSR(drv_data->rx_channel) = 0;
1655 RSSR(drv_data->tx_channel) = 0;
1656 imx_dma_free(drv_data->tx_channel);
1657 imx_dma_free(drv_data->rx_channel);
1658 }
1659
1660 /* Release IRQ */
1661 irq = platform_get_irq(pdev, 0);
1662 if (irq >= 0)
1663 free_irq(irq, drv_data);
1664
1665 /* Release map resources */
1666 iounmap(drv_data->regs);
1667 release_resource(drv_data->ioarea);
1668 kfree(drv_data->ioarea);
1669
1670 /* Disconnect from the SPI framework */
1671 spi_unregister_master(drv_data->master);
1672 spi_master_put(drv_data->master);
1673
1674 /* Prevent double remove */
1675 platform_set_drvdata(pdev, NULL);
1676
1677 dev_dbg(&pdev->dev, "remove succeded\n");
1678
1679 return 0;
1680 }
1681
1682 static void spi_imx_shutdown(struct platform_device *pdev)
1683 {
1684 struct driver_data *drv_data = platform_get_drvdata(pdev);
1685
1686 /* Reset SPI */
1687 writel(SPI_RESET_START, drv_data->regs + SPI_RESET);
1688 writel(0, drv_data->regs + SPI_RESET);
1689
1690 dev_dbg(&pdev->dev, "shutdown succeded\n");
1691 }
1692
1693 #ifdef CONFIG_PM
1694
1695 static int spi_imx_suspend(struct platform_device *pdev, pm_message_t state)
1696 {
1697 struct driver_data *drv_data = platform_get_drvdata(pdev);
1698 int status = 0;
1699
1700 status = stop_queue(drv_data);
1701 if (status != 0) {
1702 dev_warn(&pdev->dev, "suspend cannot stop queue\n");
1703 return status;
1704 }
1705
1706 dev_dbg(&pdev->dev, "suspended\n");
1707
1708 return 0;
1709 }
1710
1711 static int spi_imx_resume(struct platform_device *pdev)
1712 {
1713 struct driver_data *drv_data = platform_get_drvdata(pdev);
1714 int status = 0;
1715
1716 /* Start the queue running */
1717 status = start_queue(drv_data);
1718 if (status != 0)
1719 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1720 else
1721 dev_dbg(&pdev->dev, "resumed\n");
1722
1723 return status;
1724 }
1725 #else
1726 #define spi_imx_suspend NULL
1727 #define spi_imx_resume NULL
1728 #endif /* CONFIG_PM */
1729
1730 /* work with hotplug and coldplug */
1731 MODULE_ALIAS("platform:spi_imx");
1732
1733 static struct platform_driver driver = {
1734 .driver = {
1735 .name = "spi_imx",
1736 .owner = THIS_MODULE,
1737 },
1738 .remove = __exit_p(spi_imx_remove),
1739 .shutdown = spi_imx_shutdown,
1740 .suspend = spi_imx_suspend,
1741 .resume = spi_imx_resume,
1742 };
1743
1744 static int __init spi_imx_init(void)
1745 {
1746 return platform_driver_probe(&driver, spi_imx_probe);
1747 }
1748 module_init(spi_imx_init);
1749
1750 static void __exit spi_imx_exit(void)
1751 {
1752 platform_driver_unregister(&driver);
1753 }
1754 module_exit(spi_imx_exit);
1755
1756 MODULE_AUTHOR("Andrea Paterniani, <a.paterniani@swapp-eng.it>");
1757 MODULE_DESCRIPTION("iMX SPI Controller Driver");
1758 MODULE_LICENSE("GPL");
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