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Linux 2.6.26-rc5
[linux-2.6/openmoko-kernel/knife-kernel.git] / arch / sparc64 / kernel / sbus.c
blobe33a8a660e9e5ab0ca27199732b7758dde3d8819
1 /*
2 * sbus.c: UltraSparc SBUS controller support.
3 *
4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 #include <linux/mm.h>
10 #include <linux/spinlock.h>
11 #include <linux/slab.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14
15 #include <asm/page.h>
16 #include <asm/sbus.h>
17 #include <asm/io.h>
18 #include <asm/upa.h>
19 #include <asm/cache.h>
20 #include <asm/dma.h>
21 #include <asm/irq.h>
22 #include <asm/prom.h>
23 #include <asm/starfire.h>
24
25 #include "iommu_common.h"
26
27 #define MAP_BASE ((u32)0xc0000000)
28
29 /* Offsets from iommu_regs */
30 #define SYSIO_IOMMUREG_BASE 0x2400UL
31 #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
32 #define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */
33 #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
34 #define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */
35 #define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */
36 #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
37 #define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */
38 #define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */
39
40 #define IOMMU_DRAM_VALID (1UL << 30UL)
41
42 /* Offsets from strbuf_regs */
43 #define SYSIO_STRBUFREG_BASE 0x2800UL
44 #define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */
45 #define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */
46 #define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */
47 #define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */
48 #define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */
49 #define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */
50 #define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */
51
52 #define STRBUF_TAG_VALID 0x02UL
53
54 /* Enable 64-bit DVMA mode for the given device. */
55 void sbus_set_sbus64(struct sbus_dev *sdev, int bursts)
56 {
57 struct iommu *iommu = sdev->ofdev.dev.archdata.iommu;
58 int slot = sdev->slot;
59 unsigned long cfg_reg;
60 u64 val;
61
62 cfg_reg = iommu->write_complete_reg;
63 switch (slot) {
64 case 0:
65 cfg_reg += 0x20UL;
66 break;
67 case 1:
68 cfg_reg += 0x28UL;
69 break;
70 case 2:
71 cfg_reg += 0x30UL;
72 break;
73 case 3:
74 cfg_reg += 0x38UL;
75 break;
76 case 13:
77 cfg_reg += 0x40UL;
78 break;
79 case 14:
80 cfg_reg += 0x48UL;
81 break;
82 case 15:
83 cfg_reg += 0x50UL;
84 break;
85
86 default:
87 return;
88 };
89
90 val = upa_readq(cfg_reg);
91 if (val & (1UL << 14UL)) {
92 /* Extended transfer mode already enabled. */
93 return;
94 }
95
96 val |= (1UL << 14UL);
97
98 if (bursts & DMA_BURST8)
99 val |= (1UL << 1UL);
100 if (bursts & DMA_BURST16)
101 val |= (1UL << 2UL);
102 if (bursts & DMA_BURST32)
103 val |= (1UL << 3UL);
104 if (bursts & DMA_BURST64)
105 val |= (1UL << 4UL);
106 upa_writeq(val, cfg_reg);
107 }
108
109 /* INO number to IMAP register offset for SYSIO external IRQ's.
110 * This should conform to both Sunfire/Wildfire server and Fusion
111 * desktop designs.
112 */
113 #define SYSIO_IMAP_SLOT0 0x2c00UL
114 #define SYSIO_IMAP_SLOT1 0x2c08UL
115 #define SYSIO_IMAP_SLOT2 0x2c10UL
116 #define SYSIO_IMAP_SLOT3 0x2c18UL
117 #define SYSIO_IMAP_SCSI 0x3000UL
118 #define SYSIO_IMAP_ETH 0x3008UL
119 #define SYSIO_IMAP_BPP 0x3010UL
120 #define SYSIO_IMAP_AUDIO 0x3018UL
121 #define SYSIO_IMAP_PFAIL 0x3020UL
122 #define SYSIO_IMAP_KMS 0x3028UL
123 #define SYSIO_IMAP_FLPY 0x3030UL
124 #define SYSIO_IMAP_SHW 0x3038UL
125 #define SYSIO_IMAP_KBD 0x3040UL
126 #define SYSIO_IMAP_MS 0x3048UL
127 #define SYSIO_IMAP_SER 0x3050UL
128 #define SYSIO_IMAP_TIM0 0x3060UL
129 #define SYSIO_IMAP_TIM1 0x3068UL
130 #define SYSIO_IMAP_UE 0x3070UL
131 #define SYSIO_IMAP_CE 0x3078UL
132 #define SYSIO_IMAP_SBERR 0x3080UL
133 #define SYSIO_IMAP_PMGMT 0x3088UL
134 #define SYSIO_IMAP_GFX 0x3090UL
135 #define SYSIO_IMAP_EUPA 0x3098UL
136
137 #define bogon ((unsigned long) -1)
138 static unsigned long sysio_irq_offsets[] = {
139 /* SBUS Slot 0 --> 3, level 1 --> 7 */
140 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
141 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
142 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
143 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
144 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
145 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
146 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
147 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
148
149 /* Onboard devices (not relevant/used on SunFire). */
150 SYSIO_IMAP_SCSI,
151 SYSIO_IMAP_ETH,
152 SYSIO_IMAP_BPP,
153 bogon,
154 SYSIO_IMAP_AUDIO,
155 SYSIO_IMAP_PFAIL,
156 bogon,
157 bogon,
158 SYSIO_IMAP_KMS,
159 SYSIO_IMAP_FLPY,
160 SYSIO_IMAP_SHW,
161 SYSIO_IMAP_KBD,
162 SYSIO_IMAP_MS,
163 SYSIO_IMAP_SER,
164 bogon,
165 bogon,
166 SYSIO_IMAP_TIM0,
167 SYSIO_IMAP_TIM1,
168 bogon,
169 bogon,
170 SYSIO_IMAP_UE,
171 SYSIO_IMAP_CE,
172 SYSIO_IMAP_SBERR,
173 SYSIO_IMAP_PMGMT,
174 };
175
176 #undef bogon
177
178 #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
179
180 /* Convert Interrupt Mapping register pointer to associated
181 * Interrupt Clear register pointer, SYSIO specific version.
182 */
183 #define SYSIO_ICLR_UNUSED0 0x3400UL
184 #define SYSIO_ICLR_SLOT0 0x3408UL
185 #define SYSIO_ICLR_SLOT1 0x3448UL
186 #define SYSIO_ICLR_SLOT2 0x3488UL
187 #define SYSIO_ICLR_SLOT3 0x34c8UL
188 static unsigned long sysio_imap_to_iclr(unsigned long imap)
189 {
190 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
191 return imap + diff;
192 }
193
194 unsigned int sbus_build_irq(void *buscookie, unsigned int ino)
195 {
196 struct sbus_bus *sbus = (struct sbus_bus *)buscookie;
197 struct iommu *iommu = sbus->ofdev.dev.archdata.iommu;
198 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
199 unsigned long imap, iclr;
200 int sbus_level = 0;
201
202 imap = sysio_irq_offsets[ino];
203 if (imap == ((unsigned long)-1)) {
204 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
205 ino);
206 prom_halt();
207 }
208 imap += reg_base;
209
210 /* SYSIO inconsistency. For external SLOTS, we have to select
211 * the right ICLR register based upon the lower SBUS irq level
212 * bits.
213 */
214 if (ino >= 0x20) {
215 iclr = sysio_imap_to_iclr(imap);
216 } else {
217 int sbus_slot = (ino & 0x18)>>3;
218
219 sbus_level = ino & 0x7;
220
221 switch(sbus_slot) {
222 case 0:
223 iclr = reg_base + SYSIO_ICLR_SLOT0;
224 break;
225 case 1:
226 iclr = reg_base + SYSIO_ICLR_SLOT1;
227 break;
228 case 2:
229 iclr = reg_base + SYSIO_ICLR_SLOT2;
230 break;
231 default:
232 case 3:
233 iclr = reg_base + SYSIO_ICLR_SLOT3;
234 break;
235 };
236
237 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
238 }
239 return build_irq(sbus_level, iclr, imap);
240 }
241
242 /* Error interrupt handling. */
243 #define SYSIO_UE_AFSR 0x0030UL
244 #define SYSIO_UE_AFAR 0x0038UL
245 #define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
246 #define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
247 #define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
248 #define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
249 #define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
250 #define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
251 #define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
252 #define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */
253 #define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
254 #define SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
255 #define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
256 static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
257 {
258 struct sbus_bus *sbus = dev_id;
259 struct iommu *iommu = sbus->ofdev.dev.archdata.iommu;
260 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
261 unsigned long afsr_reg, afar_reg;
262 unsigned long afsr, afar, error_bits;
263 int reported;
264
265 afsr_reg = reg_base + SYSIO_UE_AFSR;
266 afar_reg = reg_base + SYSIO_UE_AFAR;
267
268 /* Latch error status. */
269 afsr = upa_readq(afsr_reg);
270 afar = upa_readq(afar_reg);
271
272 /* Clear primary/secondary error status bits. */
273 error_bits = afsr &
274 (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR |
275 SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR);
276 upa_writeq(error_bits, afsr_reg);
277
278 /* Log the error. */
279 printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
280 sbus->portid,
281 (((error_bits & SYSIO_UEAFSR_PPIO) ?
282 "PIO" :
283 ((error_bits & SYSIO_UEAFSR_PDRD) ?
284 "DVMA Read" :
285 ((error_bits & SYSIO_UEAFSR_PDWR) ?
286 "DVMA Write" : "???")))));
287 printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
288 sbus->portid,
289 (afsr & SYSIO_UEAFSR_DOFF) >> 45UL,
290 (afsr & SYSIO_UEAFSR_SIZE) >> 42UL,
291 (afsr & SYSIO_UEAFSR_MID) >> 37UL);
292 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
293 printk("SYSIO[%x]: Secondary UE errors [", sbus->portid);
294 reported = 0;
295 if (afsr & SYSIO_UEAFSR_SPIO) {
296 reported++;
297 printk("(PIO)");
298 }
299 if (afsr & SYSIO_UEAFSR_SDRD) {
300 reported++;
301 printk("(DVMA Read)");
302 }
303 if (afsr & SYSIO_UEAFSR_SDWR) {
304 reported++;
305 printk("(DVMA Write)");
306 }
307 if (!reported)
308 printk("(none)");
309 printk("]\n");
310
311 return IRQ_HANDLED;
312 }
313
314 #define SYSIO_CE_AFSR 0x0040UL
315 #define SYSIO_CE_AFAR 0x0048UL
316 #define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
317 #define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
318 #define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
319 #define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */
320 #define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
321 #define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
322 #define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
323 #define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
324 #define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */
325 #define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
326 #define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
327 #define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
328 static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
329 {
330 struct sbus_bus *sbus = dev_id;
331 struct iommu *iommu = sbus->ofdev.dev.archdata.iommu;
332 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
333 unsigned long afsr_reg, afar_reg;
334 unsigned long afsr, afar, error_bits;
335 int reported;
336
337 afsr_reg = reg_base + SYSIO_CE_AFSR;
338 afar_reg = reg_base + SYSIO_CE_AFAR;
339
340 /* Latch error status. */
341 afsr = upa_readq(afsr_reg);
342 afar = upa_readq(afar_reg);
343
344 /* Clear primary/secondary error status bits. */
345 error_bits = afsr &
346 (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR |
347 SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR);
348 upa_writeq(error_bits, afsr_reg);
349
350 printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
351 sbus->portid,
352 (((error_bits & SYSIO_CEAFSR_PPIO) ?
353 "PIO" :
354 ((error_bits & SYSIO_CEAFSR_PDRD) ?
355 "DVMA Read" :
356 ((error_bits & SYSIO_CEAFSR_PDWR) ?
357 "DVMA Write" : "???")))));
358
359 /* XXX Use syndrome and afar to print out module string just like
360 * XXX UDB CE trap handler does... -DaveM
361 */
362 printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
363 sbus->portid,
364 (afsr & SYSIO_CEAFSR_DOFF) >> 45UL,
365 (afsr & SYSIO_CEAFSR_ESYND) >> 48UL,
366 (afsr & SYSIO_CEAFSR_SIZE) >> 42UL,
367 (afsr & SYSIO_CEAFSR_MID) >> 37UL);
368 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
369
370 printk("SYSIO[%x]: Secondary CE errors [", sbus->portid);
371 reported = 0;
372 if (afsr & SYSIO_CEAFSR_SPIO) {
373 reported++;
374 printk("(PIO)");
375 }
376 if (afsr & SYSIO_CEAFSR_SDRD) {
377 reported++;
378 printk("(DVMA Read)");
379 }
380 if (afsr & SYSIO_CEAFSR_SDWR) {
381 reported++;
382 printk("(DVMA Write)");
383 }
384 if (!reported)
385 printk("(none)");
386 printk("]\n");
387
388 return IRQ_HANDLED;
389 }
390
391 #define SYSIO_SBUS_AFSR 0x2010UL
392 #define SYSIO_SBUS_AFAR 0x2018UL
393 #define SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */
394 #define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */
395 #define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */
396 #define SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */
397 #define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */
398 #define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */
399 #define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */
400 #define SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */
401 #define SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */
402 #define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */
403 #define SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */
404 #define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */
405 static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
406 {
407 struct sbus_bus *sbus = dev_id;
408 struct iommu *iommu = sbus->ofdev.dev.archdata.iommu;
409 unsigned long afsr_reg, afar_reg, reg_base;
410 unsigned long afsr, afar, error_bits;
411 int reported;
412
413 reg_base = iommu->write_complete_reg - 0x2000UL;
414 afsr_reg = reg_base + SYSIO_SBUS_AFSR;
415 afar_reg = reg_base + SYSIO_SBUS_AFAR;
416
417 afsr = upa_readq(afsr_reg);
418 afar = upa_readq(afar_reg);
419
420 /* Clear primary/secondary error status bits. */
421 error_bits = afsr &
422 (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR |
423 SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR);
424 upa_writeq(error_bits, afsr_reg);
425
426 /* Log the error. */
427 printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
428 sbus->portid,
429 (((error_bits & SYSIO_SBAFSR_PLE) ?
430 "Late PIO Error" :
431 ((error_bits & SYSIO_SBAFSR_PTO) ?
432 "Time Out" :
433 ((error_bits & SYSIO_SBAFSR_PBERR) ?
434 "Error Ack" : "???")))),
435 (afsr & SYSIO_SBAFSR_RD) ? 1 : 0);
436 printk("SYSIO[%x]: size[%lx] MID[%lx]\n",
437 sbus->portid,
438 (afsr & SYSIO_SBAFSR_SIZE) >> 42UL,
439 (afsr & SYSIO_SBAFSR_MID) >> 37UL);
440 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
441 printk("SYSIO[%x]: Secondary SBUS errors [", sbus->portid);
442 reported = 0;
443 if (afsr & SYSIO_SBAFSR_SLE) {
444 reported++;
445 printk("(Late PIO Error)");
446 }
447 if (afsr & SYSIO_SBAFSR_STO) {
448 reported++;
449 printk("(Time Out)");
450 }
451 if (afsr & SYSIO_SBAFSR_SBERR) {
452 reported++;
453 printk("(Error Ack)");
454 }
455 if (!reported)
456 printk("(none)");
457 printk("]\n");
458
459 /* XXX check iommu/strbuf for further error status XXX */
460
461 return IRQ_HANDLED;
462 }
463
464 #define ECC_CONTROL 0x0020UL
465 #define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */
466 #define SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */
467 #define SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */
468
469 #define SYSIO_UE_INO 0x34
470 #define SYSIO_CE_INO 0x35
471 #define SYSIO_SBUSERR_INO 0x36
472
473 static void __init sysio_register_error_handlers(struct sbus_bus *sbus)
474 {
475 struct iommu *iommu = sbus->ofdev.dev.archdata.iommu;
476 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
477 unsigned int irq;
478 u64 control;
479
480 irq = sbus_build_irq(sbus, SYSIO_UE_INO);
481 if (request_irq(irq, sysio_ue_handler, 0,
482 "SYSIO_UE", sbus) < 0) {
483 prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n",
484 sbus->portid);
485 prom_halt();
486 }
487
488 irq = sbus_build_irq(sbus, SYSIO_CE_INO);
489 if (request_irq(irq, sysio_ce_handler, 0,
490 "SYSIO_CE", sbus) < 0) {
491 prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n",
492 sbus->portid);
493 prom_halt();
494 }
495
496 irq = sbus_build_irq(sbus, SYSIO_SBUSERR_INO);
497 if (request_irq(irq, sysio_sbus_error_handler, 0,
498 "SYSIO_SBERR", sbus) < 0) {
499 prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
500 sbus->portid);
501 prom_halt();
502 }
503
504 /* Now turn the error interrupts on and also enable ECC checking. */
505 upa_writeq((SYSIO_ECNTRL_ECCEN |
506 SYSIO_ECNTRL_UEEN |
507 SYSIO_ECNTRL_CEEN),
508 reg_base + ECC_CONTROL);
509
510 control = upa_readq(iommu->write_complete_reg);
511 control |= 0x100UL; /* SBUS Error Interrupt Enable */
512 upa_writeq(control, iommu->write_complete_reg);
513 }
514
515 /* Boot time initialization. */
516 static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
517 {
518 const struct linux_prom64_registers *pr;
519 struct device_node *dp;
520 struct iommu *iommu;
521 struct strbuf *strbuf;
522 unsigned long regs, reg_base;
523 u64 control;
524 int i;
525
526 dp = of_find_node_by_phandle(__node);
527
528 sbus->portid = of_getintprop_default(dp, "upa-portid", -1);
529
530 pr = of_get_property(dp, "reg", NULL);
531 if (!pr) {
532 prom_printf("sbus_iommu_init: Cannot map SYSIO "
533 "control registers.\n");
534 prom_halt();
535 }
536 regs = pr->phys_addr;
537
538 iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
539 if (!iommu)
540 goto fatal_memory_error;
541 strbuf = kzalloc(sizeof(*strbuf), GFP_ATOMIC);
542 if (!strbuf)
543 goto fatal_memory_error;
544
545 sbus->ofdev.dev.archdata.iommu = iommu;
546 sbus->ofdev.dev.archdata.stc = strbuf;
547 sbus->ofdev.dev.archdata.numa_node = -1;
548
549 reg_base = regs + SYSIO_IOMMUREG_BASE;
550 iommu->iommu_control = reg_base + IOMMU_CONTROL;
551 iommu->iommu_tsbbase = reg_base + IOMMU_TSBBASE;
552 iommu->iommu_flush = reg_base + IOMMU_FLUSH;
553 iommu->iommu_tags = iommu->iommu_control +
554 (IOMMU_TAGDIAG - IOMMU_CONTROL);
555
556 reg_base = regs + SYSIO_STRBUFREG_BASE;
557 strbuf->strbuf_control = reg_base + STRBUF_CONTROL;
558 strbuf->strbuf_pflush = reg_base + STRBUF_PFLUSH;
559 strbuf->strbuf_fsync = reg_base + STRBUF_FSYNC;
560
561 strbuf->strbuf_enabled = 1;
562
563 strbuf->strbuf_flushflag = (volatile unsigned long *)
564 ((((unsigned long)&strbuf->__flushflag_buf[0])
565 + 63UL)
566 & ~63UL);
567 strbuf->strbuf_flushflag_pa = (unsigned long)
568 __pa(strbuf->strbuf_flushflag);
569
570 /* The SYSIO SBUS control register is used for dummy reads
571 * in order to ensure write completion.
572 */
573 iommu->write_complete_reg = regs + 0x2000UL;
574
575 printk("SYSIO: UPA portID %x, at %016lx\n",
576 sbus->portid, regs);
577
578 /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
579 if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff, -1))
580 goto fatal_memory_error;
581
582 control = upa_readq(iommu->iommu_control);
583 control = ((7UL << 16UL) |
584 (0UL << 2UL) |
585 (1UL << 1UL) |
586 (1UL << 0UL));
587 upa_writeq(control, iommu->iommu_control);
588
589 /* Clean out any cruft in the IOMMU using
590 * diagnostic accesses.
591 */
592 for (i = 0; i < 16; i++) {
593 unsigned long dram, tag;
594
595 dram = iommu->iommu_control + (IOMMU_DRAMDIAG - IOMMU_CONTROL);
596 tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL);
597
598 dram += (unsigned long)i * 8UL;
599 tag += (unsigned long)i * 8UL;
600 upa_writeq(0, dram);
601 upa_writeq(0, tag);
602 }
603 upa_readq(iommu->write_complete_reg);
604
605 /* Give the TSB to SYSIO. */
606 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
607
608 /* Setup streaming buffer, DE=1 SB_EN=1 */
609 control = (1UL << 1UL) | (1UL << 0UL);
610 upa_writeq(control, strbuf->strbuf_control);
611
612 /* Clear out the tags using diagnostics. */
613 for (i = 0; i < 16; i++) {
614 unsigned long ptag, ltag;
615
616 ptag = strbuf->strbuf_control +
617 (STRBUF_PTAGDIAG - STRBUF_CONTROL);
618 ltag = strbuf->strbuf_control +
619 (STRBUF_LTAGDIAG - STRBUF_CONTROL);
620 ptag += (unsigned long)i * 8UL;
621 ltag += (unsigned long)i * 8UL;
622
623 upa_writeq(0UL, ptag);
624 upa_writeq(0UL, ltag);
625 }
626
627 /* Enable DVMA arbitration for all devices/slots. */
628 control = upa_readq(iommu->write_complete_reg);
629 control |= 0x3fUL;
630 upa_writeq(control, iommu->write_complete_reg);
631
632 /* Now some Xfire specific grot... */
633 if (this_is_starfire)
634 starfire_hookup(sbus->portid);
635
636 sysio_register_error_handlers(sbus);
637 return;
638
639 fatal_memory_error:
640 prom_printf("sbus_iommu_init: Fatal memory allocation error.\n");
641 }
642
643 void sbus_fill_device_irq(struct sbus_dev *sdev)
644 {
645 struct device_node *dp = of_find_node_by_phandle(sdev->prom_node);
646 const struct linux_prom_irqs *irqs;
647
648 irqs = of_get_property(dp, "interrupts", NULL);
649 if (!irqs) {
650 sdev->irqs[0] = 0;
651 sdev->num_irqs = 0;
652 } else {
653 unsigned int pri = irqs[0].pri;
654
655 sdev->num_irqs = 1;
656 if (pri < 0x20)
657 pri += sdev->slot * 8;
658
659 sdev->irqs[0] = sbus_build_irq(sdev->bus, pri);
660 }
661 }
662
663 void __init sbus_arch_bus_ranges_init(struct device_node *pn, struct sbus_bus *sbus)
664 {
665 }
666
667 void __init sbus_setup_iommu(struct sbus_bus *sbus, struct device_node *dp)
668 {
669 sbus_iommu_init(dp->node, sbus);
670 }
671
672 void __init sbus_setup_arch_props(struct sbus_bus *sbus, struct device_node *dp)
673 {
674 }
675
676 int __init sbus_arch_preinit(void)
677 {
678 return 0;
679 }
680
681 void __init sbus_arch_postinit(void)
682 {
683 extern void firetruck_init(void);
684
685 firetruck_init();
686 }
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