arch/powerpc/sysdev/qe_lib/ucc_fast.c

   1 /*
   2  * arch/powerpc/sysdev/qe_lib/ucc_fast.c
   3  *
   4  * QE UCC Fast API Set - UCC Fast specific routines implementations.
   5  *
   6  * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
   7  *
   8  * Authors:     Shlomi Gridish <gridish@freescale.com>
   9  *              Li Yang <leoli@freescale.com>
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/slab.h>
  20 #include <linux/stddef.h>
  21 #include <linux/interrupt.h>
  22
  23 #include <asm/io.h>
  24 #include <asm/immap_qe.h>
  25 #include <asm/qe.h>
  26
  27 #include <asm/ucc.h>
  28 #include <asm/ucc_fast.h>
  29
  30 #define uccf_printk(level, format, arg...) \
  31         printk(level format "\n", ## arg)
  32
  33 #define uccf_dbg(format, arg...) \
  34         uccf_printk(KERN_DEBUG , format , ## arg)
  35 #define uccf_err(format, arg...) \
  36         uccf_printk(KERN_ERR , format , ## arg)
  37 #define uccf_info(format, arg...) \
  38         uccf_printk(KERN_INFO , format , ## arg)
  39 #define uccf_warn(format, arg...) \
  40         uccf_printk(KERN_WARNING , format , ## arg)
  41
  42 #ifdef UCCF_VERBOSE_DEBUG
  43 #define uccf_vdbg uccf_dbg
  44 #else
  45 #define uccf_vdbg(fmt, args...) do { } while (0)
  46 #endif                          /* UCCF_VERBOSE_DEBUG */
  47
  48 void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
  49 {
  50         uccf_info("UCC%d Fast registers:", uccf->uf_info->ucc_num);
  51         uccf_info("Base address: 0x%08x", (u32) uccf->uf_regs);
  52
  53         uccf_info("gumr  : addr - 0x%08x, val - 0x%08x",
  54                   (u32) & uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
  55         uccf_info("upsmr : addr - 0x%08x, val - 0x%08x",
  56                   (u32) & uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
  57         uccf_info("utodr : addr - 0x%08x, val - 0x%04x",
  58                   (u32) & uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
  59         uccf_info("udsr  : addr - 0x%08x, val - 0x%04x",
  60                   (u32) & uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
  61         uccf_info("ucce  : addr - 0x%08x, val - 0x%08x",
  62                   (u32) & uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
  63         uccf_info("uccm  : addr - 0x%08x, val - 0x%08x",
  64                   (u32) & uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
  65         uccf_info("uccs  : addr - 0x%08x, val - 0x%02x",
  66                   (u32) & uccf->uf_regs->uccs, uccf->uf_regs->uccs);
  67         uccf_info("urfb  : addr - 0x%08x, val - 0x%08x",
  68                   (u32) & uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
  69         uccf_info("urfs  : addr - 0x%08x, val - 0x%04x",
  70                   (u32) & uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
  71         uccf_info("urfet : addr - 0x%08x, val - 0x%04x",
  72                   (u32) & uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
  73         uccf_info("urfset: addr - 0x%08x, val - 0x%04x",
  74                   (u32) & uccf->uf_regs->urfset,
  75                   in_be16(&uccf->uf_regs->urfset));
  76         uccf_info("utfb  : addr - 0x%08x, val - 0x%08x",
  77                   (u32) & uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
  78         uccf_info("utfs  : addr - 0x%08x, val - 0x%04x",
  79                   (u32) & uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
  80         uccf_info("utfet : addr - 0x%08x, val - 0x%04x",
  81                   (u32) & uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
  82         uccf_info("utftt : addr - 0x%08x, val - 0x%04x",
  83                   (u32) & uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
  84         uccf_info("utpt  : addr - 0x%08x, val - 0x%04x",
  85                   (u32) & uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
  86         uccf_info("urtry : addr - 0x%08x, val - 0x%08x",
  87                   (u32) & uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
  88         uccf_info("guemr : addr - 0x%08x, val - 0x%02x",
  89                   (u32) & uccf->uf_regs->guemr, uccf->uf_regs->guemr);
  90 }
  91
  92 u32 ucc_fast_get_qe_cr_subblock(int uccf_num)
  93 {
  94         switch (uccf_num) {
  95         case 0: return QE_CR_SUBBLOCK_UCCFAST1;
  96         case 1: return QE_CR_SUBBLOCK_UCCFAST2;
  97         case 2: return QE_CR_SUBBLOCK_UCCFAST3;
  98         case 3: return QE_CR_SUBBLOCK_UCCFAST4;
  99         case 4: return QE_CR_SUBBLOCK_UCCFAST5;
 100         case 5: return QE_CR_SUBBLOCK_UCCFAST6;
 101         case 6: return QE_CR_SUBBLOCK_UCCFAST7;
 102         case 7: return QE_CR_SUBBLOCK_UCCFAST8;
 103         default: return QE_CR_SUBBLOCK_INVALID;
 104         }
 105 }
 106
 107 void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
 108 {
 109         out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
 110 }
 111
 112 void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
 113 {
 114         struct ucc_fast *uf_regs;
 115         u32 gumr;
 116
 117         uf_regs = uccf->uf_regs;
 118
 119         /* Enable reception and/or transmission on this UCC. */
 120         gumr = in_be32(&uf_regs->gumr);
 121         if (mode & COMM_DIR_TX) {
 122                 gumr |= UCC_FAST_GUMR_ENT;
 123                 uccf->enabled_tx = 1;
 124         }
 125         if (mode & COMM_DIR_RX) {
 126                 gumr |= UCC_FAST_GUMR_ENR;
 127                 uccf->enabled_rx = 1;
 128         }
 129         out_be32(&uf_regs->gumr, gumr);
 130 }
 131
 132 void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
 133 {
 134         struct ucc_fast *uf_regs;
 135         u32 gumr;
 136
 137         uf_regs = uccf->uf_regs;
 138
 139         /* Disable reception and/or transmission on this UCC. */
 140         gumr = in_be32(&uf_regs->gumr);
 141         if (mode & COMM_DIR_TX) {
 142                 gumr &= ~UCC_FAST_GUMR_ENT;
 143                 uccf->enabled_tx = 0;
 144         }
 145         if (mode & COMM_DIR_RX) {
 146                 gumr &= ~UCC_FAST_GUMR_ENR;
 147                 uccf->enabled_rx = 0;
 148         }
 149         out_be32(&uf_regs->gumr, gumr);
 150 }
 151
 152 int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret)
 153 {
 154         struct ucc_fast_private *uccf;
 155         struct ucc_fast *uf_regs;
 156         u32 gumr = 0;
 157         int ret;
 158
 159         uccf_vdbg("%s: IN", __FUNCTION__);
 160
 161         if (!uf_info)
 162                 return -EINVAL;
 163
 164         /* check if the UCC port number is in range. */
 165         if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
 166                 uccf_err("ucc_fast_init: Illagal UCC number!");
 167                 return -EINVAL;
 168         }
 169
 170         /* Check that 'max_rx_buf_length' is properly aligned (4). */
 171         if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {
 172                 uccf_err("ucc_fast_init: max_rx_buf_length not aligned.");
 173                 return -EINVAL;
 174         }
 175
 176         /* Validate Virtual Fifo register values */
 177         if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {
 178                 uccf_err
 179                     ("ucc_fast_init: Virtual Fifo register urfs too small.");
 180                 return -EINVAL;
 181         }
 182
 183         if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
 184                 uccf_err
 185                     ("ucc_fast_init: Virtual Fifo register urfs not aligned.");
 186                 return -EINVAL;
 187         }
 188
 189         if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
 190                 uccf_err
 191                     ("ucc_fast_init: Virtual Fifo register urfet not aligned.");
 192                 return -EINVAL;
 193         }
 194
 195         if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
 196                 uccf_err
 197                    ("ucc_fast_init: Virtual Fifo register urfset not aligned.");
 198                 return -EINVAL;
 199         }
 200
 201         if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
 202                 uccf_err
 203                     ("ucc_fast_init: Virtual Fifo register utfs not aligned.");
 204                 return -EINVAL;
 205         }
 206
 207         if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
 208                 uccf_err
 209                     ("ucc_fast_init: Virtual Fifo register utfet not aligned.");
 210                 return -EINVAL;
 211         }
 212
 213         if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
 214                 uccf_err
 215                     ("ucc_fast_init: Virtual Fifo register utftt not aligned.");
 216                 return -EINVAL;
 217         }
 218
 219         uccf = (struct ucc_fast_private *)
 220                  kmalloc(sizeof(struct ucc_fast_private), GFP_KERNEL);
 221         if (!uccf) {
 222                 uccf_err
 223                     ("ucc_fast_init: No memory for UCC slow data structure!");
 224                 return -ENOMEM;
 225         }
 226         memset(uccf, 0, sizeof(struct ucc_fast_private));
 227
 228         /* Fill fast UCC structure */
 229         uccf->uf_info = uf_info;
 230         /* Set the PHY base address */
 231         uccf->uf_regs =
 232             (struct ucc_fast *) ioremap(uf_info->regs, sizeof(struct ucc_fast));
 233         if (uccf->uf_regs == NULL) {
 234                 uccf_err
 235                     ("ucc_fast_init: No memory map for UCC slow controller!");
 236                 return -ENOMEM;
 237         }
 238
 239         uccf->enabled_tx = 0;
 240         uccf->enabled_rx = 0;
 241         uccf->stopped_tx = 0;
 242         uccf->stopped_rx = 0;
 243         uf_regs = uccf->uf_regs;
 244         uccf->p_ucce = (u32 *) & (uf_regs->ucce);
 245         uccf->p_uccm = (u32 *) & (uf_regs->uccm);
 246 #ifdef STATISTICS
 247         uccf->tx_frames = 0;
 248         uccf->rx_frames = 0;
 249         uccf->rx_discarded = 0;
 250 #endif                          /* STATISTICS */
 251
 252         /* Init Guemr register */
 253         if ((ret = ucc_init_guemr((struct ucc_common *) (uf_regs)))) {
 254                 uccf_err("ucc_fast_init: Could not init the guemr register.");
 255                 ucc_fast_free(uccf);
 256                 return ret;
 257         }
 258
 259         /* Set UCC to fast type */
 260         if ((ret = ucc_set_type(uf_info->ucc_num,
 261                                 (struct ucc_common *) (uf_regs),
 262                                 UCC_SPEED_TYPE_FAST))) {
 263                 uccf_err("ucc_fast_init: Could not set type to fast.");
 264                 ucc_fast_free(uccf);
 265                 return ret;
 266         }
 267
 268         uccf->mrblr = uf_info->max_rx_buf_length;
 269
 270         /* Set GUMR */
 271         /* For more details see the hardware spec. */
 272         /* gumr starts as zero. */
 273         if (uf_info->tci)
 274                 gumr |= UCC_FAST_GUMR_TCI;
 275         gumr |= uf_info->ttx_trx;
 276         if (uf_info->cdp)
 277                 gumr |= UCC_FAST_GUMR_CDP;
 278         if (uf_info->ctsp)
 279                 gumr |= UCC_FAST_GUMR_CTSP;
 280         if (uf_info->cds)
 281                 gumr |= UCC_FAST_GUMR_CDS;
 282         if (uf_info->ctss)
 283                 gumr |= UCC_FAST_GUMR_CTSS;
 284         if (uf_info->txsy)
 285                 gumr |= UCC_FAST_GUMR_TXSY;
 286         if (uf_info->rsyn)
 287                 gumr |= UCC_FAST_GUMR_RSYN;
 288         gumr |= uf_info->synl;
 289         if (uf_info->rtsm)
 290                 gumr |= UCC_FAST_GUMR_RTSM;
 291         gumr |= uf_info->renc;
 292         if (uf_info->revd)
 293                 gumr |= UCC_FAST_GUMR_REVD;
 294         gumr |= uf_info->tenc;
 295         gumr |= uf_info->tcrc;
 296         gumr |= uf_info->mode;
 297         out_be32(&uf_regs->gumr, gumr);
 298
 299         /* Allocate memory for Tx Virtual Fifo */
 300         uccf->ucc_fast_tx_virtual_fifo_base_offset =
 301             qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
 302         if (IS_MURAM_ERR(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
 303                 uccf_err
 304                     ("ucc_fast_init: Can not allocate MURAM memory for "
 305                         "struct ucc_fastx_virtual_fifo_base_offset.");
 306                 uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
 307                 ucc_fast_free(uccf);
 308                 return -ENOMEM;
 309         }
 310
 311         /* Allocate memory for Rx Virtual Fifo */
 312         uccf->ucc_fast_rx_virtual_fifo_base_offset =
 313             qe_muram_alloc(uf_info->urfs +
 314                            (u32)
 315                            UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,
 316                            UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
 317         if (IS_MURAM_ERR(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
 318                 uccf_err
 319                     ("ucc_fast_init: Can not allocate MURAM memory for "
 320                         "ucc_fast_rx_virtual_fifo_base_offset.");
 321                 uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
 322                 ucc_fast_free(uccf);
 323                 return -ENOMEM;
 324         }
 325
 326         /* Set Virtual Fifo registers */
 327         out_be16(&uf_regs->urfs, uf_info->urfs);
 328         out_be16(&uf_regs->urfet, uf_info->urfet);
 329         out_be16(&uf_regs->urfset, uf_info->urfset);
 330         out_be16(&uf_regs->utfs, uf_info->utfs);
 331         out_be16(&uf_regs->utfet, uf_info->utfet);
 332         out_be16(&uf_regs->utftt, uf_info->utftt);
 333         /* utfb, urfb are offsets from MURAM base */
 334         out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);
 335         out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);
 336
 337         /* Mux clocking */
 338         /* Grant Support */
 339         ucc_set_qe_mux_grant(uf_info->ucc_num, uf_info->grant_support);
 340         /* Breakpoint Support */
 341         ucc_set_qe_mux_bkpt(uf_info->ucc_num, uf_info->brkpt_support);
 342         /* Set Tsa or NMSI mode. */
 343         ucc_set_qe_mux_tsa(uf_info->ucc_num, uf_info->tsa);
 344         /* If NMSI (not Tsa), set Tx and Rx clock. */
 345         if (!uf_info->tsa) {
 346                 /* Rx clock routing */
 347                 if (uf_info->rx_clock != QE_CLK_NONE) {
 348                         if (ucc_set_qe_mux_rxtx
 349                             (uf_info->ucc_num, uf_info->rx_clock,
 350                              COMM_DIR_RX)) {
 351                                 uccf_err
 352                 ("ucc_fast_init: Illegal value for parameter 'RxClock'.");
 353                                 ucc_fast_free(uccf);
 354                                 return -EINVAL;
 355                         }
 356                 }
 357                 /* Tx clock routing */
 358                 if (uf_info->tx_clock != QE_CLK_NONE) {
 359                         if (ucc_set_qe_mux_rxtx
 360                             (uf_info->ucc_num, uf_info->tx_clock,
 361                              COMM_DIR_TX)) {
 362                                 uccf_err
 363                 ("ucc_fast_init: Illegal value for parameter 'TxClock'.");
 364                                 ucc_fast_free(uccf);
 365                                 return -EINVAL;
 366                         }
 367                 }
 368         }
 369
 370         /* Set interrupt mask register at UCC level. */
 371         out_be32(&uf_regs->uccm, uf_info->uccm_mask);
 372
 373         /* First, clear anything pending at UCC level,
 374          * otherwise, old garbage may come through
 375          * as soon as the dam is opened
 376          * Writing '1' clears
 377          */
 378         out_be32(&uf_regs->ucce, 0xffffffff);
 379
 380         *uccf_ret = uccf;
 381         return 0;
 382 }
 383
 384 void ucc_fast_free(struct ucc_fast_private * uccf)
 385 {
 386         if (!uccf)
 387                 return;
 388
 389         if (uccf->ucc_fast_tx_virtual_fifo_base_offset)
 390                 qe_muram_free(uccf->ucc_fast_tx_virtual_fifo_base_offset);
 391
 392         if (uccf->ucc_fast_rx_virtual_fifo_base_offset)
 393                 qe_muram_free(uccf->ucc_fast_rx_virtual_fifo_base_offset);
 394
 395         kfree(uccf);
 396 }