include/asm-x86/uv/uv_mmrs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV MMR definitions
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #ifndef __ASM_X86_UV_MMRS__
  12 #define __ASM_X86_UV_MMRS__
  13
  14 /*
  15  *       AUTO GENERATED - Do not edit
  16  */
  17
  18  #define UV_MMR_ENABLE          (1UL << 63)
  19
  20 /* ========================================================================= */
  21 /*                               UVH_IPI_INT                                 */
  22 /* ========================================================================= */
  23 #define UVH_IPI_INT 0x60500UL
  24 #define UVH_IPI_INT_32 0x0360
  25
  26 #define UVH_IPI_INT_VECTOR_SHFT 0
  27 #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
  28 #define UVH_IPI_INT_DELIVERY_MODE_SHFT 8
  29 #define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
  30 #define UVH_IPI_INT_DESTMODE_SHFT 11
  31 #define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
  32 #define UVH_IPI_INT_APIC_ID_SHFT 16
  33 #define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
  34 #define UVH_IPI_INT_SEND_SHFT 63
  35 #define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL
  36
  37 union uvh_ipi_int_u {
  38     unsigned long       v;
  39     struct uvh_ipi_int_s {
  40         unsigned long   vector_       :  8;  /* RW */
  41         unsigned long   delivery_mode :  3;  /* RW */
  42         unsigned long   destmode      :  1;  /* RW */
  43         unsigned long   rsvd_12_15    :  4;  /*    */
  44         unsigned long   apic_id       : 32;  /* RW */
  45         unsigned long   rsvd_48_62    : 15;  /*    */
  46         unsigned long   send          :  1;  /* WP */
  47     } s;
  48 };
  49
  50 /* ========================================================================= */
  51 /*                   UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST                     */
  52 /* ========================================================================= */
  53 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
  54 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009f0
  55
  56 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
  57 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
  58 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
  59 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
  60
  61 union uvh_lb_bau_intd_payload_queue_first_u {
  62     unsigned long       v;
  63     struct uvh_lb_bau_intd_payload_queue_first_s {
  64         unsigned long   rsvd_0_3:  4;  /*    */
  65         unsigned long   address : 39;  /* RW */
  66         unsigned long   rsvd_43_48:  6;  /*    */
  67         unsigned long   node_id : 14;  /* RW */
  68         unsigned long   rsvd_63 :  1;  /*    */
  69     } s;
  70 };
  71
  72 /* ========================================================================= */
  73 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST                     */
  74 /* ========================================================================= */
  75 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
  76 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009f8
  77
  78 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
  79 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
  80
  81 union uvh_lb_bau_intd_payload_queue_last_u {
  82     unsigned long       v;
  83     struct uvh_lb_bau_intd_payload_queue_last_s {
  84         unsigned long   rsvd_0_3:  4;  /*    */
  85         unsigned long   address : 39;  /* RW */
  86         unsigned long   rsvd_43_63: 21;  /*    */
  87     } s;
  88 };
  89
  90 /* ========================================================================= */
  91 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL                     */
  92 /* ========================================================================= */
  93 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
  94 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x00a00
  95
  96 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
  97 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
  98
  99 union uvh_lb_bau_intd_payload_queue_tail_u {
 100     unsigned long       v;
 101     struct uvh_lb_bau_intd_payload_queue_tail_s {
 102         unsigned long   rsvd_0_3:  4;  /*    */
 103         unsigned long   address : 39;  /* RW */
 104         unsigned long   rsvd_43_63: 21;  /*    */
 105     } s;
 106 };
 107
 108 /* ========================================================================= */
 109 /*                   UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE                    */
 110 /* ========================================================================= */
 111 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
 112
 113 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
 114 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
 115 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
 116 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
 117 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
 118 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
 119 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
 120 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
 121 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
 122 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
 123 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
 124 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
 125 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
 126 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
 127 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
 128 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
 129 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
 130 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
 131 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
 132 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
 133 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
 134 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
 135 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
 136 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
 137 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
 138 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
 139 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
 140 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
 141 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
 142 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
 143 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
 144 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
 145 union uvh_lb_bau_intd_software_acknowledge_u {
 146     unsigned long       v;
 147     struct uvh_lb_bau_intd_software_acknowledge_s {
 148         unsigned long   pending_0 :  1;  /* RW, W1C */
 149         unsigned long   pending_1 :  1;  /* RW, W1C */
 150         unsigned long   pending_2 :  1;  /* RW, W1C */
 151         unsigned long   pending_3 :  1;  /* RW, W1C */
 152         unsigned long   pending_4 :  1;  /* RW, W1C */
 153         unsigned long   pending_5 :  1;  /* RW, W1C */
 154         unsigned long   pending_6 :  1;  /* RW, W1C */
 155         unsigned long   pending_7 :  1;  /* RW, W1C */
 156         unsigned long   timeout_0 :  1;  /* RW, W1C */
 157         unsigned long   timeout_1 :  1;  /* RW, W1C */
 158         unsigned long   timeout_2 :  1;  /* RW, W1C */
 159         unsigned long   timeout_3 :  1;  /* RW, W1C */
 160         unsigned long   timeout_4 :  1;  /* RW, W1C */
 161         unsigned long   timeout_5 :  1;  /* RW, W1C */
 162         unsigned long   timeout_6 :  1;  /* RW, W1C */
 163         unsigned long   timeout_7 :  1;  /* RW, W1C */
 164         unsigned long   rsvd_16_63: 48;  /*    */
 165     } s;
 166 };
 167
 168 /* ========================================================================= */
 169 /*                UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS                 */
 170 /* ========================================================================= */
 171 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
 172
 173 /* ========================================================================= */
 174 /*                     UVH_LB_BAU_SB_ACTIVATION_CONTROL                      */
 175 /* ========================================================================= */
 176 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
 177 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009d8
 178
 179 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
 180 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
 181 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
 182 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
 183 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63
 184 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
 185
 186 union uvh_lb_bau_sb_activation_control_u {
 187     unsigned long       v;
 188     struct uvh_lb_bau_sb_activation_control_s {
 189         unsigned long   index :  6;  /* RW */
 190         unsigned long   rsvd_6_61: 56;  /*    */
 191         unsigned long   push  :  1;  /* WP */
 192         unsigned long   init  :  1;  /* WP */
 193     } s;
 194 };
 195
 196 /* ========================================================================= */
 197 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_0                      */
 198 /* ========================================================================= */
 199 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
 200 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009e0
 201
 202 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
 203 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
 204
 205 union uvh_lb_bau_sb_activation_status_0_u {
 206     unsigned long       v;
 207     struct uvh_lb_bau_sb_activation_status_0_s {
 208         unsigned long   status : 64;  /* RW */
 209     } s;
 210 };
 211
 212 /* ========================================================================= */
 213 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_1                      */
 214 /* ========================================================================= */
 215 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
 216 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009e8
 217
 218 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
 219 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
 220
 221 union uvh_lb_bau_sb_activation_status_1_u {
 222     unsigned long       v;
 223     struct uvh_lb_bau_sb_activation_status_1_s {
 224         unsigned long   status : 64;  /* RW */
 225     } s;
 226 };
 227
 228 /* ========================================================================= */
 229 /*                      UVH_LB_BAU_SB_DESCRIPTOR_BASE                        */
 230 /* ========================================================================= */
 231 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
 232 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009d0
 233
 234 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
 235 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
 236 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
 237 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
 238
 239 union uvh_lb_bau_sb_descriptor_base_u {
 240     unsigned long       v;
 241     struct uvh_lb_bau_sb_descriptor_base_s {
 242         unsigned long   rsvd_0_11    : 12;  /*    */
 243         unsigned long   page_address : 31;  /* RW */
 244         unsigned long   rsvd_43_48   :  6;  /*    */
 245         unsigned long   node_id      : 14;  /* RW */
 246         unsigned long   rsvd_63      :  1;  /*    */
 247     } s;
 248 };
 249
 250 /* ========================================================================= */
 251 /*                               UVH_NODE_ID                                 */
 252 /* ========================================================================= */
 253 #define UVH_NODE_ID 0x0UL
 254
 255 #define UVH_NODE_ID_FORCE1_SHFT 0
 256 #define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
 257 #define UVH_NODE_ID_MANUFACTURER_SHFT 1
 258 #define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
 259 #define UVH_NODE_ID_PART_NUMBER_SHFT 12
 260 #define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
 261 #define UVH_NODE_ID_REVISION_SHFT 28
 262 #define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
 263 #define UVH_NODE_ID_NODE_ID_SHFT 32
 264 #define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
 265 #define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
 266 #define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
 267 #define UVH_NODE_ID_NI_PORT_SHFT 56
 268 #define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
 269
 270 union uvh_node_id_u {
 271     unsigned long       v;
 272     struct uvh_node_id_s {
 273         unsigned long   force1        :  1;  /* RO */
 274         unsigned long   manufacturer  : 11;  /* RO */
 275         unsigned long   part_number   : 16;  /* RO */
 276         unsigned long   revision      :  4;  /* RO */
 277         unsigned long   node_id       : 15;  /* RW */
 278         unsigned long   rsvd_47       :  1;  /*    */
 279         unsigned long   nodes_per_bit :  7;  /* RW */
 280         unsigned long   rsvd_55       :  1;  /*    */
 281         unsigned long   ni_port       :  4;  /* RO */
 282         unsigned long   rsvd_60_63    :  4;  /*    */
 283     } s;
 284 };
 285
 286 /* ========================================================================= */
 287 /*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */
 288 /* ========================================================================= */
 289 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
 290
 291 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
 292 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
 293 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 46
 294 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0000400000000000UL
 295 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
 296 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
 297 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
 298 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
 299
 300 union uvh_rh_gam_gru_overlay_config_mmr_u {
 301     unsigned long       v;
 302     struct uvh_rh_gam_gru_overlay_config_mmr_s {
 303         unsigned long   rsvd_0_27: 28;  /*    */
 304         unsigned long   base   : 18;  /* RW */
 305         unsigned long   gr4    :  1;  /* RW */
 306         unsigned long   rsvd_47_51:  5;  /*    */
 307         unsigned long   n_gru  :  4;  /* RW */
 308         unsigned long   rsvd_56_62:  7;  /*    */
 309         unsigned long   enable :  1;  /* RW */
 310     } s;
 311 };
 312
 313 /* ========================================================================= */
 314 /*                    UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR                      */
 315 /* ========================================================================= */
 316 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
 317
 318 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
 319 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
 320 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
 321 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
 322 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
 323 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
 324
 325 union uvh_rh_gam_mmr_overlay_config_mmr_u {
 326     unsigned long       v;
 327     struct uvh_rh_gam_mmr_overlay_config_mmr_s {
 328         unsigned long   rsvd_0_25: 26;  /*    */
 329         unsigned long   base     : 20;  /* RW */
 330         unsigned long   dual_hub :  1;  /* RW */
 331         unsigned long   rsvd_47_62: 16;  /*    */
 332         unsigned long   enable   :  1;  /* RW */
 333     } s;
 334 };
 335
 336 /* ========================================================================= */
 337 /*                                 UVH_RTC                                   */
 338 /* ========================================================================= */
 339 #define UVH_RTC 0x28000UL
 340
 341 #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
 342 #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
 343
 344 union uvh_rtc_u {
 345     unsigned long       v;
 346     struct uvh_rtc_s {
 347         unsigned long   real_time_clock : 56;  /* RW */
 348         unsigned long   rsvd_56_63      :  8;  /*    */
 349     } s;
 350 };
 351
 352 /* ========================================================================= */
 353 /*                          UVH_SI_ADDR_MAP_CONFIG                           */
 354 /* ========================================================================= */
 355 #define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
 356
 357 #define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
 358 #define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
 359 #define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
 360 #define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
 361
 362 union uvh_si_addr_map_config_u {
 363     unsigned long       v;
 364     struct uvh_si_addr_map_config_s {
 365         unsigned long   m_skt :  6;  /* RW */
 366         unsigned long   rsvd_6_7:  2;  /*    */
 367         unsigned long   n_skt :  4;  /* RW */
 368         unsigned long   rsvd_12_63: 52;  /*    */
 369     } s;
 370 };
 371
 372
 373 #endif /* __ASM_X86_UV_MMRS__ */