drivers/net/tulip/tulip.h

   1 /*
   2         drivers/net/tulip/tulip.h
   3
   4         Copyright 2000,2001  The Linux Kernel Team
   5         Written/copyright 1994-2001 by Donald Becker.
   6
   7         This software may be used and distributed according to the terms
   8         of the GNU General Public License, incorporated herein by reference.
   9
  10         Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
  11         for more information on this driver, or visit the project
  12         Web page at http://sourceforge.net/projects/tulip/
  13
  14 */
  15
  16 #ifndef __NET_TULIP_H__
  17 #define __NET_TULIP_H__
  18
  19 #include <linux/config.h>
  20 #include <linux/kernel.h>
  21 #include <linux/types.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/netdevice.h>
  24 #include <linux/timer.h>
  25 #include <linux/delay.h>
  26 #include <asm/io.h>
  27 #include <asm/irq.h>
  28
  29
  30
  31 /* undefine, or define to various debugging levels (>4 == obscene levels) */
  32 #define TULIP_DEBUG 1
  33
  34 /* undefine USE_IO_OPS for MMIO, define for PIO */
  35 #ifdef CONFIG_TULIP_MMIO
  36 # undef USE_IO_OPS
  37 #else
  38 # define USE_IO_OPS 1
  39 #endif
  40
  41
  42
  43 struct tulip_chip_table {
  44         char *chip_name;
  45         int io_size;
  46         int valid_intrs;        /* CSR7 interrupt enable settings */
  47         int flags;
  48         void (*media_timer) (unsigned long data);
  49 };
  50
  51
  52 enum tbl_flag {
  53         HAS_MII                 = 0x0001,
  54         HAS_MEDIA_TABLE         = 0x0002,
  55         CSR12_IN_SROM           = 0x0004,
  56         ALWAYS_CHECK_MII        = 0x0008,
  57         HAS_ACPI                = 0x0010,
  58         MC_HASH_ONLY            = 0x0020, /* Hash-only multicast filter. */
  59         HAS_PNICNWAY            = 0x0080,
  60         HAS_NWAY                = 0x0040, /* Uses internal NWay xcvr. */
  61         HAS_INTR_MITIGATION     = 0x0100,
  62         IS_ASIX                 = 0x0200,
  63         HAS_8023X               = 0x0400,
  64         COMET_MAC_ADDR          = 0x0800,
  65         HAS_PCI_MWI             = 0x1000,
  66         HAS_PHY_IRQ             = 0x2000,
  67         HAS_SWAPPED_SEEPROM     = 0x4000,
  68         NEEDS_FAKE_MEDIA_TABLE  = 0x8000,
  69 };
  70
  71
  72 /* chip types.  careful!  order is VERY IMPORTANT here, as these
  73  * are used throughout the driver as indices into arrays */
  74 /* Note 21142 == 21143. */
  75 enum chips {
  76         DC21040 = 0,
  77         DC21041 = 1,
  78         DC21140 = 2,
  79         DC21142 = 3, DC21143 = 3,
  80         LC82C168,
  81         MX98713,
  82         MX98715,
  83         MX98725,
  84         AX88140,
  85         PNIC2,
  86         COMET,
  87         COMPEX9881,
  88         I21145,
  89         DM910X,
  90         CONEXANT,
  91 };
  92
  93
  94 enum MediaIs {
  95         MediaIsFD = 1,
  96         MediaAlwaysFD = 2,
  97         MediaIsMII = 4,
  98         MediaIsFx = 8,
  99         MediaIs100 = 16
 100 };
 101
 102
 103 /* Offsets to the Command and Status Registers, "CSRs".  All accesses
 104    must be longword instructions and quadword aligned. */
 105 enum tulip_offsets {
 106         CSR0 = 0,
 107         CSR1 = 0x08,
 108         CSR2 = 0x10,
 109         CSR3 = 0x18,
 110         CSR4 = 0x20,
 111         CSR5 = 0x28,
 112         CSR6 = 0x30,
 113         CSR7 = 0x38,
 114         CSR8 = 0x40,
 115         CSR9 = 0x48,
 116         CSR10 = 0x50,
 117         CSR11 = 0x58,
 118         CSR12 = 0x60,
 119         CSR13 = 0x68,
 120         CSR14 = 0x70,
 121         CSR15 = 0x78,
 122 };
 123
 124 /* register offset and bits for CFDD PCI config reg */
 125 enum pci_cfg_driver_reg {
 126         CFDD = 0x40,
 127         CFDD_Sleep = (1 << 31),
 128         CFDD_Snooze = (1 << 30),
 129 };
 130
 131 #define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)
 132
 133 /* The bits in the CSR5 status registers, mostly interrupt sources. */
 134 enum status_bits {
 135         TimerInt = 0x800,
 136         SytemError = 0x2000,
 137         TPLnkFail = 0x1000,
 138         TPLnkPass = 0x10,
 139         NormalIntr = 0x10000,
 140         AbnormalIntr = 0x8000,
 141         RxJabber = 0x200,
 142         RxDied = 0x100,
 143         RxNoBuf = 0x80,
 144         RxIntr = 0x40,
 145         TxFIFOUnderflow = 0x20,
 146         TxJabber = 0x08,
 147         TxNoBuf = 0x04,
 148         TxDied = 0x02,
 149         TxIntr = 0x01,
 150 };
 151
 152 /* bit mask for CSR5 TX/RX process state */
 153 #define CSR5_TS 0x00700000
 154 #define CSR5_RS 0x000e0000
 155
 156 enum tulip_mode_bits {
 157         TxThreshold             = (1 << 22),
 158         FullDuplex              = (1 << 9),
 159         TxOn                    = 0x2000,
 160         AcceptBroadcast         = 0x0100,
 161         AcceptAllMulticast      = 0x0080,
 162         AcceptAllPhys           = 0x0040,
 163         AcceptRunt              = 0x0008,
 164         RxOn                    = 0x0002,
 165         RxTx                    = (TxOn | RxOn),
 166 };
 167
 168
 169 enum tulip_busconfig_bits {
 170         MWI                     = (1 << 24),
 171         MRL                     = (1 << 23),
 172         MRM                     = (1 << 21),
 173         CALShift                = 14,
 174         BurstLenShift           = 8,
 175 };
 176
 177
 178 /* The Tulip Rx and Tx buffer descriptors. */
 179 struct tulip_rx_desc {
 180         s32 status;
 181         s32 length;
 182         u32 buffer1;
 183         u32 buffer2;
 184 };
 185
 186
 187 struct tulip_tx_desc {
 188         s32 status;
 189         s32 length;
 190         u32 buffer1;
 191         u32 buffer2;            /* We use only buffer 1.  */
 192 };
 193
 194
 195 enum desc_status_bits {
 196         DescOwned = 0x80000000,
 197         RxDescFatalErr = 0x8000,
 198         RxWholePkt = 0x0300,
 199 };
 200
 201
 202 enum t21143_csr6_bits {
 203         csr6_sc = (1<<31),
 204         csr6_ra = (1<<30),
 205         csr6_ign_dest_msb = (1<<26),
 206         csr6_mbo = (1<<25),
 207         csr6_scr = (1<<24),  /* scramble mode flag: can't be set */
 208         csr6_pcs = (1<<23),  /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
 209         csr6_ttm = (1<<22),  /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
 210         csr6_sf = (1<<21),   /* Store and forward. If set ignores TR bits */
 211         csr6_hbd = (1<<19),  /* Heart beat disable. Disables SQE function in 10baseT */
 212         csr6_ps = (1<<18),   /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
 213         csr6_ca = (1<<17),   /* Collision Offset Enable. If set uses special algorithm in low collision situations */
 214         csr6_trh = (1<<15),  /* Transmit Threshold high bit */
 215         csr6_trl = (1<<14),  /* Transmit Threshold low bit */
 216
 217         /***************************************************************
 218          * This table shows transmit threshold values based on media   *
 219          * and these two registers (from PNIC1 & 2 docs) Note: this is *
 220          * all meaningless if sf is set.                               *
 221          ***************************************************************/
 222
 223         /***********************************
 224          * (trh,trl) * 100BaseTX * 10BaseT *
 225          ***********************************
 226          *   (0,0)   *     128   *    72   *
 227          *   (0,1)   *     256   *    96   *
 228          *   (1,0)   *     512   *   128   *
 229          *   (1,1)   *    1024   *   160   *
 230          ***********************************/
 231
 232         csr6_fc = (1<<12),   /* Forces a collision in next transmission (for testing in loopback mode) */
 233         csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
 234         csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
 235         /* set both and you get (PHY) loopback */
 236         csr6_fd = (1<<9),    /* Full duplex mode, disables hearbeat, no loopback */
 237         csr6_pm = (1<<7),    /* Pass All Multicast */
 238         csr6_pr = (1<<6),    /* Promiscuous mode */
 239         csr6_sb = (1<<5),    /* Start(1)/Stop(0) backoff counter */
 240         csr6_if = (1<<4),    /* Inverse Filtering, rejects only addresses in address table: can't be set */
 241         csr6_pb = (1<<3),    /* Pass Bad Frames, (1) causes even bad frames to be passed on */
 242         csr6_ho = (1<<2),    /* Hash-only filtering mode: can't be set */
 243         csr6_hp = (1<<0),    /* Hash/Perfect Receive Filtering Mode: can't be set */
 244
 245         csr6_mask_capture = (csr6_sc | csr6_ca),
 246         csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
 247         csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
 248         csr6_mask_hdcaptt = (csr6_mask_hdcap  | csr6_trh | csr6_trl),
 249         csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
 250         csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
 251         csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
 252         csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
 253 };
 254
 255
 256 /* Keep the ring sizes a power of two for efficiency.
 257    Making the Tx ring too large decreases the effectiveness of channel
 258    bonding and packet priority.
 259    There are no ill effects from too-large receive rings. */
 260
 261 #define TX_RING_SIZE    32
 262 #define RX_RING_SIZE    128
 263 #define MEDIA_MASK     31
 264
 265 #define PKT_BUF_SZ              1536    /* Size of each temporary Rx buffer. */
 266
 267 #define TULIP_MIN_CACHE_LINE    8       /* in units of 32-bit words */
 268
 269 #if defined(__sparc__) || defined(__hppa__)
 270 /* The UltraSparc PCI controllers will disconnect at every 64-byte
 271  * crossing anyways so it makes no sense to tell Tulip to burst
 272  * any more than that.
 273  */
 274 #define TULIP_MAX_CACHE_LINE    16      /* in units of 32-bit words */
 275 #else
 276 #define TULIP_MAX_CACHE_LINE    32      /* in units of 32-bit words */
 277 #endif
 278
 279
 280 /* Ring-wrap flag in length field, use for last ring entry.
 281         0x01000000 means chain on buffer2 address,
 282         0x02000000 means use the ring start address in CSR2/3.
 283    Note: Some work-alike chips do not function correctly in chained mode.
 284    The ASIX chip works only in chained mode.
 285    Thus we indicates ring mode, but always write the 'next' field for
 286    chained mode as well.
 287 */
 288 #define DESC_RING_WRAP 0x02000000
 289
 290
 291 #define EEPROM_SIZE 512         /* 2 << EEPROM_ADDRLEN */
 292
 293
 294 #define RUN_AT(x) (jiffies + (x))
 295
 296 #if defined(__i386__)                   /* AKA get_unaligned() */
 297 #define get_u16(ptr) (*(u16 *)(ptr))
 298 #else
 299 #define get_u16(ptr) (((u8*)(ptr))[0] + (((u8*)(ptr))[1]<<8))
 300 #endif
 301
 302 struct medialeaf {
 303         u8 type;
 304         u8 media;
 305         unsigned char *leafdata;
 306 };
 307
 308
 309 struct mediatable {
 310         u16 defaultmedia;
 311         u8 leafcount;
 312         u8 csr12dir;            /* General purpose pin directions. */
 313         unsigned has_mii:1;
 314         unsigned has_nonmii:1;
 315         unsigned has_reset:6;
 316         u32 csr15dir;
 317         u32 csr15val;           /* 21143 NWay setting. */
 318         struct medialeaf mleaf[0];
 319 };
 320
 321
 322 struct mediainfo {
 323         struct mediainfo *next;
 324         int info_type;
 325         int index;
 326         unsigned char *info;
 327 };
 328
 329 struct ring_info {
 330         struct sk_buff  *skb;
 331         dma_addr_t      mapping;
 332 };
 333
 334
 335 struct tulip_private {
 336         const char *product_name;
 337         struct net_device *next_module;
 338         struct tulip_rx_desc *rx_ring;
 339         struct tulip_tx_desc *tx_ring;
 340         dma_addr_t rx_ring_dma;
 341         dma_addr_t tx_ring_dma;
 342         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 343         struct ring_info tx_buffers[TX_RING_SIZE];
 344         /* The addresses of receive-in-place skbuffs. */
 345         struct ring_info rx_buffers[RX_RING_SIZE];
 346         u16 setup_frame[96];    /* Pseudo-Tx frame to init address table. */
 347         int chip_id;
 348         int revision;
 349         int flags;
 350         struct net_device_stats stats;
 351         struct timer_list timer;        /* Media selection timer. */
 352         struct timer_list oom_timer;    /* Out of memory timer. */
 353         u32 mc_filter[2];
 354         spinlock_t lock;
 355         spinlock_t mii_lock;
 356         unsigned int cur_rx, cur_tx;    /* The next free ring entry */
 357         unsigned int dirty_rx, dirty_tx;        /* The ring entries to be free()ed. */
 358
 359 #ifdef  CONFIG_TULIP_NAPI_HW_MITIGATION
 360         int mit_on;
 361 #endif
 362         unsigned int full_duplex:1;     /* Full-duplex operation requested. */
 363         unsigned int full_duplex_lock:1;
 364         unsigned int fake_addr:1;       /* Multiport board faked address. */
 365         unsigned int default_port:4;    /* Last dev->if_port value. */
 366         unsigned int media2:4;  /* Secondary monitored media port. */
 367         unsigned int medialock:1;       /* Don't sense media type. */
 368         unsigned int mediasense:1;      /* Media sensing in progress. */
 369         unsigned int nway:1, nwayset:1;         /* 21143 internal NWay. */
 370         unsigned int csr0;      /* CSR0 setting. */
 371         unsigned int csr6;      /* Current CSR6 control settings. */
 372         unsigned char eeprom[EEPROM_SIZE];      /* Serial EEPROM contents. */
 373         void (*link_change) (struct net_device * dev, int csr5);
 374         u16 sym_advertise, mii_advertise; /* NWay capabilities advertised.  */
 375         u16 lpar;               /* 21143 Link partner ability. */
 376         u16 advertising[4];
 377         signed char phys[4], mii_cnt;   /* MII device addresses. */
 378         struct mediatable *mtable;
 379         int cur_index;          /* Current media index. */
 380         int saved_if_port;
 381         struct pci_dev *pdev;
 382         int ttimer;
 383         int susp_rx;
 384         unsigned long nir;
 385         void __iomem *base_addr;
 386         int csr12_shadow;
 387         int pad0;               /* Used for 8-byte alignment */
 388 };
 389
 390
 391 struct eeprom_fixup {
 392         char *name;
 393         unsigned char addr0;
 394         unsigned char addr1;
 395         unsigned char addr2;
 396         u16 newtable[32];       /* Max length below. */
 397 };
 398
 399
 400 /* 21142.c */
 401 extern u16 t21142_csr14[];
 402 void t21142_timer(unsigned long data);
 403 void t21142_start_nway(struct net_device *dev);
 404 void t21142_lnk_change(struct net_device *dev, int csr5);
 405
 406
 407 /* PNIC2.c */
 408 void pnic2_lnk_change(struct net_device *dev, int csr5);
 409 void pnic2_timer(unsigned long data);
 410 void pnic2_start_nway(struct net_device *dev);
 411 void pnic2_lnk_change(struct net_device *dev, int csr5);
 412
 413 /* eeprom.c */
 414 void tulip_parse_eeprom(struct net_device *dev);
 415 int tulip_read_eeprom(struct net_device *dev, int location, int addr_len);
 416
 417 /* interrupt.c */
 418 extern unsigned int tulip_max_interrupt_work;
 419 extern int tulip_rx_copybreak;
 420 irqreturn_t tulip_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
 421 int tulip_refill_rx(struct net_device *dev);
 422 #ifdef CONFIG_TULIP_NAPI
 423 int tulip_poll(struct net_device *dev, int *budget);
 424 #endif
 425
 426
 427 /* media.c */
 428 int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
 429 void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
 430 void tulip_select_media(struct net_device *dev, int startup);
 431 int tulip_check_duplex(struct net_device *dev);
 432 void tulip_find_mii (struct net_device *dev, int board_idx);
 433
 434 /* pnic.c */
 435 void pnic_do_nway(struct net_device *dev);
 436 void pnic_lnk_change(struct net_device *dev, int csr5);
 437 void pnic_timer(unsigned long data);
 438
 439 /* timer.c */
 440 void tulip_timer(unsigned long data);
 441 void mxic_timer(unsigned long data);
 442 void comet_timer(unsigned long data);
 443
 444 /* tulip_core.c */
 445 extern int tulip_debug;
 446 extern const char * const medianame[];
 447 extern const char tulip_media_cap[];
 448 extern struct tulip_chip_table tulip_tbl[];
 449 void oom_timer(unsigned long data);
 450 extern u8 t21040_csr13[];
 451
 452 static inline void tulip_start_rxtx(struct tulip_private *tp)
 453 {
 454         void __iomem *ioaddr = tp->base_addr;
 455         iowrite32(tp->csr6 | RxTx, ioaddr + CSR6);
 456         barrier();
 457         (void) ioread32(ioaddr + CSR6); /* mmio sync */
 458 }
 459
 460 static inline void tulip_stop_rxtx(struct tulip_private *tp)
 461 {
 462         void __iomem *ioaddr = tp->base_addr;
 463         u32 csr6 = ioread32(ioaddr + CSR6);
 464
 465         if (csr6 & RxTx) {
 466                 unsigned i=1300/10;
 467                 iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
 468                 barrier();
 469                 /* wait until in-flight frame completes.
 470                  * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
 471                  * Typically expect this loop to end in < 50 us on 100BT.
 472                  */
 473                 while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
 474                         udelay(10);
 475
 476                 if (!i)
 477                         printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed\n",
 478                                         pci_name(tp->pdev));
 479         }
 480 }
 481
 482 static inline void tulip_restart_rxtx(struct tulip_private *tp)
 483 {
 484         tulip_stop_rxtx(tp);
 485         udelay(5);
 486         tulip_start_rxtx(tp);
 487 }
 488
 489 #endif /* __NET_TULIP_H__ */