drivers/net/pasemi_mac.h

   1 /*
   2  * Copyright (C) 2006 PA Semi, Inc
   3  *
   4  * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
   5  * hardware register layouts.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  */
  20
  21 #ifndef PASEMI_MAC_H
  22 #define PASEMI_MAC_H
  23
  24 #include <linux/ethtool.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/phy.h>
  28
  29 struct pasemi_mac_txring {
  30         spinlock_t       lock;
  31         struct pas_dma_xct_descr        *desc;
  32         dma_addr_t       dma;
  33         unsigned int     size;
  34         unsigned int     next_to_use;
  35         unsigned int     next_to_clean;
  36         struct pasemi_mac_buffer *desc_info;
  37         char             irq_name[10];  /* "eth%d tx" */
  38 };
  39
  40 struct pasemi_mac_rxring {
  41         spinlock_t       lock;
  42         struct pas_dma_xct_descr        *desc;  /* RX channel descriptor ring */
  43         dma_addr_t       dma;
  44         u64             *buffers;       /* RX interface buffer ring */
  45         dma_addr_t       buf_dma;
  46         unsigned int     size;
  47         unsigned int     next_to_fill;
  48         unsigned int     next_to_clean;
  49         struct pasemi_mac_buffer *desc_info;
  50         char             irq_name[10];  /* "eth%d rx" */
  51 };
  52
  53 struct pasemi_mac {
  54         struct net_device *netdev;
  55         struct pci_dev *pdev;
  56         struct pci_dev *dma_pdev;
  57         struct pci_dev *iob_pdev;
  58         struct phy_device *phydev;
  59         struct net_device_stats stats;
  60
  61         /* Pointer to the cacheable per-channel status registers */
  62         u64     *rx_status;
  63         u64     *tx_status;
  64
  65         u8              type;
  66 #define MAC_TYPE_GMAC   1
  67 #define MAC_TYPE_XAUI   2
  68         u32     dma_txch;
  69         u32     dma_if;
  70         u32     dma_rxch;
  71
  72         u8              mac_addr[6];
  73
  74         struct timer_list       rxtimer;
  75
  76         struct pasemi_mac_txring *tx;
  77         struct pasemi_mac_rxring *rx;
  78         unsigned long   tx_irq;
  79         unsigned long   rx_irq;
  80         int     link;
  81         int     speed;
  82         int     duplex;
  83
  84         unsigned int    msg_enable;
  85         char    phy_id[BUS_ID_SIZE];
  86 };
  87
  88 /* Software status descriptor (desc_info) */
  89 struct pasemi_mac_buffer {
  90         struct sk_buff *skb;
  91         dma_addr_t      dma;
  92 };
  93
  94
  95 /* status register layout in IOB region, at 0xfb800000 */
  96 struct pasdma_status {
  97         u64 rx_sta[64];
  98         u64 tx_sta[20];
  99 };
 100
 101 /* descriptor structure */
 102 struct pas_dma_xct_descr {
 103         union {
 104                 u64     mactx;
 105                 u64     macrx;
 106         };
 107         union {
 108                 u64     ptr;
 109                 u64     rxb;
 110         };
 111 };
 112
 113 /* MAC CFG register offsets */
 114
 115 enum {
 116         PAS_MAC_CFG_PCFG = 0x80,
 117         PAS_MAC_CFG_TXP = 0x98,
 118         PAS_MAC_IPC_CHNL = 0x208,
 119 };
 120
 121 /* MAC CFG register fields */
 122 #define PAS_MAC_CFG_PCFG_PE             0x80000000
 123 #define PAS_MAC_CFG_PCFG_CE             0x40000000
 124 #define PAS_MAC_CFG_PCFG_BU             0x20000000
 125 #define PAS_MAC_CFG_PCFG_TT             0x10000000
 126 #define PAS_MAC_CFG_PCFG_TSR_M          0x0c000000
 127 #define PAS_MAC_CFG_PCFG_TSR_10M        0x00000000
 128 #define PAS_MAC_CFG_PCFG_TSR_100M       0x04000000
 129 #define PAS_MAC_CFG_PCFG_TSR_1G         0x08000000
 130 #define PAS_MAC_CFG_PCFG_TSR_10G        0x0c000000
 131 #define PAS_MAC_CFG_PCFG_T24            0x02000000
 132 #define PAS_MAC_CFG_PCFG_PR             0x01000000
 133 #define PAS_MAC_CFG_PCFG_CRO_M          0x00ff0000
 134 #define PAS_MAC_CFG_PCFG_CRO_S  16
 135 #define PAS_MAC_CFG_PCFG_IPO_M          0x0000ff00
 136 #define PAS_MAC_CFG_PCFG_IPO_S  8
 137 #define PAS_MAC_CFG_PCFG_S1             0x00000080
 138 #define PAS_MAC_CFG_PCFG_IO_M           0x00000060
 139 #define PAS_MAC_CFG_PCFG_IO_MAC         0x00000000
 140 #define PAS_MAC_CFG_PCFG_IO_OFF         0x00000020
 141 #define PAS_MAC_CFG_PCFG_IO_IND_ETH     0x00000040
 142 #define PAS_MAC_CFG_PCFG_IO_IND_IP      0x00000060
 143 #define PAS_MAC_CFG_PCFG_LP             0x00000010
 144 #define PAS_MAC_CFG_PCFG_TS             0x00000008
 145 #define PAS_MAC_CFG_PCFG_HD             0x00000004
 146 #define PAS_MAC_CFG_PCFG_SPD_M          0x00000003
 147 #define PAS_MAC_CFG_PCFG_SPD_10M        0x00000000
 148 #define PAS_MAC_CFG_PCFG_SPD_100M       0x00000001
 149 #define PAS_MAC_CFG_PCFG_SPD_1G         0x00000002
 150 #define PAS_MAC_CFG_PCFG_SPD_10G        0x00000003
 151 #define PAS_MAC_CFG_TXP_FCF             0x01000000
 152 #define PAS_MAC_CFG_TXP_FCE             0x00800000
 153 #define PAS_MAC_CFG_TXP_FC              0x00400000
 154 #define PAS_MAC_CFG_TXP_FPC_M           0x00300000
 155 #define PAS_MAC_CFG_TXP_FPC_S           20
 156 #define PAS_MAC_CFG_TXP_FPC(x)          (((x) << PAS_MAC_CFG_TXP_FPC_S) & \
 157                                          PAS_MAC_CFG_TXP_FPC_M)
 158 #define PAS_MAC_CFG_TXP_RT              0x00080000
 159 #define PAS_MAC_CFG_TXP_BL              0x00040000
 160 #define PAS_MAC_CFG_TXP_SL_M            0x00030000
 161 #define PAS_MAC_CFG_TXP_SL_S            16
 162 #define PAS_MAC_CFG_TXP_SL(x)           (((x) << PAS_MAC_CFG_TXP_SL_S) & \
 163                                          PAS_MAC_CFG_TXP_SL_M)
 164 #define PAS_MAC_CFG_TXP_COB_M           0x0000f000
 165 #define PAS_MAC_CFG_TXP_COB_S           12
 166 #define PAS_MAC_CFG_TXP_COB(x)          (((x) << PAS_MAC_CFG_TXP_COB_S) & \
 167                                          PAS_MAC_CFG_TXP_COB_M)
 168 #define PAS_MAC_CFG_TXP_TIFT_M          0x00000f00
 169 #define PAS_MAC_CFG_TXP_TIFT_S          8
 170 #define PAS_MAC_CFG_TXP_TIFT(x)         (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
 171                                          PAS_MAC_CFG_TXP_TIFT_M)
 172 #define PAS_MAC_CFG_TXP_TIFG_M          0x000000ff
 173 #define PAS_MAC_CFG_TXP_TIFG_S          0
 174 #define PAS_MAC_CFG_TXP_TIFG(x)         (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
 175                                          PAS_MAC_CFG_TXP_TIFG_M)
 176
 177 #define PAS_MAC_IPC_CHNL_DCHNO_M        0x003f0000
 178 #define PAS_MAC_IPC_CHNL_DCHNO_S        16
 179 #define PAS_MAC_IPC_CHNL_DCHNO(x)       (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
 180                                          PAS_MAC_IPC_CHNL_DCHNO_M)
 181 #define PAS_MAC_IPC_CHNL_BCH_M          0x0000003f
 182 #define PAS_MAC_IPC_CHNL_BCH_S          0
 183 #define PAS_MAC_IPC_CHNL_BCH(x)         (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
 184                                          PAS_MAC_IPC_CHNL_BCH_M)
 185
 186 /* All these registers live in the PCI configuration space for the DMA PCI
 187  * device. Use the normal PCI config access functions for them.
 188  */
 189 enum {
 190         PAS_DMA_COM_TXCMD = 0x100,      /* Transmit Command Register  */
 191         PAS_DMA_COM_TXSTA = 0x104,      /* Transmit Status Register   */
 192         PAS_DMA_COM_RXCMD = 0x108,      /* Receive Command Register   */
 193         PAS_DMA_COM_RXSTA = 0x10c,      /* Receive Status Register    */
 194 };
 195 #define PAS_DMA_COM_TXCMD_EN    0x00000001 /* enable */
 196 #define PAS_DMA_COM_TXSTA_ACT   0x00000001 /* active */
 197 #define PAS_DMA_COM_RXCMD_EN    0x00000001 /* enable */
 198 #define PAS_DMA_COM_RXSTA_ACT   0x00000001 /* active */
 199
 200
 201 /* Per-interface and per-channel registers */
 202 #define _PAS_DMA_RXINT_STRIDE           0x20
 203 #define PAS_DMA_RXINT_RCMDSTA(i)        (0x200+(i)*_PAS_DMA_RXINT_STRIDE)
 204 #define    PAS_DMA_RXINT_RCMDSTA_EN     0x00000001
 205 #define    PAS_DMA_RXINT_RCMDSTA_ST     0x00000002
 206 #define    PAS_DMA_RXINT_RCMDSTA_MBT    0x00000008
 207 #define    PAS_DMA_RXINT_RCMDSTA_MDR    0x00000010
 208 #define    PAS_DMA_RXINT_RCMDSTA_MOO    0x00000020
 209 #define    PAS_DMA_RXINT_RCMDSTA_MBP    0x00000040
 210 #define    PAS_DMA_RXINT_RCMDSTA_BT     0x00000800
 211 #define    PAS_DMA_RXINT_RCMDSTA_DR     0x00001000
 212 #define    PAS_DMA_RXINT_RCMDSTA_OO     0x00002000
 213 #define    PAS_DMA_RXINT_RCMDSTA_BP     0x00004000
 214 #define    PAS_DMA_RXINT_RCMDSTA_TB     0x00008000
 215 #define    PAS_DMA_RXINT_RCMDSTA_ACT    0x00010000
 216 #define    PAS_DMA_RXINT_RCMDSTA_DROPS_M        0xfffe0000
 217 #define    PAS_DMA_RXINT_RCMDSTA_DROPS_S        17
 218 #define PAS_DMA_RXINT_INCR(i)           (0x210+(i)*_PAS_DMA_RXINT_STRIDE)
 219 #define    PAS_DMA_RXINT_INCR_INCR_M    0x0000ffff
 220 #define    PAS_DMA_RXINT_INCR_INCR_S    0
 221 #define    PAS_DMA_RXINT_INCR_INCR(x)   ((x) & 0x0000ffff)
 222 #define PAS_DMA_RXINT_BASEL(i)          (0x218+(i)*_PAS_DMA_RXINT_STRIDE)
 223 #define    PAS_DMA_RXINT_BASEL_BRBL(x)  ((x) & ~0x3f)
 224 #define PAS_DMA_RXINT_BASEU(i)          (0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
 225 #define    PAS_DMA_RXINT_BASEU_BRBH(x)  ((x) & 0xfff)
 226 #define    PAS_DMA_RXINT_BASEU_SIZ_M    0x3fff0000      /* # of cache lines worth of buffer ring */
 227 #define    PAS_DMA_RXINT_BASEU_SIZ_S    16              /* 0 = 16K */
 228 #define    PAS_DMA_RXINT_BASEU_SIZ(x)   (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
 229                                          PAS_DMA_RXINT_BASEU_SIZ_M)
 230
 231
 232 #define _PAS_DMA_TXCHAN_STRIDE  0x20    /* Size per channel             */
 233 #define _PAS_DMA_TXCHAN_TCMDSTA 0x300   /* Command / Status             */
 234 #define _PAS_DMA_TXCHAN_CFG     0x304   /* Configuration                */
 235 #define _PAS_DMA_TXCHAN_DSCRBU  0x308   /* Descriptor BU Allocation     */
 236 #define _PAS_DMA_TXCHAN_INCR    0x310   /* Descriptor increment         */
 237 #define _PAS_DMA_TXCHAN_CNT     0x314   /* Descriptor count/offset      */
 238 #define _PAS_DMA_TXCHAN_BASEL   0x318   /* Descriptor ring base (low)   */
 239 #define _PAS_DMA_TXCHAN_BASEU   0x31c   /*                      (high)  */
 240 #define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
 241 #define    PAS_DMA_TXCHAN_TCMDSTA_EN    0x00000001      /* Enabled */
 242 #define    PAS_DMA_TXCHAN_TCMDSTA_ST    0x00000002      /* Stop interface */
 243 #define    PAS_DMA_TXCHAN_TCMDSTA_ACT   0x00010000      /* Active */
 244 #define PAS_DMA_TXCHAN_CFG(c)     (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
 245 #define    PAS_DMA_TXCHAN_CFG_TY_IFACE  0x00000000      /* Type = interface */
 246 #define    PAS_DMA_TXCHAN_CFG_TATTR_M   0x0000003c
 247 #define    PAS_DMA_TXCHAN_CFG_TATTR_S   2
 248 #define    PAS_DMA_TXCHAN_CFG_TATTR(x)  (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
 249                                          PAS_DMA_TXCHAN_CFG_TATTR_M)
 250 #define    PAS_DMA_TXCHAN_CFG_WT_M      0x000001c0
 251 #define    PAS_DMA_TXCHAN_CFG_WT_S      6
 252 #define    PAS_DMA_TXCHAN_CFG_WT(x)     (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
 253                                          PAS_DMA_TXCHAN_CFG_WT_M)
 254 #define    PAS_DMA_TXCHAN_CFG_CF        0x00001000      /* Clean first line */
 255 #define    PAS_DMA_TXCHAN_CFG_CL        0x00002000      /* Clean last line */
 256 #define    PAS_DMA_TXCHAN_CFG_UP        0x00004000      /* update tx descr when sent */
 257 #define PAS_DMA_TXCHAN_INCR(c)    (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
 258 #define PAS_DMA_TXCHAN_BASEL(c)   (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
 259 #define    PAS_DMA_TXCHAN_BASEL_BRBL_M  0xffffffc0
 260 #define    PAS_DMA_TXCHAN_BASEL_BRBL_S  0
 261 #define    PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
 262                                          PAS_DMA_TXCHAN_BASEL_BRBL_M)
 263 #define PAS_DMA_TXCHAN_BASEU(c)   (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
 264 #define    PAS_DMA_TXCHAN_BASEU_BRBH_M  0x00000fff
 265 #define    PAS_DMA_TXCHAN_BASEU_BRBH_S  0
 266 #define    PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
 267                                          PAS_DMA_TXCHAN_BASEU_BRBH_M)
 268 /* # of cache lines worth of buffer ring */
 269 #define    PAS_DMA_TXCHAN_BASEU_SIZ_M   0x3fff0000
 270 #define    PAS_DMA_TXCHAN_BASEU_SIZ_S   16              /* 0 = 16K */
 271 #define    PAS_DMA_TXCHAN_BASEU_SIZ(x)  (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
 272                                          PAS_DMA_TXCHAN_BASEU_SIZ_M)
 273
 274 #define _PAS_DMA_RXCHAN_STRIDE  0x20    /* Size per channel             */
 275 #define _PAS_DMA_RXCHAN_CCMDSTA 0x800   /* Command / Status             */
 276 #define _PAS_DMA_RXCHAN_CFG     0x804   /* Configuration                */
 277 #define _PAS_DMA_RXCHAN_INCR    0x810   /* Descriptor increment         */
 278 #define _PAS_DMA_RXCHAN_CNT     0x814   /* Descriptor count/offset      */
 279 #define _PAS_DMA_RXCHAN_BASEL   0x818   /* Descriptor ring base (low)   */
 280 #define _PAS_DMA_RXCHAN_BASEU   0x81c   /*                      (high)  */
 281 #define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
 282 #define    PAS_DMA_RXCHAN_CCMDSTA_EN    0x00000001      /* Enabled */
 283 #define    PAS_DMA_RXCHAN_CCMDSTA_ST    0x00000002      /* Stop interface */
 284 #define    PAS_DMA_RXCHAN_CCMDSTA_ACT   0x00010000      /* Active */
 285 #define    PAS_DMA_RXCHAN_CCMDSTA_DU    0x00020000
 286 #define PAS_DMA_RXCHAN_CFG(c)     (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
 287 #define    PAS_DMA_RXCHAN_CFG_HBU_M     0x00000380
 288 #define    PAS_DMA_RXCHAN_CFG_HBU_S     7
 289 #define    PAS_DMA_RXCHAN_CFG_HBU(x)    (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
 290                                          PAS_DMA_RXCHAN_CFG_HBU_M)
 291 #define PAS_DMA_RXCHAN_INCR(c)    (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
 292 #define PAS_DMA_RXCHAN_BASEL(c)   (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
 293 #define    PAS_DMA_RXCHAN_BASEL_BRBL_M  0xffffffc0
 294 #define    PAS_DMA_RXCHAN_BASEL_BRBL_S  0
 295 #define    PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
 296                                          PAS_DMA_RXCHAN_BASEL_BRBL_M)
 297 #define PAS_DMA_RXCHAN_BASEU(c)   (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
 298 #define    PAS_DMA_RXCHAN_BASEU_BRBH_M  0x00000fff
 299 #define    PAS_DMA_RXCHAN_BASEU_BRBH_S  0
 300 #define    PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
 301                                          PAS_DMA_RXCHAN_BASEU_BRBH_M)
 302 /* # of cache lines worth of buffer ring */
 303 #define    PAS_DMA_RXCHAN_BASEU_SIZ_M   0x3fff0000
 304 #define    PAS_DMA_RXCHAN_BASEU_SIZ_S   16              /* 0 = 16K */
 305 #define    PAS_DMA_RXCHAN_BASEU_SIZ(x)  (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
 306                                          PAS_DMA_RXCHAN_BASEU_SIZ_M)
 307
 308 #define    PAS_STATUS_PCNT_M            0x000000000000ffffull
 309 #define    PAS_STATUS_PCNT_S            0
 310 #define    PAS_STATUS_DCNT_M            0x00000000ffff0000ull
 311 #define    PAS_STATUS_DCNT_S            16
 312 #define    PAS_STATUS_BPCNT_M           0x0000ffff00000000ull
 313 #define    PAS_STATUS_BPCNT_S           32
 314 #define    PAS_STATUS_CAUSE_M           0xf000000000000000ull
 315 #define    PAS_STATUS_TIMER             0x1000000000000000ull
 316 #define    PAS_STATUS_ERROR             0x2000000000000000ull
 317 #define    PAS_STATUS_SOFT              0x4000000000000000ull
 318 #define    PAS_STATUS_INT               0x8000000000000000ull
 319
 320 #define PAS_IOB_DMA_RXCH_CFG(i)         (0x1100 + (i)*4)
 321 #define    PAS_IOB_DMA_RXCH_CFG_CNTTH_M         0x00000fff
 322 #define    PAS_IOB_DMA_RXCH_CFG_CNTTH_S         0
 323 #define    PAS_IOB_DMA_RXCH_CFG_CNTTH(x)        (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
 324                                                  PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
 325 #define PAS_IOB_DMA_TXCH_CFG(i)         (0x1200 + (i)*4)
 326 #define    PAS_IOB_DMA_TXCH_CFG_CNTTH_M         0x00000fff
 327 #define    PAS_IOB_DMA_TXCH_CFG_CNTTH_S         0
 328 #define    PAS_IOB_DMA_TXCH_CFG_CNTTH(x)        (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
 329                                                  PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
 330 #define PAS_IOB_DMA_RXCH_STAT(i)        (0x1300 + (i)*4)
 331 #define    PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000
 332 #define    PAS_IOB_DMA_RXCH_STAT_CNTDEL_M       0x00000fff
 333 #define    PAS_IOB_DMA_RXCH_STAT_CNTDEL_S       0
 334 #define    PAS_IOB_DMA_RXCH_STAT_CNTDEL(x)      (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
 335                                                  PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
 336 #define PAS_IOB_DMA_TXCH_STAT(i)        (0x1400 + (i)*4)
 337 #define    PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000
 338 #define    PAS_IOB_DMA_TXCH_STAT_CNTDEL_M       0x00000fff
 339 #define    PAS_IOB_DMA_TXCH_STAT_CNTDEL_S       0
 340 #define    PAS_IOB_DMA_TXCH_STAT_CNTDEL(x)      (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
 341                                                  PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
 342 #define PAS_IOB_DMA_RXCH_RESET(i)       (0x1500 + (i)*4)
 343 #define    PAS_IOB_DMA_RXCH_RESET_PCNT_M        0xffff0000
 344 #define    PAS_IOB_DMA_RXCH_RESET_PCNT_S        0
 345 #define    PAS_IOB_DMA_RXCH_RESET_PCNT(x)       (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
 346                                                  PAS_IOB_DMA_RXCH_RESET_PCNT_M)
 347 #define    PAS_IOB_DMA_RXCH_RESET_PCNTRST       0x00000020
 348 #define    PAS_IOB_DMA_RXCH_RESET_DCNTRST       0x00000010
 349 #define    PAS_IOB_DMA_RXCH_RESET_TINTC         0x00000008
 350 #define    PAS_IOB_DMA_RXCH_RESET_DINTC         0x00000004
 351 #define    PAS_IOB_DMA_RXCH_RESET_SINTC         0x00000002
 352 #define    PAS_IOB_DMA_RXCH_RESET_PINTC         0x00000001
 353 #define PAS_IOB_DMA_TXCH_RESET(i)       (0x1600 + (i)*4)
 354 #define    PAS_IOB_DMA_TXCH_RESET_PCNT_M        0xffff0000
 355 #define    PAS_IOB_DMA_TXCH_RESET_PCNT_S        0
 356 #define    PAS_IOB_DMA_TXCH_RESET_PCNT(x)       (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
 357                                                  PAS_IOB_DMA_TXCH_RESET_PCNT_M)
 358 #define    PAS_IOB_DMA_TXCH_RESET_PCNTRST       0x00000020
 359 #define    PAS_IOB_DMA_TXCH_RESET_DCNTRST       0x00000010
 360 #define    PAS_IOB_DMA_TXCH_RESET_TINTC         0x00000008
 361 #define    PAS_IOB_DMA_TXCH_RESET_DINTC         0x00000004
 362 #define    PAS_IOB_DMA_TXCH_RESET_SINTC         0x00000002
 363 #define    PAS_IOB_DMA_TXCH_RESET_PINTC         0x00000001
 364
 365 #define PAS_IOB_DMA_COM_TIMEOUTCFG              0x1700
 366 #define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M    0x00ffffff
 367 #define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S    0
 368 #define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x)   (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
 369                                                  PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)
 370
 371 /* Transmit descriptor fields */
 372 #define XCT_MACTX_T             0x8000000000000000ull
 373 #define XCT_MACTX_ST            0x4000000000000000ull
 374 #define XCT_MACTX_NORES         0x0000000000000000ull
 375 #define XCT_MACTX_8BRES         0x1000000000000000ull
 376 #define XCT_MACTX_24BRES        0x2000000000000000ull
 377 #define XCT_MACTX_40BRES        0x3000000000000000ull
 378 #define XCT_MACTX_I             0x0800000000000000ull
 379 #define XCT_MACTX_O             0x0400000000000000ull
 380 #define XCT_MACTX_E             0x0200000000000000ull
 381 #define XCT_MACTX_VLAN_M        0x0180000000000000ull
 382 #define XCT_MACTX_VLAN_NOP      0x0000000000000000ull
 383 #define XCT_MACTX_VLAN_REMOVE   0x0080000000000000ull
 384 #define XCT_MACTX_VLAN_INSERT   0x0100000000000000ull
 385 #define XCT_MACTX_VLAN_REPLACE  0x0180000000000000ull
 386 #define XCT_MACTX_CRC_M         0x0060000000000000ull
 387 #define XCT_MACTX_CRC_NOP       0x0000000000000000ull
 388 #define XCT_MACTX_CRC_INSERT    0x0020000000000000ull
 389 #define XCT_MACTX_CRC_PAD       0x0040000000000000ull
 390 #define XCT_MACTX_CRC_REPLACE   0x0060000000000000ull
 391 #define XCT_MACTX_SS            0x0010000000000000ull
 392 #define XCT_MACTX_LLEN_M        0x00007fff00000000ull
 393 #define XCT_MACTX_LLEN_S        32ull
 394 #define XCT_MACTX_LLEN(x)       ((((long)(x)) << XCT_MACTX_LLEN_S) & \
 395                                  XCT_MACTX_LLEN_M)
 396 #define XCT_MACTX_IPH_M         0x00000000f8000000ull
 397 #define XCT_MACTX_IPH_S         27ull
 398 #define XCT_MACTX_IPH(x)        ((((long)(x)) << XCT_MACTX_IPH_S) & \
 399                                  XCT_MACTX_IPH_M)
 400 #define XCT_MACTX_IPO_M         0x0000000007c00000ull
 401 #define XCT_MACTX_IPO_S         22ull
 402 #define XCT_MACTX_IPO(x)        ((((long)(x)) << XCT_MACTX_IPO_S) & \
 403                                  XCT_MACTX_IPO_M)
 404 #define XCT_MACTX_CSUM_M        0x0000000000000060ull
 405 #define XCT_MACTX_CSUM_NOP      0x0000000000000000ull
 406 #define XCT_MACTX_CSUM_TCP      0x0000000000000040ull
 407 #define XCT_MACTX_CSUM_UDP      0x0000000000000060ull
 408 #define XCT_MACTX_V6            0x0000000000000010ull
 409 #define XCT_MACTX_C             0x0000000000000004ull
 410 #define XCT_MACTX_AL2           0x0000000000000002ull
 411
 412 /* Receive descriptor fields */
 413 #define XCT_MACRX_T             0x8000000000000000ull
 414 #define XCT_MACRX_ST            0x4000000000000000ull
 415 #define XCT_MACRX_NORES         0x0000000000000000ull
 416 #define XCT_MACRX_8BRES         0x1000000000000000ull
 417 #define XCT_MACRX_24BRES        0x2000000000000000ull
 418 #define XCT_MACRX_40BRES        0x3000000000000000ull
 419 #define XCT_MACRX_O             0x0400000000000000ull
 420 #define XCT_MACRX_E             0x0200000000000000ull
 421 #define XCT_MACRX_FF            0x0100000000000000ull
 422 #define XCT_MACRX_PF            0x0080000000000000ull
 423 #define XCT_MACRX_OB            0x0040000000000000ull
 424 #define XCT_MACRX_OD            0x0020000000000000ull
 425 #define XCT_MACRX_FS            0x0010000000000000ull
 426 #define XCT_MACRX_NB_M          0x000fc00000000000ull
 427 #define XCT_MACRX_NB_S          46ULL
 428 #define XCT_MACRX_NB(x)         ((((long)(x)) << XCT_MACRX_NB_S) & \
 429                                  XCT_MACRX_NB_M)
 430 #define XCT_MACRX_LLEN_M        0x00003fff00000000ull
 431 #define XCT_MACRX_LLEN_S        32ULL
 432 #define XCT_MACRX_LLEN(x)       ((((long)(x)) << XCT_MACRX_LLEN_S) & \
 433                                  XCT_MACRX_LLEN_M)
 434 #define XCT_MACRX_CRC           0x0000000080000000ull
 435 #define XCT_MACRX_LEN_M         0x0000000060000000ull
 436 #define XCT_MACRX_LEN_TOOSHORT  0x0000000020000000ull
 437 #define XCT_MACRX_LEN_BELOWMIN  0x0000000040000000ull
 438 #define XCT_MACRX_LEN_TRUNC     0x0000000060000000ull
 439 #define XCT_MACRX_CAST_M        0x0000000018000000ull
 440 #define XCT_MACRX_CAST_UNI      0x0000000000000000ull
 441 #define XCT_MACRX_CAST_MULTI    0x0000000008000000ull
 442 #define XCT_MACRX_CAST_BROAD    0x0000000010000000ull
 443 #define XCT_MACRX_CAST_PAUSE    0x0000000018000000ull
 444 #define XCT_MACRX_VLC_M         0x0000000006000000ull
 445 #define XCT_MACRX_FM            0x0000000001000000ull
 446 #define XCT_MACRX_HTY_M         0x0000000000c00000ull
 447 #define XCT_MACRX_HTY_IPV4_OK   0x0000000000000000ull
 448 #define XCT_MACRX_HTY_IPV6      0x0000000000400000ull
 449 #define XCT_MACRX_HTY_IPV4_BAD  0x0000000000800000ull
 450 #define XCT_MACRX_HTY_NONIP     0x0000000000c00000ull
 451 #define XCT_MACRX_IPP_M         0x00000000003f0000ull
 452 #define XCT_MACRX_IPP_S         16
 453 #define XCT_MACRX_CSUM_M        0x000000000000ffffull
 454 #define XCT_MACRX_CSUM_S        0
 455
 456 #define XCT_PTR_T               0x8000000000000000ull
 457 #define XCT_PTR_LEN_M           0x7ffff00000000000ull
 458 #define XCT_PTR_LEN_S           44
 459 #define XCT_PTR_LEN(x)          ((((long)(x)) << XCT_PTR_LEN_S) & \
 460                                  XCT_PTR_LEN_M)
 461 #define XCT_PTR_ADDR_M          0x00000fffffffffffull
 462 #define XCT_PTR_ADDR_S          0
 463 #define XCT_PTR_ADDR(x)         ((((long)(x)) << XCT_PTR_ADDR_S) & \
 464                                  XCT_PTR_ADDR_M)
 465
 466 /* Receive interface buffer fields */
 467 #define XCT_RXB_LEN_M           0x0ffff00000000000ull
 468 #define XCT_RXB_LEN_S           44
 469 #define XCT_RXB_LEN(x)          ((((long)(x)) << XCT_PTR_LEN_S) & XCT_PTR_LEN_M)
 470 #define XCT_RXB_ADDR_M          0x00000fffffffffffull
 471 #define XCT_RXB_ADDR_S          0
 472 #define XCT_RXB_ADDR(x)         ((((long)(x)) << XCT_PTR_ADDR_S) & XCT_PTR_ADDR_M)
 473
 474
 475 #endif /* PASEMI_MAC_H */