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[PATCH] Add ->splice_read/splice_write to def_blk_fops
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / serial / serial_txx9.c
blob3bdee64d1a997101f12f49f9f7c509c25694cbd8
1 /*
2 * drivers/serial/serial_txx9.c
3 *
4 * Derived from many drivers using generic_serial interface,
5 * especially serial_tx3912.c by Steven J. Hill and r39xx_serial.c
6 * (was in Linux/VR tree) by Jim Pick.
7 *
8 * Copyright (C) 1999 Harald Koerfgen
9 * Copyright (C) 2000 Jim Pick <jim@jimpick.com>
10 * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
11 * Copyright (C) 2000-2002 Toshiba Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
17 * Serial driver for TX3927/TX4927/TX4925/TX4938 internal SIO controller
18 *
19 * Revision History:
20 * 0.30 Initial revision. (Renamed from serial_txx927.c)
21 * 0.31 Use save_flags instead of local_irq_save.
22 * 0.32 Support SCLK.
23 * 0.33 Switch TXX9_TTY_NAME by CONFIG_SERIAL_TXX9_STDSERIAL.
24 * Support TIOCSERGETLSR.
25 * 0.34 Support slow baudrate.
26 * 0.40 Merge codes from mainstream kernel (2.4.22).
27 * 0.41 Fix console checking in rs_shutdown_port().
28 * Disable flow-control in serial_console_write().
29 * 0.42 Fix minor compiler warning.
30 * 1.00 Kernel 2.6. Converted to new serial core (based on 8250.c).
31 * 1.01 Set fifosize to make tx_empry called properly.
32 * Use standard uart_get_divisor.
33 * 1.02 Cleanup. (import 8250.c changes)
34 * 1.03 Fix low-latency mode. (import 8250.c changes)
35 * 1.04 Remove usage of deprecated functions, cleanup.
36 * 1.05 More strict check in verify_port. Cleanup.
37 * 1.06 Do not insert a char caused previous overrun.
38 * Fix some spin_locks.
39 * Do not call uart_add_one_port for absent ports.
40 */
41 #include <linux/config.h>
42
43 #if defined(CONFIG_SERIAL_TXX9_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
44 #define SUPPORT_SYSRQ
45 #endif
46
47 #include <linux/module.h>
48 #include <linux/ioport.h>
49 #include <linux/init.h>
50 #include <linux/console.h>
51 #include <linux/sysrq.h>
52 #include <linux/delay.h>
53 #include <linux/device.h>
54 #include <linux/pci.h>
55 #include <linux/tty.h>
56 #include <linux/tty_flip.h>
57 #include <linux/serial_core.h>
58 #include <linux/serial.h>
59 #include <linux/mutex.h>
60
61 #include <asm/io.h>
62 #include <asm/irq.h>
63
64 static char *serial_version = "1.06";
65 static char *serial_name = "TX39/49 Serial driver";
66
67 #define PASS_LIMIT 256
68
69 #if !defined(CONFIG_SERIAL_TXX9_STDSERIAL)
70 /* "ttyS" is used for standard serial driver */
71 #define TXX9_TTY_NAME "ttyTX"
72 #define TXX9_TTY_DEVFS_NAME "tttx/"
73 #define TXX9_TTY_MINOR_START (64 + 64) /* ttyTX0(128), ttyTX1(129) */
74 #else
75 /* acts like standard serial driver */
76 #define TXX9_TTY_NAME "ttyS"
77 #define TXX9_TTY_DEVFS_NAME "tts/"
78 #define TXX9_TTY_MINOR_START 64
79 #endif
80 #define TXX9_TTY_MAJOR TTY_MAJOR
81
82 /* flag aliases */
83 #define UPF_TXX9_HAVE_CTS_LINE UPF_BUGGY_UART
84 #define UPF_TXX9_USE_SCLK UPF_MAGIC_MULTIPLIER
85
86 #ifdef CONFIG_PCI
87 /* support for Toshiba TC86C001 SIO */
88 #define ENABLE_SERIAL_TXX9_PCI
89 #endif
90
91 /*
92 * Number of serial ports
93 */
94 #ifdef ENABLE_SERIAL_TXX9_PCI
95 #define NR_PCI_BOARDS 4
96 #define UART_NR (4 + NR_PCI_BOARDS)
97 #else
98 #define UART_NR 4
99 #endif
100
101 #define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
102
103 struct uart_txx9_port {
104 struct uart_port port;
105
106 /*
107 * We provide a per-port pm hook.
108 */
109 void (*pm)(struct uart_port *port,
110 unsigned int state, unsigned int old);
111 };
112
113 #define TXX9_REGION_SIZE 0x24
114
115 /* TXX9 Serial Registers */
116 #define TXX9_SILCR 0x00
117 #define TXX9_SIDICR 0x04
118 #define TXX9_SIDISR 0x08
119 #define TXX9_SICISR 0x0c
120 #define TXX9_SIFCR 0x10
121 #define TXX9_SIFLCR 0x14
122 #define TXX9_SIBGR 0x18
123 #define TXX9_SITFIFO 0x1c
124 #define TXX9_SIRFIFO 0x20
125
126 /* SILCR : Line Control */
127 #define TXX9_SILCR_SCS_MASK 0x00000060
128 #define TXX9_SILCR_SCS_IMCLK 0x00000000
129 #define TXX9_SILCR_SCS_IMCLK_BG 0x00000020
130 #define TXX9_SILCR_SCS_SCLK 0x00000040
131 #define TXX9_SILCR_SCS_SCLK_BG 0x00000060
132 #define TXX9_SILCR_UEPS 0x00000010
133 #define TXX9_SILCR_UPEN 0x00000008
134 #define TXX9_SILCR_USBL_MASK 0x00000004
135 #define TXX9_SILCR_USBL_1BIT 0x00000000
136 #define TXX9_SILCR_USBL_2BIT 0x00000004
137 #define TXX9_SILCR_UMODE_MASK 0x00000003
138 #define TXX9_SILCR_UMODE_8BIT 0x00000000
139 #define TXX9_SILCR_UMODE_7BIT 0x00000001
140
141 /* SIDICR : DMA/Int. Control */
142 #define TXX9_SIDICR_TDE 0x00008000
143 #define TXX9_SIDICR_RDE 0x00004000
144 #define TXX9_SIDICR_TIE 0x00002000
145 #define TXX9_SIDICR_RIE 0x00001000
146 #define TXX9_SIDICR_SPIE 0x00000800
147 #define TXX9_SIDICR_CTSAC 0x00000600
148 #define TXX9_SIDICR_STIE_MASK 0x0000003f
149 #define TXX9_SIDICR_STIE_OERS 0x00000020
150 #define TXX9_SIDICR_STIE_CTSS 0x00000010
151 #define TXX9_SIDICR_STIE_RBRKD 0x00000008
152 #define TXX9_SIDICR_STIE_TRDY 0x00000004
153 #define TXX9_SIDICR_STIE_TXALS 0x00000002
154 #define TXX9_SIDICR_STIE_UBRKD 0x00000001
155
156 /* SIDISR : DMA/Int. Status */
157 #define TXX9_SIDISR_UBRK 0x00008000
158 #define TXX9_SIDISR_UVALID 0x00004000
159 #define TXX9_SIDISR_UFER 0x00002000
160 #define TXX9_SIDISR_UPER 0x00001000
161 #define TXX9_SIDISR_UOER 0x00000800
162 #define TXX9_SIDISR_ERI 0x00000400
163 #define TXX9_SIDISR_TOUT 0x00000200
164 #define TXX9_SIDISR_TDIS 0x00000100
165 #define TXX9_SIDISR_RDIS 0x00000080
166 #define TXX9_SIDISR_STIS 0x00000040
167 #define TXX9_SIDISR_RFDN_MASK 0x0000001f
168
169 /* SICISR : Change Int. Status */
170 #define TXX9_SICISR_OERS 0x00000020
171 #define TXX9_SICISR_CTSS 0x00000010
172 #define TXX9_SICISR_RBRKD 0x00000008
173 #define TXX9_SICISR_TRDY 0x00000004
174 #define TXX9_SICISR_TXALS 0x00000002
175 #define TXX9_SICISR_UBRKD 0x00000001
176
177 /* SIFCR : FIFO Control */
178 #define TXX9_SIFCR_SWRST 0x00008000
179 #define TXX9_SIFCR_RDIL_MASK 0x00000180
180 #define TXX9_SIFCR_RDIL_1 0x00000000
181 #define TXX9_SIFCR_RDIL_4 0x00000080
182 #define TXX9_SIFCR_RDIL_8 0x00000100
183 #define TXX9_SIFCR_RDIL_12 0x00000180
184 #define TXX9_SIFCR_RDIL_MAX 0x00000180
185 #define TXX9_SIFCR_TDIL_MASK 0x00000018
186 #define TXX9_SIFCR_TDIL_MASK 0x00000018
187 #define TXX9_SIFCR_TDIL_1 0x00000000
188 #define TXX9_SIFCR_TDIL_4 0x00000001
189 #define TXX9_SIFCR_TDIL_8 0x00000010
190 #define TXX9_SIFCR_TDIL_MAX 0x00000010
191 #define TXX9_SIFCR_TFRST 0x00000004
192 #define TXX9_SIFCR_RFRST 0x00000002
193 #define TXX9_SIFCR_FRSTE 0x00000001
194 #define TXX9_SIO_TX_FIFO 8
195 #define TXX9_SIO_RX_FIFO 16
196
197 /* SIFLCR : Flow Control */
198 #define TXX9_SIFLCR_RCS 0x00001000
199 #define TXX9_SIFLCR_TES 0x00000800
200 #define TXX9_SIFLCR_RTSSC 0x00000200
201 #define TXX9_SIFLCR_RSDE 0x00000100
202 #define TXX9_SIFLCR_TSDE 0x00000080
203 #define TXX9_SIFLCR_RTSTL_MASK 0x0000001e
204 #define TXX9_SIFLCR_RTSTL_MAX 0x0000001e
205 #define TXX9_SIFLCR_TBRK 0x00000001
206
207 /* SIBGR : Baudrate Control */
208 #define TXX9_SIBGR_BCLK_MASK 0x00000300
209 #define TXX9_SIBGR_BCLK_T0 0x00000000
210 #define TXX9_SIBGR_BCLK_T2 0x00000100
211 #define TXX9_SIBGR_BCLK_T4 0x00000200
212 #define TXX9_SIBGR_BCLK_T6 0x00000300
213 #define TXX9_SIBGR_BRD_MASK 0x000000ff
214
215 static inline unsigned int sio_in(struct uart_txx9_port *up, int offset)
216 {
217 switch (up->port.iotype) {
218 default:
219 return __raw_readl(up->port.membase + offset);
220 case UPIO_PORT:
221 return inl(up->port.iobase + offset);
222 }
223 }
224
225 static inline void
226 sio_out(struct uart_txx9_port *up, int offset, int value)
227 {
228 switch (up->port.iotype) {
229 default:
230 __raw_writel(value, up->port.membase + offset);
231 break;
232 case UPIO_PORT:
233 outl(value, up->port.iobase + offset);
234 break;
235 }
236 }
237
238 static inline void
239 sio_mask(struct uart_txx9_port *up, int offset, unsigned int value)
240 {
241 sio_out(up, offset, sio_in(up, offset) & ~value);
242 }
243 static inline void
244 sio_set(struct uart_txx9_port *up, int offset, unsigned int value)
245 {
246 sio_out(up, offset, sio_in(up, offset) | value);
247 }
248
249 static inline void
250 sio_quot_set(struct uart_txx9_port *up, int quot)
251 {
252 quot >>= 1;
253 if (quot < 256)
254 sio_out(up, TXX9_SIBGR, quot | TXX9_SIBGR_BCLK_T0);
255 else if (quot < (256 << 2))
256 sio_out(up, TXX9_SIBGR, (quot >> 2) | TXX9_SIBGR_BCLK_T2);
257 else if (quot < (256 << 4))
258 sio_out(up, TXX9_SIBGR, (quot >> 4) | TXX9_SIBGR_BCLK_T4);
259 else if (quot < (256 << 6))
260 sio_out(up, TXX9_SIBGR, (quot >> 6) | TXX9_SIBGR_BCLK_T6);
261 else
262 sio_out(up, TXX9_SIBGR, 0xff | TXX9_SIBGR_BCLK_T6);
263 }
264
265 static void serial_txx9_stop_tx(struct uart_port *port)
266 {
267 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
268 sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
269 }
270
271 static void serial_txx9_start_tx(struct uart_port *port)
272 {
273 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
274 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
275 }
276
277 static void serial_txx9_stop_rx(struct uart_port *port)
278 {
279 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
280 up->port.read_status_mask &= ~TXX9_SIDISR_RDIS;
281 }
282
283 static void serial_txx9_enable_ms(struct uart_port *port)
284 {
285 /* TXX9-SIO can not control DTR... */
286 }
287
288 static inline void
289 receive_chars(struct uart_txx9_port *up, unsigned int *status, struct pt_regs *regs)
290 {
291 struct tty_struct *tty = up->port.info->tty;
292 unsigned char ch;
293 unsigned int disr = *status;
294 int max_count = 256;
295 char flag;
296 unsigned int next_ignore_status_mask;
297
298 do {
299 ch = sio_in(up, TXX9_SIRFIFO);
300 flag = TTY_NORMAL;
301 up->port.icount.rx++;
302
303 /* mask out RFDN_MASK bit added by previous overrun */
304 next_ignore_status_mask =
305 up->port.ignore_status_mask & ~TXX9_SIDISR_RFDN_MASK;
306 if (unlikely(disr & (TXX9_SIDISR_UBRK | TXX9_SIDISR_UPER |
307 TXX9_SIDISR_UFER | TXX9_SIDISR_UOER))) {
308 /*
309 * For statistics only
310 */
311 if (disr & TXX9_SIDISR_UBRK) {
312 disr &= ~(TXX9_SIDISR_UFER | TXX9_SIDISR_UPER);
313 up->port.icount.brk++;
314 /*
315 * We do the SysRQ and SAK checking
316 * here because otherwise the break
317 * may get masked by ignore_status_mask
318 * or read_status_mask.
319 */
320 if (uart_handle_break(&up->port))
321 goto ignore_char;
322 } else if (disr & TXX9_SIDISR_UPER)
323 up->port.icount.parity++;
324 else if (disr & TXX9_SIDISR_UFER)
325 up->port.icount.frame++;
326 if (disr & TXX9_SIDISR_UOER) {
327 up->port.icount.overrun++;
328 /*
329 * The receiver read buffer still hold
330 * a char which caused overrun.
331 * Ignore next char by adding RFDN_MASK
332 * to ignore_status_mask temporarily.
333 */
334 next_ignore_status_mask |=
335 TXX9_SIDISR_RFDN_MASK;
336 }
337
338 /*
339 * Mask off conditions which should be ingored.
340 */
341 disr &= up->port.read_status_mask;
342
343 if (disr & TXX9_SIDISR_UBRK) {
344 flag = TTY_BREAK;
345 } else if (disr & TXX9_SIDISR_UPER)
346 flag = TTY_PARITY;
347 else if (disr & TXX9_SIDISR_UFER)
348 flag = TTY_FRAME;
349 }
350 if (uart_handle_sysrq_char(&up->port, ch, regs))
351 goto ignore_char;
352
353 uart_insert_char(&up->port, disr, TXX9_SIDISR_UOER, ch, flag);
354
355 ignore_char:
356 up->port.ignore_status_mask = next_ignore_status_mask;
357 disr = sio_in(up, TXX9_SIDISR);
358 } while (!(disr & TXX9_SIDISR_UVALID) && (max_count-- > 0));
359 spin_unlock(&up->port.lock);
360 tty_flip_buffer_push(tty);
361 spin_lock(&up->port.lock);
362 *status = disr;
363 }
364
365 static inline void transmit_chars(struct uart_txx9_port *up)
366 {
367 struct circ_buf *xmit = &up->port.info->xmit;
368 int count;
369
370 if (up->port.x_char) {
371 sio_out(up, TXX9_SITFIFO, up->port.x_char);
372 up->port.icount.tx++;
373 up->port.x_char = 0;
374 return;
375 }
376 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
377 serial_txx9_stop_tx(&up->port);
378 return;
379 }
380
381 count = TXX9_SIO_TX_FIFO;
382 do {
383 sio_out(up, TXX9_SITFIFO, xmit->buf[xmit->tail]);
384 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
385 up->port.icount.tx++;
386 if (uart_circ_empty(xmit))
387 break;
388 } while (--count > 0);
389
390 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
391 uart_write_wakeup(&up->port);
392
393 if (uart_circ_empty(xmit))
394 serial_txx9_stop_tx(&up->port);
395 }
396
397 static irqreturn_t serial_txx9_interrupt(int irq, void *dev_id, struct pt_regs *regs)
398 {
399 int pass_counter = 0;
400 struct uart_txx9_port *up = dev_id;
401 unsigned int status;
402
403 while (1) {
404 spin_lock(&up->port.lock);
405 status = sio_in(up, TXX9_SIDISR);
406 if (!(sio_in(up, TXX9_SIDICR) & TXX9_SIDICR_TIE))
407 status &= ~TXX9_SIDISR_TDIS;
408 if (!(status & (TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
409 TXX9_SIDISR_TOUT))) {
410 spin_unlock(&up->port.lock);
411 break;
412 }
413
414 if (status & TXX9_SIDISR_RDIS)
415 receive_chars(up, &status, regs);
416 if (status & TXX9_SIDISR_TDIS)
417 transmit_chars(up);
418 /* Clear TX/RX Int. Status */
419 sio_mask(up, TXX9_SIDISR,
420 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
421 TXX9_SIDISR_TOUT);
422 spin_unlock(&up->port.lock);
423
424 if (pass_counter++ > PASS_LIMIT)
425 break;
426 }
427
428 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
429 }
430
431 static unsigned int serial_txx9_tx_empty(struct uart_port *port)
432 {
433 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
434 unsigned long flags;
435 unsigned int ret;
436
437 spin_lock_irqsave(&up->port.lock, flags);
438 ret = (sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS) ? TIOCSER_TEMT : 0;
439 spin_unlock_irqrestore(&up->port.lock, flags);
440
441 return ret;
442 }
443
444 static unsigned int serial_txx9_get_mctrl(struct uart_port *port)
445 {
446 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
447 unsigned int ret;
448
449 ret = ((sio_in(up, TXX9_SIFLCR) & TXX9_SIFLCR_RTSSC) ? 0 : TIOCM_RTS)
450 | ((sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS) ? 0 : TIOCM_CTS);
451
452 return ret;
453 }
454
455 static void serial_txx9_set_mctrl(struct uart_port *port, unsigned int mctrl)
456 {
457 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
458
459 if (mctrl & TIOCM_RTS)
460 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
461 else
462 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
463 }
464
465 static void serial_txx9_break_ctl(struct uart_port *port, int break_state)
466 {
467 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
468 unsigned long flags;
469
470 spin_lock_irqsave(&up->port.lock, flags);
471 if (break_state == -1)
472 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
473 else
474 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
475 spin_unlock_irqrestore(&up->port.lock, flags);
476 }
477
478 static int serial_txx9_startup(struct uart_port *port)
479 {
480 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
481 unsigned long flags;
482 int retval;
483
484 /*
485 * Clear the FIFO buffers and disable them.
486 * (they will be reenabled in set_termios())
487 */
488 sio_set(up, TXX9_SIFCR,
489 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
490 /* clear reset */
491 sio_mask(up, TXX9_SIFCR,
492 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
493 sio_out(up, TXX9_SIDICR, 0);
494
495 /*
496 * Clear the interrupt registers.
497 */
498 sio_out(up, TXX9_SIDISR, 0);
499
500 retval = request_irq(up->port.irq, serial_txx9_interrupt,
501 SA_SHIRQ, "serial_txx9", up);
502 if (retval)
503 return retval;
504
505 /*
506 * Now, initialize the UART
507 */
508 spin_lock_irqsave(&up->port.lock, flags);
509 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
510 spin_unlock_irqrestore(&up->port.lock, flags);
511
512 /* Enable RX/TX */
513 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
514
515 /*
516 * Finally, enable interrupts.
517 */
518 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_RIE);
519
520 return 0;
521 }
522
523 static void serial_txx9_shutdown(struct uart_port *port)
524 {
525 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
526 unsigned long flags;
527
528 /*
529 * Disable interrupts from this port
530 */
531 sio_out(up, TXX9_SIDICR, 0); /* disable all intrs */
532
533 spin_lock_irqsave(&up->port.lock, flags);
534 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
535 spin_unlock_irqrestore(&up->port.lock, flags);
536
537 /*
538 * Disable break condition
539 */
540 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
541
542 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
543 if (up->port.cons && up->port.line == up->port.cons->index) {
544 free_irq(up->port.irq, up);
545 return;
546 }
547 #endif
548 /* reset FIFOs */
549 sio_set(up, TXX9_SIFCR,
550 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
551 /* clear reset */
552 sio_mask(up, TXX9_SIFCR,
553 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
554
555 /* Disable RX/TX */
556 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
557
558 free_irq(up->port.irq, up);
559 }
560
561 static void
562 serial_txx9_set_termios(struct uart_port *port, struct termios *termios,
563 struct termios *old)
564 {
565 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
566 unsigned int cval, fcr = 0;
567 unsigned long flags;
568 unsigned int baud, quot;
569
570 cval = sio_in(up, TXX9_SILCR);
571 /* byte size and parity */
572 cval &= ~TXX9_SILCR_UMODE_MASK;
573 switch (termios->c_cflag & CSIZE) {
574 case CS7:
575 cval |= TXX9_SILCR_UMODE_7BIT;
576 break;
577 default:
578 case CS5: /* not supported */
579 case CS6: /* not supported */
580 case CS8:
581 cval |= TXX9_SILCR_UMODE_8BIT;
582 break;
583 }
584
585 cval &= ~TXX9_SILCR_USBL_MASK;
586 if (termios->c_cflag & CSTOPB)
587 cval |= TXX9_SILCR_USBL_2BIT;
588 else
589 cval |= TXX9_SILCR_USBL_1BIT;
590 cval &= ~(TXX9_SILCR_UPEN | TXX9_SILCR_UEPS);
591 if (termios->c_cflag & PARENB)
592 cval |= TXX9_SILCR_UPEN;
593 if (!(termios->c_cflag & PARODD))
594 cval |= TXX9_SILCR_UEPS;
595
596 /*
597 * Ask the core to calculate the divisor for us.
598 */
599 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16/2);
600 quot = uart_get_divisor(port, baud);
601
602 /* Set up FIFOs */
603 /* TX Int by FIFO Empty, RX Int by Receiving 1 char. */
604 fcr = TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1;
605
606 /*
607 * Ok, we're now changing the port state. Do it with
608 * interrupts disabled.
609 */
610 spin_lock_irqsave(&up->port.lock, flags);
611
612 /*
613 * Update the per-port timeout.
614 */
615 uart_update_timeout(port, termios->c_cflag, baud);
616
617 up->port.read_status_mask = TXX9_SIDISR_UOER |
618 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS;
619 if (termios->c_iflag & INPCK)
620 up->port.read_status_mask |= TXX9_SIDISR_UFER | TXX9_SIDISR_UPER;
621 if (termios->c_iflag & (BRKINT | PARMRK))
622 up->port.read_status_mask |= TXX9_SIDISR_UBRK;
623
624 /*
625 * Characteres to ignore
626 */
627 up->port.ignore_status_mask = 0;
628 if (termios->c_iflag & IGNPAR)
629 up->port.ignore_status_mask |= TXX9_SIDISR_UPER | TXX9_SIDISR_UFER;
630 if (termios->c_iflag & IGNBRK) {
631 up->port.ignore_status_mask |= TXX9_SIDISR_UBRK;
632 /*
633 * If we're ignoring parity and break indicators,
634 * ignore overruns too (for real raw support).
635 */
636 if (termios->c_iflag & IGNPAR)
637 up->port.ignore_status_mask |= TXX9_SIDISR_UOER;
638 }
639
640 /*
641 * ignore all characters if CREAD is not set
642 */
643 if ((termios->c_cflag & CREAD) == 0)
644 up->port.ignore_status_mask |= TXX9_SIDISR_RDIS;
645
646 /* CTS flow control flag */
647 if ((termios->c_cflag & CRTSCTS) &&
648 (up->port.flags & UPF_TXX9_HAVE_CTS_LINE)) {
649 sio_set(up, TXX9_SIFLCR,
650 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
651 } else {
652 sio_mask(up, TXX9_SIFLCR,
653 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
654 }
655
656 sio_out(up, TXX9_SILCR, cval);
657 sio_quot_set(up, quot);
658 sio_out(up, TXX9_SIFCR, fcr);
659
660 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
661 spin_unlock_irqrestore(&up->port.lock, flags);
662 }
663
664 static void
665 serial_txx9_pm(struct uart_port *port, unsigned int state,
666 unsigned int oldstate)
667 {
668 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
669 if (up->pm)
670 up->pm(port, state, oldstate);
671 }
672
673 static int serial_txx9_request_resource(struct uart_txx9_port *up)
674 {
675 unsigned int size = TXX9_REGION_SIZE;
676 int ret = 0;
677
678 switch (up->port.iotype) {
679 default:
680 if (!up->port.mapbase)
681 break;
682
683 if (!request_mem_region(up->port.mapbase, size, "serial_txx9")) {
684 ret = -EBUSY;
685 break;
686 }
687
688 if (up->port.flags & UPF_IOREMAP) {
689 up->port.membase = ioremap(up->port.mapbase, size);
690 if (!up->port.membase) {
691 release_mem_region(up->port.mapbase, size);
692 ret = -ENOMEM;
693 }
694 }
695 break;
696
697 case UPIO_PORT:
698 if (!request_region(up->port.iobase, size, "serial_txx9"))
699 ret = -EBUSY;
700 break;
701 }
702 return ret;
703 }
704
705 static void serial_txx9_release_resource(struct uart_txx9_port *up)
706 {
707 unsigned int size = TXX9_REGION_SIZE;
708
709 switch (up->port.iotype) {
710 default:
711 if (!up->port.mapbase)
712 break;
713
714 if (up->port.flags & UPF_IOREMAP) {
715 iounmap(up->port.membase);
716 up->port.membase = NULL;
717 }
718
719 release_mem_region(up->port.mapbase, size);
720 break;
721
722 case UPIO_PORT:
723 release_region(up->port.iobase, size);
724 break;
725 }
726 }
727
728 static void serial_txx9_release_port(struct uart_port *port)
729 {
730 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
731 serial_txx9_release_resource(up);
732 }
733
734 static int serial_txx9_request_port(struct uart_port *port)
735 {
736 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
737 return serial_txx9_request_resource(up);
738 }
739
740 static void serial_txx9_config_port(struct uart_port *port, int uflags)
741 {
742 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
743 unsigned long flags;
744 int ret;
745
746 /*
747 * Find the region that we can probe for. This in turn
748 * tells us whether we can probe for the type of port.
749 */
750 ret = serial_txx9_request_resource(up);
751 if (ret < 0)
752 return;
753 port->type = PORT_TXX9;
754 up->port.fifosize = TXX9_SIO_TX_FIFO;
755
756 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
757 if (up->port.line == up->port.cons->index)
758 return;
759 #endif
760 spin_lock_irqsave(&up->port.lock, flags);
761 /*
762 * Reset the UART.
763 */
764 sio_out(up, TXX9_SIFCR, TXX9_SIFCR_SWRST);
765 #ifdef CONFIG_CPU_TX49XX
766 /* TX4925 BUG WORKAROUND. Accessing SIOC register
767 * immediately after soft reset causes bus error. */
768 iob();
769 udelay(1);
770 #endif
771 while (sio_in(up, TXX9_SIFCR) & TXX9_SIFCR_SWRST)
772 ;
773 /* TX Int by FIFO Empty, RX Int by Receiving 1 char. */
774 sio_set(up, TXX9_SIFCR,
775 TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1);
776 /* initial settings */
777 sio_out(up, TXX9_SILCR,
778 TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT |
779 ((up->port.flags & UPF_TXX9_USE_SCLK) ?
780 TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG));
781 sio_quot_set(up, uart_get_divisor(port, 9600));
782 sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX /* 15 */);
783 spin_unlock_irqrestore(&up->port.lock, flags);
784 }
785
786 static int
787 serial_txx9_verify_port(struct uart_port *port, struct serial_struct *ser)
788 {
789 unsigned long new_port = ser->port;
790 if (HIGH_BITS_OFFSET)
791 new_port += (unsigned long)ser->port_high << HIGH_BITS_OFFSET;
792 if (ser->type != port->type ||
793 ser->irq != port->irq ||
794 ser->io_type != port->iotype ||
795 new_port != port->iobase ||
796 (unsigned long)ser->iomem_base != port->mapbase)
797 return -EINVAL;
798 return 0;
799 }
800
801 static const char *
802 serial_txx9_type(struct uart_port *port)
803 {
804 return "txx9";
805 }
806
807 static struct uart_ops serial_txx9_pops = {
808 .tx_empty = serial_txx9_tx_empty,
809 .set_mctrl = serial_txx9_set_mctrl,
810 .get_mctrl = serial_txx9_get_mctrl,
811 .stop_tx = serial_txx9_stop_tx,
812 .start_tx = serial_txx9_start_tx,
813 .stop_rx = serial_txx9_stop_rx,
814 .enable_ms = serial_txx9_enable_ms,
815 .break_ctl = serial_txx9_break_ctl,
816 .startup = serial_txx9_startup,
817 .shutdown = serial_txx9_shutdown,
818 .set_termios = serial_txx9_set_termios,
819 .pm = serial_txx9_pm,
820 .type = serial_txx9_type,
821 .release_port = serial_txx9_release_port,
822 .request_port = serial_txx9_request_port,
823 .config_port = serial_txx9_config_port,
824 .verify_port = serial_txx9_verify_port,
825 };
826
827 static struct uart_txx9_port serial_txx9_ports[UART_NR];
828
829 static void __init serial_txx9_register_ports(struct uart_driver *drv)
830 {
831 int i;
832
833 for (i = 0; i < UART_NR; i++) {
834 struct uart_txx9_port *up = &serial_txx9_ports[i];
835
836 up->port.line = i;
837 up->port.ops = &serial_txx9_pops;
838 if (up->port.iobase || up->port.mapbase)
839 uart_add_one_port(drv, &up->port);
840 }
841 }
842
843 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
844
845 /*
846 * Wait for transmitter & holding register to empty
847 */
848 static inline void wait_for_xmitr(struct uart_txx9_port *up)
849 {
850 unsigned int tmout = 10000;
851
852 /* Wait up to 10ms for the character(s) to be sent. */
853 while (--tmout &&
854 !(sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS))
855 udelay(1);
856
857 /* Wait up to 1s for flow control if necessary */
858 if (up->port.flags & UPF_CONS_FLOW) {
859 tmout = 1000000;
860 while (--tmout &&
861 (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS))
862 udelay(1);
863 }
864 }
865
866 static void serial_txx9_console_putchar(struct uart_port *port, int ch)
867 {
868 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
869
870 wait_for_xmitr(up);
871 sio_out(up, TXX9_SITFIFO, ch);
872 }
873
874 /*
875 * Print a string to the serial port trying not to disturb
876 * any possible real use of the port...
877 *
878 * The console_lock must be held when we get here.
879 */
880 static void
881 serial_txx9_console_write(struct console *co, const char *s, unsigned int count)
882 {
883 struct uart_txx9_port *up = &serial_txx9_ports[co->index];
884 unsigned int ier, flcr;
885
886 /*
887 * First save the UER then disable the interrupts
888 */
889 ier = sio_in(up, TXX9_SIDICR);
890 sio_out(up, TXX9_SIDICR, 0);
891 /*
892 * Disable flow-control if enabled (and unnecessary)
893 */
894 flcr = sio_in(up, TXX9_SIFLCR);
895 if (!(up->port.flags & UPF_CONS_FLOW) && (flcr & TXX9_SIFLCR_TES))
896 sio_out(up, TXX9_SIFLCR, flcr & ~TXX9_SIFLCR_TES);
897
898 uart_console_write(&up->port, s, count, serial_txx9_console_putchar);
899
900 /*
901 * Finally, wait for transmitter to become empty
902 * and restore the IER
903 */
904 wait_for_xmitr(up);
905 sio_out(up, TXX9_SIFLCR, flcr);
906 sio_out(up, TXX9_SIDICR, ier);
907 }
908
909 static int serial_txx9_console_setup(struct console *co, char *options)
910 {
911 struct uart_port *port;
912 struct uart_txx9_port *up;
913 int baud = 9600;
914 int bits = 8;
915 int parity = 'n';
916 int flow = 'n';
917
918 /*
919 * Check whether an invalid uart number has been specified, and
920 * if so, search for the first available port that does have
921 * console support.
922 */
923 if (co->index >= UART_NR)
924 co->index = 0;
925 up = &serial_txx9_ports[co->index];
926 port = &up->port;
927 if (!port->ops)
928 return -ENODEV;
929
930 /*
931 * Disable UART interrupts, set DTR and RTS high
932 * and set speed.
933 */
934 sio_out(up, TXX9_SIDICR, 0);
935 /* initial settings */
936 sio_out(up, TXX9_SILCR,
937 TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT |
938 ((port->flags & UPF_TXX9_USE_SCLK) ?
939 TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG));
940 sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX /* 15 */);
941
942 if (options)
943 uart_parse_options(options, &baud, &parity, &bits, &flow);
944
945 return uart_set_options(port, co, baud, parity, bits, flow);
946 }
947
948 static struct uart_driver serial_txx9_reg;
949 static struct console serial_txx9_console = {
950 .name = TXX9_TTY_NAME,
951 .write = serial_txx9_console_write,
952 .device = uart_console_device,
953 .setup = serial_txx9_console_setup,
954 .flags = CON_PRINTBUFFER,
955 .index = -1,
956 .data = &serial_txx9_reg,
957 };
958
959 static int __init serial_txx9_console_init(void)
960 {
961 register_console(&serial_txx9_console);
962 return 0;
963 }
964 console_initcall(serial_txx9_console_init);
965
966 #define SERIAL_TXX9_CONSOLE &serial_txx9_console
967 #else
968 #define SERIAL_TXX9_CONSOLE NULL
969 #endif
970
971 static struct uart_driver serial_txx9_reg = {
972 .owner = THIS_MODULE,
973 .driver_name = "serial_txx9",
974 .devfs_name = TXX9_TTY_DEVFS_NAME,
975 .dev_name = TXX9_TTY_NAME,
976 .major = TXX9_TTY_MAJOR,
977 .minor = TXX9_TTY_MINOR_START,
978 .nr = UART_NR,
979 .cons = SERIAL_TXX9_CONSOLE,
980 };
981
982 int __init early_serial_txx9_setup(struct uart_port *port)
983 {
984 if (port->line >= ARRAY_SIZE(serial_txx9_ports))
985 return -ENODEV;
986
987 serial_txx9_ports[port->line].port = *port;
988 serial_txx9_ports[port->line].port.ops = &serial_txx9_pops;
989 serial_txx9_ports[port->line].port.flags |= UPF_BOOT_AUTOCONF;
990 return 0;
991 }
992
993 #ifdef ENABLE_SERIAL_TXX9_PCI
994 /**
995 * serial_txx9_suspend_port - suspend one serial port
996 * @line: serial line number
997 * @level: the level of port suspension, as per uart_suspend_port
998 *
999 * Suspend one serial port.
1000 */
1001 static void serial_txx9_suspend_port(int line)
1002 {
1003 uart_suspend_port(&serial_txx9_reg, &serial_txx9_ports[line].port);
1004 }
1005
1006 /**
1007 * serial_txx9_resume_port - resume one serial port
1008 * @line: serial line number
1009 * @level: the level of port resumption, as per uart_resume_port
1010 *
1011 * Resume one serial port.
1012 */
1013 static void serial_txx9_resume_port(int line)
1014 {
1015 uart_resume_port(&serial_txx9_reg, &serial_txx9_ports[line].port);
1016 }
1017
1018 static DEFINE_MUTEX(serial_txx9_mutex);
1019
1020 /**
1021 * serial_txx9_register_port - register a serial port
1022 * @port: serial port template
1023 *
1024 * Configure the serial port specified by the request.
1025 *
1026 * The port is then probed and if necessary the IRQ is autodetected
1027 * If this fails an error is returned.
1028 *
1029 * On success the port is ready to use and the line number is returned.
1030 */
1031 static int __devinit serial_txx9_register_port(struct uart_port *port)
1032 {
1033 int i;
1034 struct uart_txx9_port *uart;
1035 int ret = -ENOSPC;
1036
1037 mutex_lock(&serial_txx9_mutex);
1038 for (i = 0; i < UART_NR; i++) {
1039 uart = &serial_txx9_ports[i];
1040 if (!(uart->port.iobase || uart->port.mapbase))
1041 break;
1042 }
1043 if (i < UART_NR) {
1044 uart->port.iobase = port->iobase;
1045 uart->port.membase = port->membase;
1046 uart->port.irq = port->irq;
1047 uart->port.uartclk = port->uartclk;
1048 uart->port.iotype = port->iotype;
1049 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
1050 uart->port.mapbase = port->mapbase;
1051 if (port->dev)
1052 uart->port.dev = port->dev;
1053 ret = uart_add_one_port(&serial_txx9_reg, &uart->port);
1054 if (ret == 0)
1055 ret = uart->port.line;
1056 }
1057 mutex_unlock(&serial_txx9_mutex);
1058 return ret;
1059 }
1060
1061 /**
1062 * serial_txx9_unregister_port - remove a txx9 serial port at runtime
1063 * @line: serial line number
1064 *
1065 * Remove one serial port. This may not be called from interrupt
1066 * context. We hand the port back to the our control.
1067 */
1068 static void __devexit serial_txx9_unregister_port(int line)
1069 {
1070 struct uart_txx9_port *uart = &serial_txx9_ports[line];
1071
1072 mutex_lock(&serial_txx9_mutex);
1073 uart_remove_one_port(&serial_txx9_reg, &uart->port);
1074 uart->port.flags = 0;
1075 uart->port.type = PORT_UNKNOWN;
1076 uart->port.iobase = 0;
1077 uart->port.mapbase = 0;
1078 uart->port.membase = NULL;
1079 uart->port.dev = NULL;
1080 mutex_unlock(&serial_txx9_mutex);
1081 }
1082
1083 /*
1084 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1085 * to the arrangement of serial ports on a PCI card.
1086 */
1087 static int __devinit
1088 pciserial_txx9_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1089 {
1090 struct uart_port port;
1091 int line;
1092 int rc;
1093
1094 rc = pci_enable_device(dev);
1095 if (rc)
1096 return rc;
1097
1098 memset(&port, 0, sizeof(port));
1099 port.ops = &serial_txx9_pops;
1100 port.flags |= UPF_TXX9_HAVE_CTS_LINE;
1101 port.uartclk = 66670000;
1102 port.irq = dev->irq;
1103 port.iotype = UPIO_PORT;
1104 port.iobase = pci_resource_start(dev, 1);
1105 port.dev = &dev->dev;
1106 line = serial_txx9_register_port(&port);
1107 if (line < 0) {
1108 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), line);
1109 }
1110 pci_set_drvdata(dev, (void *)(long)line);
1111
1112 return 0;
1113 }
1114
1115 static void __devexit pciserial_txx9_remove_one(struct pci_dev *dev)
1116 {
1117 int line = (int)(long)pci_get_drvdata(dev);
1118
1119 pci_set_drvdata(dev, NULL);
1120
1121 if (line) {
1122 serial_txx9_unregister_port(line);
1123 pci_disable_device(dev);
1124 }
1125 }
1126
1127 static int pciserial_txx9_suspend_one(struct pci_dev *dev, pm_message_t state)
1128 {
1129 int line = (int)(long)pci_get_drvdata(dev);
1130
1131 if (line)
1132 serial_txx9_suspend_port(line);
1133 pci_save_state(dev);
1134 pci_set_power_state(dev, pci_choose_state(dev, state));
1135 return 0;
1136 }
1137
1138 static int pciserial_txx9_resume_one(struct pci_dev *dev)
1139 {
1140 int line = (int)(long)pci_get_drvdata(dev);
1141
1142 pci_set_power_state(dev, PCI_D0);
1143 pci_restore_state(dev);
1144
1145 if (line) {
1146 pci_enable_device(dev);
1147 serial_txx9_resume_port(line);
1148 }
1149 return 0;
1150 }
1151
1152 static struct pci_device_id serial_txx9_pci_tbl[] = {
1153 { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC,
1154 PCI_ANY_ID, PCI_ANY_ID,
1155 0, 0, 0 },
1156 { 0, }
1157 };
1158
1159 static struct pci_driver serial_txx9_pci_driver = {
1160 .name = "serial_txx9",
1161 .probe = pciserial_txx9_init_one,
1162 .remove = __devexit_p(pciserial_txx9_remove_one),
1163 .suspend = pciserial_txx9_suspend_one,
1164 .resume = pciserial_txx9_resume_one,
1165 .id_table = serial_txx9_pci_tbl,
1166 };
1167
1168 MODULE_DEVICE_TABLE(pci, serial_txx9_pci_tbl);
1169 #endif /* ENABLE_SERIAL_TXX9_PCI */
1170
1171 static int __init serial_txx9_init(void)
1172 {
1173 int ret;
1174
1175 printk(KERN_INFO "%s version %s\n", serial_name, serial_version);
1176
1177 ret = uart_register_driver(&serial_txx9_reg);
1178 if (ret >= 0) {
1179 serial_txx9_register_ports(&serial_txx9_reg);
1180
1181 #ifdef ENABLE_SERIAL_TXX9_PCI
1182 ret = pci_register_driver(&serial_txx9_pci_driver);
1183 #endif
1184 }
1185 return ret;
1186 }
1187
1188 static void __exit serial_txx9_exit(void)
1189 {
1190 int i;
1191
1192 #ifdef ENABLE_SERIAL_TXX9_PCI
1193 pci_unregister_driver(&serial_txx9_pci_driver);
1194 #endif
1195 for (i = 0; i < UART_NR; i++) {
1196 struct uart_txx9_port *up = &serial_txx9_ports[i];
1197 if (up->port.iobase || up->port.mapbase)
1198 uart_remove_one_port(&serial_txx9_reg, &up->port);
1199 }
1200
1201 uart_unregister_driver(&serial_txx9_reg);
1202 }
1203
1204 module_init(serial_txx9_init);
1205 module_exit(serial_txx9_exit);
1206
1207 MODULE_LICENSE("GPL");
1208 MODULE_DESCRIPTION("TX39/49 serial driver");
1209
1210 MODULE_ALIAS_CHARDEV_MAJOR(TXX9_TTY_MAJOR);
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