arch/i386/kernel/i8253.c

   1 /*
   2  * i8253.c  8253/PIT functions
   3  *
   4  */
   5 #include <linux/clockchips.h>
   6 #include <linux/init.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/jiffies.h>
   9 #include <linux/module.h>
  10 #include <linux/spinlock.h>
  11
  12 #include <asm/smp.h>
  13 #include <asm/delay.h>
  14 #include <asm/i8253.h>
  15 #include <asm/io.h>
  16
  17 #include "io_ports.h"
  18
  19 DEFINE_SPINLOCK(i8253_lock);
  20 EXPORT_SYMBOL(i8253_lock);
  21
  22 /*
  23  * HPET replaces the PIT, when enabled. So we need to know, which of
  24  * the two timers is used
  25  */
  26 struct clock_event_device *global_clock_event;
  27
  28 /*
  29  * Initialize the PIT timer.
  30  *
  31  * This is also called after resume to bring the PIT into operation again.
  32  */
  33 static void init_pit_timer(enum clock_event_mode mode,
  34                            struct clock_event_device *evt)
  35 {
  36         unsigned long flags;
  37
  38         spin_lock_irqsave(&i8253_lock, flags);
  39
  40         switch(mode) {
  41         case CLOCK_EVT_MODE_PERIODIC:
  42                 /* binary, mode 2, LSB/MSB, ch 0 */
  43                 outb_p(0x34, PIT_MODE);
  44                 outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
  45                 outb(LATCH >> 8 , PIT_CH0);     /* MSB */
  46                 break;
  47
  48         case CLOCK_EVT_MODE_SHUTDOWN:
  49         case CLOCK_EVT_MODE_UNUSED:
  50                 if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
  51                     evt->mode == CLOCK_EVT_MODE_ONESHOT) {
  52                         outb_p(0x30, PIT_MODE);
  53                         outb_p(0, PIT_CH0);
  54                         outb_p(0, PIT_CH0);
  55                 }
  56                 break;
  57
  58         case CLOCK_EVT_MODE_ONESHOT:
  59                 /* One shot setup */
  60                 outb_p(0x38, PIT_MODE);
  61                 break;
  62
  63         case CLOCK_EVT_MODE_RESUME:
  64                 /* Nothing to do here */
  65                 break;
  66         }
  67         spin_unlock_irqrestore(&i8253_lock, flags);
  68 }
  69
  70 /*
  71  * Program the next event in oneshot mode
  72  *
  73  * Delta is given in PIT ticks
  74  */
  75 static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
  76 {
  77         unsigned long flags;
  78
  79         spin_lock_irqsave(&i8253_lock, flags);
  80         outb_p(delta & 0xff , PIT_CH0); /* LSB */
  81         outb(delta >> 8 , PIT_CH0);     /* MSB */
  82         spin_unlock_irqrestore(&i8253_lock, flags);
  83
  84         return 0;
  85 }
  86
  87 /*
  88  * On UP the PIT can serve all of the possible timer functions. On SMP systems
  89  * it can be solely used for the global tick.
  90  *
  91  * The profiling and update capabilites are switched off once the local apic is
  92  * registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
  93  * !using_apic_timer decisions in do_timer_interrupt_hook()
  94  */
  95 struct clock_event_device pit_clockevent = {
  96         .name           = "pit",
  97         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  98         .set_mode       = init_pit_timer,
  99         .set_next_event = pit_next_event,
 100         .shift          = 32,
 101         .irq            = 0,
 102 };
 103
 104 /*
 105  * Initialize the conversion factor and the min/max deltas of the clock event
 106  * structure and register the clock event source with the framework.
 107  */
 108 void __init setup_pit_timer(void)
 109 {
 110         /*
 111          * Start pit with the boot cpu mask and make it global after the
 112          * IO_APIC has been initialized.
 113          */
 114         pit_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
 115         pit_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, 32);
 116         pit_clockevent.max_delta_ns =
 117                 clockevent_delta2ns(0x7FFF, &pit_clockevent);
 118         pit_clockevent.min_delta_ns =
 119                 clockevent_delta2ns(0xF, &pit_clockevent);
 120         clockevents_register_device(&pit_clockevent);
 121         global_clock_event = &pit_clockevent;
 122 }
 123
 124 /*
 125  * Since the PIT overflows every tick, its not very useful
 126  * to just read by itself. So use jiffies to emulate a free
 127  * running counter:
 128  */
 129 static cycle_t pit_read(void)
 130 {
 131         unsigned long flags;
 132         int count;
 133         u32 jifs;
 134         static int old_count;
 135         static u32 old_jifs;
 136
 137         spin_lock_irqsave(&i8253_lock, flags);
 138         /*
 139          * Although our caller may have the read side of xtime_lock,
 140          * this is now a seqlock, and we are cheating in this routine
 141          * by having side effects on state that we cannot undo if
 142          * there is a collision on the seqlock and our caller has to
 143          * retry.  (Namely, old_jifs and old_count.)  So we must treat
 144          * jiffies as volatile despite the lock.  We read jiffies
 145          * before latching the timer count to guarantee that although
 146          * the jiffies value might be older than the count (that is,
 147          * the counter may underflow between the last point where
 148          * jiffies was incremented and the point where we latch the
 149          * count), it cannot be newer.
 150          */
 151         jifs = jiffies;
 152         outb_p(0x00, PIT_MODE); /* latch the count ASAP */
 153         count = inb_p(PIT_CH0); /* read the latched count */
 154         count |= inb_p(PIT_CH0) << 8;
 155
 156         /* VIA686a test code... reset the latch if count > max + 1 */
 157         if (count > LATCH) {
 158                 outb_p(0x34, PIT_MODE);
 159                 outb_p(LATCH & 0xff, PIT_CH0);
 160                 outb(LATCH >> 8, PIT_CH0);
 161                 count = LATCH - 1;
 162         }
 163
 164         /*
 165          * It's possible for count to appear to go the wrong way for a
 166          * couple of reasons:
 167          *
 168          *  1. The timer counter underflows, but we haven't handled the
 169          *     resulting interrupt and incremented jiffies yet.
 170          *  2. Hardware problem with the timer, not giving us continuous time,
 171          *     the counter does small "jumps" upwards on some Pentium systems,
 172          *     (see c't 95/10 page 335 for Neptun bug.)
 173          *
 174          * Previous attempts to handle these cases intelligently were
 175          * buggy, so we just do the simple thing now.
 176          */
 177         if (count > old_count && jifs == old_jifs) {
 178                 count = old_count;
 179         }
 180         old_count = count;
 181         old_jifs = jifs;
 182
 183         spin_unlock_irqrestore(&i8253_lock, flags);
 184
 185         count = (LATCH - 1) - count;
 186
 187         return (cycle_t)(jifs * LATCH) + count;
 188 }
 189
 190 static struct clocksource clocksource_pit = {
 191         .name   = "pit",
 192         .rating = 110,
 193         .read   = pit_read,
 194         .mask   = CLOCKSOURCE_MASK(32),
 195         .mult   = 0,
 196         .shift  = 20,
 197 };
 198
 199 static int __init init_pit_clocksource(void)
 200 {
 201         if (num_possible_cpus() > 1) /* PIT does not scale! */
 202                 return 0;
 203
 204         clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20);
 205         return clocksource_register(&clocksource_pit);
 206 }
 207 arch_initcall(init_pit_clocksource);