arch/arm/mach-orion5x/pci.c

   1 /*
   2  * arch/arm/mach-orion5x/pci.c
   3  *
   4  * PCI and PCIe functions for Marvell Orion System On Chip
   5  *
   6  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/pci.h>
  15 #include <linux/mbus.h>
  16 #include <asm/mach/pci.h>
  17 #include <asm/plat-orion/pcie.h>
  18 #include "common.h"
  19
  20 /*****************************************************************************
  21  * Orion has one PCIe controller and one PCI controller.
  22  *
  23  * Note1: The local PCIe bus number is '0'. The local PCI bus number
  24  * follows the scanned PCIe bridged busses, if any.
  25  *
  26  * Note2: It is possible for PCI/PCIe agents to access many subsystem's
  27  * space, by configuring BARs and Address Decode Windows, e.g. flashes on
  28  * device bus, Orion registers, etc. However this code only enable the
  29  * access to DDR banks.
  30  ****************************************************************************/
  31
  32
  33 /*****************************************************************************
  34  * PCIe controller
  35  ****************************************************************************/
  36 #define PCIE_BASE       ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
  37
  38 void __init orion5x_pcie_id(u32 *dev, u32 *rev)
  39 {
  40         *dev = orion_pcie_dev_id(PCIE_BASE);
  41         *rev = orion_pcie_rev(PCIE_BASE);
  42 }
  43
  44 static int pcie_valid_config(int bus, int dev)
  45 {
  46         /*
  47          * Don't go out when trying to access --
  48          * 1. nonexisting device on local bus
  49          * 2. where there's no device connected (no link)
  50          */
  51         if (bus == 0 && dev == 0)
  52                 return 1;
  53
  54         if (!orion_pcie_link_up(PCIE_BASE))
  55                 return 0;
  56
  57         if (bus == 0 && dev != 1)
  58                 return 0;
  59
  60         return 1;
  61 }
  62
  63
  64 /*
  65  * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
  66  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  67  * transactions are atomic.
  68  */
  69 static DEFINE_SPINLOCK(orion5x_pcie_lock);
  70
  71 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  72                         int size, u32 *val)
  73 {
  74         unsigned long flags;
  75         int ret;
  76
  77         if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
  78                 *val = 0xffffffff;
  79                 return PCIBIOS_DEVICE_NOT_FOUND;
  80         }
  81
  82         spin_lock_irqsave(&orion5x_pcie_lock, flags);
  83         ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
  84         spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
  85
  86         return ret;
  87 }
  88
  89 static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
  90                            int where, int size, u32 *val)
  91 {
  92         int ret;
  93
  94         if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
  95                 *val = 0xffffffff;
  96                 return PCIBIOS_DEVICE_NOT_FOUND;
  97         }
  98
  99         /*
 100          * We only support access to the non-extended configuration
 101          * space when using the WA access method (or we would have to
 102          * sacrifice 256M of CPU virtual address space.)
 103          */
 104         if (where >= 0x100) {
 105                 *val = 0xffffffff;
 106                 return PCIBIOS_DEVICE_NOT_FOUND;
 107         }
 108
 109         ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
 110                                     bus, devfn, where, size, val);
 111
 112         return ret;
 113 }
 114
 115 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 116                         int where, int size, u32 val)
 117 {
 118         unsigned long flags;
 119         int ret;
 120
 121         if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
 122                 return PCIBIOS_DEVICE_NOT_FOUND;
 123
 124         spin_lock_irqsave(&orion5x_pcie_lock, flags);
 125         ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
 126         spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
 127
 128         return ret;
 129 }
 130
 131 static struct pci_ops pcie_ops = {
 132         .read = pcie_rd_conf,
 133         .write = pcie_wr_conf,
 134 };
 135
 136
 137 static int __init pcie_setup(struct pci_sys_data *sys)
 138 {
 139         struct resource *res;
 140         int dev;
 141
 142         /*
 143          * Generic PCIe unit setup.
 144          */
 145         orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
 146
 147         /*
 148          * Check whether to apply Orion-1/Orion-NAS PCIe config
 149          * read transaction workaround.
 150          */
 151         dev = orion_pcie_dev_id(PCIE_BASE);
 152         if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
 153                 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
 154                                    "read transaction workaround\n");
 155                 pcie_ops.read = pcie_rd_conf_wa;
 156         }
 157
 158         /*
 159          * Request resources.
 160          */
 161         res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
 162         if (!res)
 163                 panic("pcie_setup unable to alloc resources");
 164
 165         /*
 166          * IORESOURCE_IO
 167          */
 168         res[0].name = "PCIe I/O Space";
 169         res[0].flags = IORESOURCE_IO;
 170         res[0].start = ORION5X_PCIE_IO_BUS_BASE;
 171         res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
 172         if (request_resource(&ioport_resource, &res[0]))
 173                 panic("Request PCIe IO resource failed\n");
 174         sys->resource[0] = &res[0];
 175
 176         /*
 177          * IORESOURCE_MEM
 178          */
 179         res[1].name = "PCIe Memory Space";
 180         res[1].flags = IORESOURCE_MEM;
 181         res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
 182         res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
 183         if (request_resource(&iomem_resource, &res[1]))
 184                 panic("Request PCIe Memory resource failed\n");
 185         sys->resource[1] = &res[1];
 186
 187         sys->resource[2] = NULL;
 188         sys->io_offset = 0;
 189
 190         return 1;
 191 }
 192
 193 /*****************************************************************************
 194  * PCI controller
 195  ****************************************************************************/
 196 #define PCI_MODE                ORION5X_PCI_REG(0xd00)
 197 #define PCI_CMD                 ORION5X_PCI_REG(0xc00)
 198 #define PCI_P2P_CONF            ORION5X_PCI_REG(0x1d14)
 199 #define PCI_CONF_ADDR           ORION5X_PCI_REG(0xc78)
 200 #define PCI_CONF_DATA           ORION5X_PCI_REG(0xc7c)
 201
 202 /*
 203  * PCI_MODE bits
 204  */
 205 #define PCI_MODE_64BIT                  (1 << 2)
 206 #define PCI_MODE_PCIX                   ((1 << 4) | (1 << 5))
 207
 208 /*
 209  * PCI_CMD bits
 210  */
 211 #define PCI_CMD_HOST_REORDER            (1 << 29)
 212
 213 /*
 214  * PCI_P2P_CONF bits
 215  */
 216 #define PCI_P2P_BUS_OFFS                16
 217 #define PCI_P2P_BUS_MASK                (0xff << PCI_P2P_BUS_OFFS)
 218 #define PCI_P2P_DEV_OFFS                24
 219 #define PCI_P2P_DEV_MASK                (0x1f << PCI_P2P_DEV_OFFS)
 220
 221 /*
 222  * PCI_CONF_ADDR bits
 223  */
 224 #define PCI_CONF_REG(reg)               ((reg) & 0xfc)
 225 #define PCI_CONF_FUNC(func)             (((func) & 0x3) << 8)
 226 #define PCI_CONF_DEV(dev)               (((dev) & 0x1f) << 11)
 227 #define PCI_CONF_BUS(bus)               (((bus) & 0xff) << 16)
 228 #define PCI_CONF_ADDR_EN                (1 << 31)
 229
 230 /*
 231  * Internal configuration space
 232  */
 233 #define PCI_CONF_FUNC_STAT_CMD          0
 234 #define PCI_CONF_REG_STAT_CMD           4
 235 #define PCIX_STAT                       0x64
 236 #define PCIX_STAT_BUS_OFFS              8
 237 #define PCIX_STAT_BUS_MASK              (0xff << PCIX_STAT_BUS_OFFS)
 238
 239 /*
 240  * PCI Address Decode Windows registers
 241  */
 242 #define PCI_BAR_SIZE_DDR_CS(n)  (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
 243                                 ((n) == 1) ? ORION5X_PCI_REG(0xd08) :  \
 244                                 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) :  \
 245                                 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
 246 #define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) :  \
 247                                 ((n) == 1) ? ORION5X_PCI_REG(0xd48) :  \
 248                                 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) :  \
 249                                 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
 250 #define PCI_BAR_ENABLE          ORION5X_PCI_REG(0xc3c)
 251 #define PCI_ADDR_DECODE_CTRL    ORION5X_PCI_REG(0xd3c)
 252
 253 /*
 254  * PCI configuration helpers for BAR settings
 255  */
 256 #define PCI_CONF_FUNC_BAR_CS(n)         ((n) >> 1)
 257 #define PCI_CONF_REG_BAR_LO_CS(n)       (((n) & 1) ? 0x18 : 0x10)
 258 #define PCI_CONF_REG_BAR_HI_CS(n)       (((n) & 1) ? 0x1c : 0x14)
 259
 260 /*
 261  * PCI config cycles are done by programming the PCI_CONF_ADDR register
 262  * and then reading the PCI_CONF_DATA register. Need to make sure these
 263  * transactions are atomic.
 264  */
 265 static DEFINE_SPINLOCK(orion5x_pci_lock);
 266
 267 static int orion5x_pci_local_bus_nr(void)
 268 {
 269         u32 conf = orion5x_read(PCI_P2P_CONF);
 270         return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
 271 }
 272
 273 static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
 274                                         u32 where, u32 size, u32 *val)
 275 {
 276         unsigned long flags;
 277         spin_lock_irqsave(&orion5x_pci_lock, flags);
 278
 279         orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
 280                         PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
 281                         PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
 282
 283         *val = orion5x_read(PCI_CONF_DATA);
 284
 285         if (size == 1)
 286                 *val = (*val >> (8*(where & 0x3))) & 0xff;
 287         else if (size == 2)
 288                 *val = (*val >> (8*(where & 0x3))) & 0xffff;
 289
 290         spin_unlock_irqrestore(&orion5x_pci_lock, flags);
 291
 292         return PCIBIOS_SUCCESSFUL;
 293 }
 294
 295 static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
 296                                         u32 where, u32 size, u32 val)
 297 {
 298         unsigned long flags;
 299         int ret = PCIBIOS_SUCCESSFUL;
 300
 301         spin_lock_irqsave(&orion5x_pci_lock, flags);
 302
 303         orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
 304                         PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
 305                         PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
 306
 307         if (size == 4) {
 308                 __raw_writel(val, PCI_CONF_DATA);
 309         } else if (size == 2) {
 310                 __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
 311         } else if (size == 1) {
 312                 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
 313         } else {
 314                 ret = PCIBIOS_BAD_REGISTER_NUMBER;
 315         }
 316
 317         spin_unlock_irqrestore(&orion5x_pci_lock, flags);
 318
 319         return ret;
 320 }
 321
 322 static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
 323                                 int where, int size, u32 *val)
 324 {
 325         /*
 326          * Don't go out for local device
 327          */
 328         if (bus->number == orion5x_pci_local_bus_nr() &&
 329             PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) {
 330                 *val = 0xffffffff;
 331                 return PCIBIOS_DEVICE_NOT_FOUND;
 332         }
 333
 334         return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
 335                                         PCI_FUNC(devfn), where, size, val);
 336 }
 337
 338 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
 339                                 int where, int size, u32 val)
 340 {
 341         if (bus->number == orion5x_pci_local_bus_nr() &&
 342             PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
 343                 return PCIBIOS_DEVICE_NOT_FOUND;
 344
 345         return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
 346                                         PCI_FUNC(devfn), where, size, val);
 347 }
 348
 349 static struct pci_ops pci_ops = {
 350         .read = orion5x_pci_rd_conf,
 351         .write = orion5x_pci_wr_conf,
 352 };
 353
 354 static void __init orion5x_pci_set_bus_nr(int nr)
 355 {
 356         u32 p2p = orion5x_read(PCI_P2P_CONF);
 357
 358         if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) {
 359                 /*
 360                  * PCI-X mode
 361                  */
 362                 u32 pcix_status, bus, dev;
 363                 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
 364                 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
 365                 orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
 366                 pcix_status &= ~PCIX_STAT_BUS_MASK;
 367                 pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
 368                 orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
 369         } else {
 370                 /*
 371                  * PCI Conventional mode
 372                  */
 373                 p2p &= ~PCI_P2P_BUS_MASK;
 374                 p2p |= (nr << PCI_P2P_BUS_OFFS);
 375                 orion5x_write(PCI_P2P_CONF, p2p);
 376         }
 377 }
 378
 379 static void __init orion5x_pci_master_slave_enable(void)
 380 {
 381         int bus_nr, func, reg;
 382         u32 val;
 383
 384         bus_nr = orion5x_pci_local_bus_nr();
 385         func = PCI_CONF_FUNC_STAT_CMD;
 386         reg = PCI_CONF_REG_STAT_CMD;
 387         orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
 388         val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 389         orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
 390 }
 391
 392 static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
 393 {
 394         u32 win_enable;
 395         int bus;
 396         int i;
 397
 398         /*
 399          * First, disable windows.
 400          */
 401         win_enable = 0xffffffff;
 402         orion5x_write(PCI_BAR_ENABLE, win_enable);
 403
 404         /*
 405          * Setup windows for DDR banks.
 406          */
 407         bus = orion5x_pci_local_bus_nr();
 408
 409         for (i = 0; i < dram->num_cs; i++) {
 410                 struct mbus_dram_window *cs = dram->cs + i;
 411                 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
 412                 u32 reg;
 413                 u32 val;
 414
 415                 /*
 416                  * Write DRAM bank base address register.
 417                  */
 418                 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
 419                 orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
 420                 val = (cs->base & 0xfffff000) | (val & 0xfff);
 421                 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
 422
 423                 /*
 424                  * Write DRAM bank size register.
 425                  */
 426                 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
 427                 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
 428                 orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index),
 429                                 (cs->size - 1) & 0xfffff000);
 430                 orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index),
 431                                 cs->base & 0xfffff000);
 432
 433                 /*
 434                  * Enable decode window for this chip select.
 435                  */
 436                 win_enable &= ~(1 << cs->cs_index);
 437         }
 438
 439         /*
 440          * Re-enable decode windows.
 441          */
 442         orion5x_write(PCI_BAR_ENABLE, win_enable);
 443
 444         /*
 445          * Disable automatic update of address remaping when writing to BARs.
 446          */
 447         orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
 448 }
 449
 450 static int __init pci_setup(struct pci_sys_data *sys)
 451 {
 452         struct resource *res;
 453
 454         /*
 455          * Point PCI unit MBUS decode windows to DRAM space.
 456          */
 457         orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
 458
 459         /*
 460          * Master + Slave enable
 461          */
 462         orion5x_pci_master_slave_enable();
 463
 464         /*
 465          * Force ordering
 466          */
 467         orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
 468
 469         /*
 470          * Request resources
 471          */
 472         res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
 473         if (!res)
 474                 panic("pci_setup unable to alloc resources");
 475
 476         /*
 477          * IORESOURCE_IO
 478          */
 479         res[0].name = "PCI I/O Space";
 480         res[0].flags = IORESOURCE_IO;
 481         res[0].start = ORION5X_PCI_IO_BUS_BASE;
 482         res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
 483         if (request_resource(&ioport_resource, &res[0]))
 484                 panic("Request PCI IO resource failed\n");
 485         sys->resource[0] = &res[0];
 486
 487         /*
 488          * IORESOURCE_MEM
 489          */
 490         res[1].name = "PCI Memory Space";
 491         res[1].flags = IORESOURCE_MEM;
 492         res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
 493         res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
 494         if (request_resource(&iomem_resource, &res[1]))
 495                 panic("Request PCI Memory resource failed\n");
 496         sys->resource[1] = &res[1];
 497
 498         sys->resource[2] = NULL;
 499         sys->io_offset = 0;
 500
 501         return 1;
 502 }
 503
 504
 505 /*****************************************************************************
 506  * General PCIe + PCI
 507  ****************************************************************************/
 508 static void __devinit rc_pci_fixup(struct pci_dev *dev)
 509 {
 510         /*
 511          * Prevent enumeration of root complex.
 512          */
 513         if (dev->bus->parent == NULL && dev->devfn == 0) {
 514                 int i;
 515
 516                 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 517                         dev->resource[i].start = 0;
 518                         dev->resource[i].end   = 0;
 519                         dev->resource[i].flags = 0;
 520                 }
 521         }
 522 }
 523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
 524
 525 int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
 526 {
 527         int ret = 0;
 528
 529         if (nr == 0) {
 530                 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
 531                 ret = pcie_setup(sys);
 532         } else if (nr == 1) {
 533                 orion5x_pci_set_bus_nr(sys->busnr);
 534                 ret = pci_setup(sys);
 535         }
 536
 537         return ret;
 538 }
 539
 540 struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
 541 {
 542         struct pci_bus *bus;
 543
 544         if (nr == 0) {
 545                 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
 546         } else if (nr == 1) {
 547                 bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
 548         } else {
 549                 bus = NULL;
 550                 BUG();
 551         }
 552
 553         return bus;
 554 }
 555
 556 int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 557 {
 558         int bus = dev->bus->number;
 559
 560         /*
 561          * PCIe endpoint?
 562          */
 563         if (bus < orion5x_pci_local_bus_nr())
 564                 return IRQ_ORION5X_PCIE0_INT;
 565
 566         return -1;
 567 }