include/asm-arm/arch-s3c2410/regs-gpio.h

   1 /* linux/include/asm/hardware/s3c2410/regs-gpio.h
   2  *
   3  * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
   4  *                         http://www.simtec.co.uk/products/SWLINUX/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * S3C2410 GPIO register definitions
  11  *
  12  *  Changelog:
  13  *    19-06-2003     BJD     Created file
  14  *    23-06-2003     BJD     Updated GSTATUS registers
  15  *    12-03-2004     BJD     Updated include protection
  16  *    20-07-2004     BJD     Added GPIO pin numbers, added Port A definitions
  17  *    04-10-2004     BJD     Fixed number of bugs, added EXT IRQ filter defs
  18  *    17-10-2004     BJD     Added GSTATUS1 register definitions
  19  *    18-11-2004     BJD     Fixed definitions of GPE3, GPE4, GPE5 and GPE6
  20  *    18-11-2004     BJD     Added S3C2440 AC97 controls
  21  *    10-Mar-2005    LCVR    Changed S3C2410_VA to S3C24XX_VA
  22  *    28-Mar-2005    LCVR    Fixed definition of GPB10
  23  *    26-Oct-2005    BJD     Added generic configuration types
  24  *    27-Nov-2005    LCVR    Added definitions to S3C2400 registers
  25 */
  26
  27
  28 #ifndef __ASM_ARCH_REGS_GPIO_H
  29 #define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $"
  30
  31 #define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
  32
  33 #define S3C2410_GPIO_BANKA   (32*0)
  34 #define S3C2410_GPIO_BANKB   (32*1)
  35 #define S3C2410_GPIO_BANKC   (32*2)
  36 #define S3C2410_GPIO_BANKD   (32*3)
  37 #define S3C2410_GPIO_BANKE   (32*4)
  38 #define S3C2410_GPIO_BANKF   (32*5)
  39 #define S3C2410_GPIO_BANKG   (32*6)
  40 #define S3C2410_GPIO_BANKH   (32*7)
  41
  42 #define S3C2410_GPIO_BASE(pin)   ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)
  43 #define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
  44
  45 /* general configuration options */
  46
  47 #define S3C2410_GPIO_LEAVE   (0xFFFFFFFF)
  48 #define S3C2410_GPIO_INPUT   (0xFFFFFFF0)
  49 #define S3C2410_GPIO_OUTPUT  (0xFFFFFFF1)
  50 #define S3C2410_GPIO_IRQ     (0xFFFFFFF2)       /* not available for all */
  51 #define S3C2410_GPIO_SFN2    (0xFFFFFFF2)       /* not available on A */
  52 #define S3C2410_GPIO_SFN3    (0xFFFFFFF3)       /* not available on A */
  53
  54 /* configure GPIO ports A..G */
  55
  56 #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
  57
  58 /* port A - S3C2410: 22bits, zero in bit X makes pin X output
  59  *          S3C2400: 18bits, zero in bit X makes pin X output
  60  * 1 makes port special function, this is default
  61 */
  62 #define S3C2410_GPACON     S3C2410_GPIOREG(0x00)
  63 #define S3C2410_GPADAT     S3C2410_GPIOREG(0x04)
  64
  65 #define S3C2400_GPACON     S3C2410_GPIOREG(0x00)
  66 #define S3C2400_GPADAT     S3C2410_GPIOREG(0x04)
  67
  68 #define S3C2410_GPA0         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
  69 #define S3C2410_GPA0_OUT     (0<<0)
  70 #define S3C2410_GPA0_ADDR0   (1<<0)
  71
  72 #define S3C2410_GPA1         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
  73 #define S3C2410_GPA1_OUT     (0<<1)
  74 #define S3C2410_GPA1_ADDR16  (1<<1)
  75
  76 #define S3C2410_GPA2         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
  77 #define S3C2410_GPA2_OUT     (0<<2)
  78 #define S3C2410_GPA2_ADDR17  (1<<2)
  79
  80 #define S3C2410_GPA3         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
  81 #define S3C2410_GPA3_OUT     (0<<3)
  82 #define S3C2410_GPA3_ADDR18  (1<<3)
  83
  84 #define S3C2410_GPA4         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
  85 #define S3C2410_GPA4_OUT     (0<<4)
  86 #define S3C2410_GPA4_ADDR19  (1<<4)
  87
  88 #define S3C2410_GPA5         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
  89 #define S3C2410_GPA5_OUT     (0<<5)
  90 #define S3C2410_GPA5_ADDR20  (1<<5)
  91
  92 #define S3C2410_GPA6         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
  93 #define S3C2410_GPA6_OUT     (0<<6)
  94 #define S3C2410_GPA6_ADDR21  (1<<6)
  95
  96 #define S3C2410_GPA7         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
  97 #define S3C2410_GPA7_OUT     (0<<7)
  98 #define S3C2410_GPA7_ADDR22  (1<<7)
  99
 100 #define S3C2410_GPA8         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
 101 #define S3C2410_GPA8_OUT     (0<<8)
 102 #define S3C2410_GPA8_ADDR23  (1<<8)
 103
 104 #define S3C2410_GPA9         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
 105 #define S3C2410_GPA9_OUT     (0<<9)
 106 #define S3C2410_GPA9_ADDR24  (1<<9)
 107
 108 #define S3C2410_GPA10        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
 109 #define S3C2410_GPA10_OUT    (0<<10)
 110 #define S3C2410_GPA10_ADDR25 (1<<10)
 111 #define S3C2400_GPA10_SCKE   (1<<10)
 112
 113 #define S3C2410_GPA11        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
 114 #define S3C2410_GPA11_OUT    (0<<11)
 115 #define S3C2410_GPA11_ADDR26 (1<<11)
 116 #define S3C2400_GPA11_nCAS0  (1<<11)
 117
 118 #define S3C2410_GPA12        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
 119 #define S3C2410_GPA12_OUT    (0<<12)
 120 #define S3C2410_GPA12_nGCS1  (1<<12)
 121 #define S3C2400_GPA12_nCAS1  (1<<12)
 122
 123 #define S3C2410_GPA13        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
 124 #define S3C2410_GPA13_OUT    (0<<13)
 125 #define S3C2410_GPA13_nGCS2  (1<<13)
 126 #define S3C2400_GPA13_nGCS1  (1<<13)
 127
 128 #define S3C2410_GPA14        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
 129 #define S3C2410_GPA14_OUT    (0<<14)
 130 #define S3C2410_GPA14_nGCS3  (1<<14)
 131 #define S3C2400_GPA14_nGCS2  (1<<14)
 132
 133 #define S3C2410_GPA15        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
 134 #define S3C2410_GPA15_OUT    (0<<15)
 135 #define S3C2410_GPA15_nGCS4  (1<<15)
 136 #define S3C2400_GPA15_nGCS3  (1<<15)
 137
 138 #define S3C2410_GPA16        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
 139 #define S3C2410_GPA16_OUT    (0<<16)
 140 #define S3C2410_GPA16_nGCS5  (1<<16)
 141 #define S3C2400_GPA16_nGCS4  (1<<16)
 142
 143 #define S3C2410_GPA17        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
 144 #define S3C2410_GPA17_OUT    (0<<17)
 145 #define S3C2410_GPA17_CLE    (1<<17)
 146 #define S3C2400_GPA17_nGCS5  (1<<17)
 147
 148 #define S3C2410_GPA18        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
 149 #define S3C2410_GPA18_OUT    (0<<18)
 150 #define S3C2410_GPA18_ALE    (1<<18)
 151
 152 #define S3C2410_GPA19        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
 153 #define S3C2410_GPA19_OUT    (0<<19)
 154 #define S3C2410_GPA19_nFWE   (1<<19)
 155
 156 #define S3C2410_GPA20        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
 157 #define S3C2410_GPA20_OUT    (0<<20)
 158 #define S3C2410_GPA20_nFRE   (1<<20)
 159
 160 #define S3C2410_GPA21        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
 161 #define S3C2410_GPA21_OUT    (0<<21)
 162 #define S3C2410_GPA21_nRSTOUT (1<<21)
 163
 164 #define S3C2410_GPA22        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
 165 #define S3C2410_GPA22_OUT    (0<<22)
 166 #define S3C2410_GPA22_nFCE   (1<<22)
 167
 168 /* 0x08 and 0x0c are reserved on S3C2410 */
 169
 170 /* S3C2410:
 171  * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
 172  *   00 = input, 01 = output, 10=special function, 11=reserved
 173
 174  * S3C2400:
 175  * GPB is 16 IO pins, each configured by 2 bits each in GPBCON.
 176  *   00 = input, 01 = output, 10=data, 11=special function
 177
 178  * bit 0,1 = pin 0, 2,3= pin 1...
 179  *
 180  * CPBUP = pull up resistor control, 1=disabled, 0=enabled
 181 */
 182
 183 #define S3C2410_GPBCON     S3C2410_GPIOREG(0x10)
 184 #define S3C2410_GPBDAT     S3C2410_GPIOREG(0x14)
 185 #define S3C2410_GPBUP      S3C2410_GPIOREG(0x18)
 186
 187 #define S3C2400_GPBCON     S3C2410_GPIOREG(0x08)
 188 #define S3C2400_GPBDAT     S3C2410_GPIOREG(0x0C)
 189 #define S3C2400_GPBUP      S3C2410_GPIOREG(0x10)
 190
 191 /* no i/o pin in port b can have value 3! */
 192
 193 #define S3C2410_GPB0         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
 194 #define S3C2410_GPB0_INP     (0x00 << 0)
 195 #define S3C2410_GPB0_OUTP    (0x01 << 0)
 196 #define S3C2410_GPB0_TOUT0   (0x02 << 0)
 197 #define S3C2400_GPB0_DATA16  (0x02 << 0)
 198
 199 #define S3C2410_GPB1         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
 200 #define S3C2410_GPB1_INP     (0x00 << 2)
 201 #define S3C2410_GPB1_OUTP    (0x01 << 2)
 202 #define S3C2410_GPB1_TOUT1   (0x02 << 2)
 203 #define S3C2400_GPB1_DATA17  (0x02 << 2)
 204
 205 #define S3C2410_GPB2         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
 206 #define S3C2410_GPB2_INP     (0x00 << 4)
 207 #define S3C2410_GPB2_OUTP    (0x01 << 4)
 208 #define S3C2410_GPB2_TOUT2   (0x02 << 4)
 209 #define S3C2400_GPB2_DATA18  (0x02 << 4)
 210 #define S3C2400_GPB2_TCLK1   (0x03 << 4)
 211
 212 #define S3C2410_GPB3         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
 213 #define S3C2410_GPB3_INP     (0x00 << 6)
 214 #define S3C2410_GPB3_OUTP    (0x01 << 6)
 215 #define S3C2410_GPB3_TOUT3   (0x02 << 6)
 216 #define S3C2400_GPB3_DATA19  (0x02 << 6)
 217 #define S3C2400_GPB3_TXD1    (0x03 << 6)
 218
 219 #define S3C2410_GPB4         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
 220 #define S3C2410_GPB4_INP     (0x00 << 8)
 221 #define S3C2410_GPB4_OUTP    (0x01 << 8)
 222 #define S3C2410_GPB4_TCLK0   (0x02 << 8)
 223 #define S3C2400_GPB4_DATA20  (0x02 << 8)
 224 #define S3C2410_GPB4_MASK    (0x03 << 8)
 225 #define S3C2400_GPB4_RXD1    (0x03 << 8)
 226 #define S3C2400_GPB4_MASK    (0x03 << 8)
 227
 228 #define S3C2410_GPB5         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
 229 #define S3C2410_GPB5_INP     (0x00 << 10)
 230 #define S3C2410_GPB5_OUTP    (0x01 << 10)
 231 #define S3C2410_GPB5_nXBACK  (0x02 << 10)
 232 #define S3C2400_GPB5_DATA21  (0x02 << 10)
 233 #define S3C2400_GPB5_nCTS1   (0x03 << 10)
 234
 235 #define S3C2410_GPB6         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
 236 #define S3C2410_GPB6_INP     (0x00 << 12)
 237 #define S3C2410_GPB6_OUTP    (0x01 << 12)
 238 #define S3C2410_GPB6_nXBREQ  (0x02 << 12)
 239 #define S3C2400_GPB6_DATA22  (0x02 << 12)
 240 #define S3C2400_GPB6_nRTS1   (0x03 << 12)
 241
 242 #define S3C2410_GPB7         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
 243 #define S3C2410_GPB7_INP     (0x00 << 14)
 244 #define S3C2410_GPB7_OUTP    (0x01 << 14)
 245 #define S3C2410_GPB7_nXDACK1 (0x02 << 14)
 246 #define S3C2400_GPB7_DATA23  (0x02 << 14)
 247
 248 #define S3C2410_GPB8         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
 249 #define S3C2410_GPB8_INP     (0x00 << 16)
 250 #define S3C2410_GPB8_OUTP    (0x01 << 16)
 251 #define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
 252 #define S3C2400_GPB8_DATA24  (0x02 << 16)
 253
 254 #define S3C2410_GPB9         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
 255 #define S3C2410_GPB9_INP     (0x00 << 18)
 256 #define S3C2410_GPB9_OUTP    (0x01 << 18)
 257 #define S3C2410_GPB9_nXDACK0 (0x02 << 18)
 258 #define S3C2400_GPB9_DATA25  (0x02 << 18)
 259 #define S3C2400_GPB9_I2SSDI  (0x03 << 18)
 260
 261 #define S3C2410_GPB10        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
 262 #define S3C2410_GPB10_INP    (0x00 << 20)
 263 #define S3C2410_GPB10_OUTP   (0x01 << 20)
 264 #define S3C2410_GPB10_nXDRE0 (0x02 << 20)
 265 #define S3C2400_GPB10_DATA26 (0x02 << 20)
 266 #define S3C2400_GPB10_nSS    (0x03 << 20)
 267
 268 #define S3C2400_GPB11        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)
 269 #define S3C2400_GPB11_INP    (0x00 << 22)
 270 #define S3C2400_GPB11_OUTP   (0x01 << 22)
 271 #define S3C2400_GPB11_DATA27 (0x02 << 22)
 272
 273 #define S3C2400_GPB12        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)
 274 #define S3C2400_GPB12_INP    (0x00 << 24)
 275 #define S3C2400_GPB12_OUTP   (0x01 << 24)
 276 #define S3C2400_GPB12_DATA28 (0x02 << 24)
 277
 278 #define S3C2400_GPB13        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)
 279 #define S3C2400_GPB13_INP    (0x00 << 26)
 280 #define S3C2400_GPB13_OUTP   (0x01 << 26)
 281 #define S3C2400_GPB13_DATA29 (0x02 << 26)
 282
 283 #define S3C2400_GPB14        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)
 284 #define S3C2400_GPB14_INP    (0x00 << 28)
 285 #define S3C2400_GPB14_OUTP   (0x01 << 28)
 286 #define S3C2400_GPB14_DATA30 (0x02 << 28)
 287
 288 #define S3C2400_GPB15        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)
 289 #define S3C2400_GPB15_INP    (0x00 << 30)
 290 #define S3C2400_GPB15_OUTP   (0x01 << 30)
 291 #define S3C2400_GPB15_DATA31 (0x02 << 30)
 292
 293 #define S3C2410_GPB_PUPDIS(x)  (1<<(x))
 294
 295 /* Port C consits of 16 GPIO/Special function
 296  *
 297  * almost identical setup to port b, but the special functions are mostly
 298  * to do with the video system's sync/etc.
 299 */
 300
 301 #define S3C2410_GPCCON     S3C2410_GPIOREG(0x20)
 302 #define S3C2410_GPCDAT     S3C2410_GPIOREG(0x24)
 303 #define S3C2410_GPCUP      S3C2410_GPIOREG(0x28)
 304
 305 #define S3C2400_GPCCON     S3C2410_GPIOREG(0x14)
 306 #define S3C2400_GPCDAT     S3C2410_GPIOREG(0x18)
 307 #define S3C2400_GPCUP      S3C2410_GPIOREG(0x1C)
 308
 309 #define S3C2410_GPC0            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
 310 #define S3C2410_GPC0_INP        (0x00 << 0)
 311 #define S3C2410_GPC0_OUTP       (0x01 << 0)
 312 #define S3C2410_GPC0_LEND       (0x02 << 0)
 313 #define S3C2400_GPC0_VD0        (0x02 << 0)
 314
 315 #define S3C2410_GPC1            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
 316 #define S3C2410_GPC1_INP        (0x00 << 2)
 317 #define S3C2410_GPC1_OUTP       (0x01 << 2)
 318 #define S3C2410_GPC1_VCLK       (0x02 << 2)
 319 #define S3C2400_GPC1_VD1        (0x02 << 2)
 320
 321 #define S3C2410_GPC2            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
 322 #define S3C2410_GPC2_INP        (0x00 << 4)
 323 #define S3C2410_GPC2_OUTP       (0x01 << 4)
 324 #define S3C2410_GPC2_VLINE      (0x02 << 4)
 325 #define S3C2400_GPC2_VD2        (0x02 << 4)
 326
 327 #define S3C2410_GPC3            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
 328 #define S3C2410_GPC3_INP        (0x00 << 6)
 329 #define S3C2410_GPC3_OUTP       (0x01 << 6)
 330 #define S3C2410_GPC3_VFRAME     (0x02 << 6)
 331 #define S3C2400_GPC3_VD3        (0x02 << 6)
 332
 333 #define S3C2410_GPC4            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
 334 #define S3C2410_GPC4_INP        (0x00 << 8)
 335 #define S3C2410_GPC4_OUTP       (0x01 << 8)
 336 #define S3C2410_GPC4_VM         (0x02 << 8)
 337 #define S3C2400_GPC4_VD4        (0x02 << 8)
 338
 339 #define S3C2410_GPC5            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
 340 #define S3C2410_GPC5_INP        (0x00 << 10)
 341 #define S3C2410_GPC5_OUTP       (0x01 << 10)
 342 #define S3C2410_GPC5_LCDVF0     (0x02 << 10)
 343 #define S3C2400_GPC5_VD5        (0x02 << 10)
 344
 345 #define S3C2410_GPC6            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
 346 #define S3C2410_GPC6_INP        (0x00 << 12)
 347 #define S3C2410_GPC6_OUTP       (0x01 << 12)
 348 #define S3C2410_GPC6_LCDVF1     (0x02 << 12)
 349 #define S3C2400_GPC6_VD6        (0x02 << 12)
 350
 351 #define S3C2410_GPC7            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
 352 #define S3C2410_GPC7_INP        (0x00 << 14)
 353 #define S3C2410_GPC7_OUTP       (0x01 << 14)
 354 #define S3C2410_GPC7_LCDVF2     (0x02 << 14)
 355 #define S3C2400_GPC7_VD7        (0x02 << 14)
 356
 357 #define S3C2410_GPC8            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
 358 #define S3C2410_GPC8_INP        (0x00 << 16)
 359 #define S3C2410_GPC8_OUTP       (0x01 << 16)
 360 #define S3C2410_GPC8_VD0        (0x02 << 16)
 361 #define S3C2400_GPC8_VD8        (0x02 << 16)
 362
 363 #define S3C2410_GPC9            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
 364 #define S3C2410_GPC9_INP        (0x00 << 18)
 365 #define S3C2410_GPC9_OUTP       (0x01 << 18)
 366 #define S3C2410_GPC9_VD1        (0x02 << 18)
 367 #define S3C2400_GPC9_VD9        (0x02 << 18)
 368
 369 #define S3C2410_GPC10           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
 370 #define S3C2410_GPC10_INP       (0x00 << 20)
 371 #define S3C2410_GPC10_OUTP      (0x01 << 20)
 372 #define S3C2410_GPC10_VD2       (0x02 << 20)
 373 #define S3C2400_GPC10_VD10      (0x02 << 20)
 374
 375 #define S3C2410_GPC11           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
 376 #define S3C2410_GPC11_INP       (0x00 << 22)
 377 #define S3C2410_GPC11_OUTP      (0x01 << 22)
 378 #define S3C2410_GPC11_VD3       (0x02 << 22)
 379 #define S3C2400_GPC11_VD11      (0x02 << 22)
 380
 381 #define S3C2410_GPC12           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
 382 #define S3C2410_GPC12_INP       (0x00 << 24)
 383 #define S3C2410_GPC12_OUTP      (0x01 << 24)
 384 #define S3C2410_GPC12_VD4       (0x02 << 24)
 385 #define S3C2400_GPC12_VD12      (0x02 << 24)
 386
 387 #define S3C2410_GPC13           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
 388 #define S3C2410_GPC13_INP       (0x00 << 26)
 389 #define S3C2410_GPC13_OUTP      (0x01 << 26)
 390 #define S3C2410_GPC13_VD5       (0x02 << 26)
 391 #define S3C2400_GPC13_VD13      (0x02 << 26)
 392
 393 #define S3C2410_GPC14           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
 394 #define S3C2410_GPC14_INP       (0x00 << 28)
 395 #define S3C2410_GPC14_OUTP      (0x01 << 28)
 396 #define S3C2410_GPC14_VD6       (0x02 << 28)
 397 #define S3C2400_GPC14_VD14      (0x02 << 28)
 398
 399 #define S3C2410_GPC15           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
 400 #define S3C2410_GPC15_INP       (0x00 << 30)
 401 #define S3C2410_GPC15_OUTP      (0x01 << 30)
 402 #define S3C2410_GPC15_VD7       (0x02 << 30)
 403 #define S3C2400_GPC15_VD15      (0x02 << 30)
 404
 405 #define S3C2410_GPC_PUPDIS(x)  (1<<(x))
 406
 407 /*
 408  * S3C2410: Port D consists of 16 GPIO/Special function
 409  *
 410  * almost identical setup to port b, but the special functions are mostly
 411  * to do with the video system's data.
 412  *
 413  * S3C2400: Port D consists of 11 GPIO/Special function
 414  *
 415  * almost identical setup to port c
 416 */
 417
 418 #define S3C2410_GPDCON     S3C2410_GPIOREG(0x30)
 419 #define S3C2410_GPDDAT     S3C2410_GPIOREG(0x34)
 420 #define S3C2410_GPDUP      S3C2410_GPIOREG(0x38)
 421
 422 #define S3C2400_GPDCON     S3C2410_GPIOREG(0x20)
 423 #define S3C2400_GPDDAT     S3C2410_GPIOREG(0x24)
 424 #define S3C2400_GPDUP      S3C2410_GPIOREG(0x28)
 425
 426 #define S3C2410_GPD0            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
 427 #define S3C2410_GPD0_INP        (0x00 << 0)
 428 #define S3C2410_GPD0_OUTP       (0x01 << 0)
 429 #define S3C2410_GPD0_VD8        (0x02 << 0)
 430 #define S3C2400_GPD0_VFRAME     (0x02 << 0)
 431
 432 #define S3C2410_GPD1            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
 433 #define S3C2410_GPD1_INP        (0x00 << 2)
 434 #define S3C2410_GPD1_OUTP       (0x01 << 2)
 435 #define S3C2410_GPD1_VD9        (0x02 << 2)
 436 #define S3C2400_GPD1_VM         (0x02 << 2)
 437
 438 #define S3C2410_GPD2            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
 439 #define S3C2410_GPD2_INP        (0x00 << 4)
 440 #define S3C2410_GPD2_OUTP       (0x01 << 4)
 441 #define S3C2410_GPD2_VD10       (0x02 << 4)
 442 #define S3C2400_GPD2_VLINE      (0x02 << 4)
 443
 444 #define S3C2410_GPD3            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
 445 #define S3C2410_GPD3_INP        (0x00 << 6)
 446 #define S3C2410_GPD3_OUTP       (0x01 << 6)
 447 #define S3C2410_GPD3_VD11       (0x02 << 6)
 448 #define S3C2400_GPD3_VCLK       (0x02 << 6)
 449
 450 #define S3C2410_GPD4            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
 451 #define S3C2410_GPD4_INP        (0x00 << 8)
 452 #define S3C2410_GPD4_OUTP       (0x01 << 8)
 453 #define S3C2410_GPD4_VD12       (0x02 << 8)
 454 #define S3C2400_GPD4_LEND       (0x02 << 8)
 455
 456 #define S3C2410_GPD5            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
 457 #define S3C2410_GPD5_INP        (0x00 << 10)
 458 #define S3C2410_GPD5_OUTP       (0x01 << 10)
 459 #define S3C2410_GPD5_VD13       (0x02 << 10)
 460 #define S3C2400_GPD5_TOUT0      (0x02 << 10)
 461
 462 #define S3C2410_GPD6            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
 463 #define S3C2410_GPD6_INP        (0x00 << 12)
 464 #define S3C2410_GPD6_OUTP       (0x01 << 12)
 465 #define S3C2410_GPD6_VD14       (0x02 << 12)
 466 #define S3C2400_GPD6_TOUT1      (0x02 << 12)
 467
 468 #define S3C2410_GPD7            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
 469 #define S3C2410_GPD7_INP        (0x00 << 14)
 470 #define S3C2410_GPD7_OUTP       (0x01 << 14)
 471 #define S3C2410_GPD7_VD15       (0x02 << 14)
 472 #define S3C2400_GPD7_TOUT2      (0x02 << 14)
 473
 474 #define S3C2410_GPD8            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
 475 #define S3C2410_GPD8_INP        (0x00 << 16)
 476 #define S3C2410_GPD8_OUTP       (0x01 << 16)
 477 #define S3C2410_GPD8_VD16       (0x02 << 16)
 478 #define S3C2400_GPD8_TOUT3      (0x02 << 16)
 479
 480 #define S3C2410_GPD9            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
 481 #define S3C2410_GPD9_INP        (0x00 << 18)
 482 #define S3C2410_GPD9_OUTP       (0x01 << 18)
 483 #define S3C2410_GPD9_VD17       (0x02 << 18)
 484 #define S3C2400_GPD9_TCLK0      (0x02 << 18)
 485 #define S3C2410_GPD9_MASK       (0x03 << 18)
 486
 487 #define S3C2410_GPD10           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
 488 #define S3C2410_GPD10_INP       (0x00 << 20)
 489 #define S3C2410_GPD10_OUTP      (0x01 << 20)
 490 #define S3C2410_GPD10_VD18      (0x02 << 20)
 491 #define S3C2400_GPD10_nWAIT     (0x02 << 20)
 492
 493 #define S3C2410_GPD11           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
 494 #define S3C2410_GPD11_INP       (0x00 << 22)
 495 #define S3C2410_GPD11_OUTP      (0x01 << 22)
 496 #define S3C2410_GPD11_VD19      (0x02 << 22)
 497
 498 #define S3C2410_GPD12           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
 499 #define S3C2410_GPD12_INP       (0x00 << 24)
 500 #define S3C2410_GPD12_OUTP      (0x01 << 24)
 501 #define S3C2410_GPD12_VD20      (0x02 << 24)
 502
 503 #define S3C2410_GPD13           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
 504 #define S3C2410_GPD13_INP       (0x00 << 26)
 505 #define S3C2410_GPD13_OUTP      (0x01 << 26)
 506 #define S3C2410_GPD13_VD21      (0x02 << 26)
 507
 508 #define S3C2410_GPD14           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
 509 #define S3C2410_GPD14_INP       (0x00 << 28)
 510 #define S3C2410_GPD14_OUTP      (0x01 << 28)
 511 #define S3C2410_GPD14_VD22      (0x02 << 28)
 512
 513 #define S3C2410_GPD15           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
 514 #define S3C2410_GPD15_INP       (0x00 << 30)
 515 #define S3C2410_GPD15_OUTP      (0x01 << 30)
 516 #define S3C2410_GPD15_VD23      (0x02 << 30)
 517
 518 #define S3C2410_GPD_PUPDIS(x)  (1<<(x))
 519
 520 /* S3C2410:
 521  * Port E consists of 16 GPIO/Special function
 522  *
 523  * again, the same as port B, but dealing with I2S, SDI, and
 524  * more miscellaneous functions
 525  *
 526  * S3C2400:
 527  * Port E consists of 12 GPIO/Special function
 528  *
 529  * GPIO / interrupt inputs
 530 */
 531
 532 #define S3C2410_GPECON     S3C2410_GPIOREG(0x40)
 533 #define S3C2410_GPEDAT     S3C2410_GPIOREG(0x44)
 534 #define S3C2410_GPEUP      S3C2410_GPIOREG(0x48)
 535
 536 #define S3C2400_GPECON     S3C2410_GPIOREG(0x2C)
 537 #define S3C2400_GPEDAT     S3C2410_GPIOREG(0x30)
 538 #define S3C2400_GPEUP      S3C2410_GPIOREG(0x34)
 539
 540 #define S3C2410_GPE0           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
 541 #define S3C2410_GPE0_INP       (0x00 << 0)
 542 #define S3C2410_GPE0_OUTP      (0x01 << 0)
 543 #define S3C2410_GPE0_I2SLRCK   (0x02 << 0)
 544 #define S3C2400_GPE0_EINT0     (0x02 << 0)
 545 #define S3C2410_GPE0_MASK      (0x03 << 0)
 546
 547 #define S3C2410_GPE1           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
 548 #define S3C2410_GPE1_INP       (0x00 << 2)
 549 #define S3C2410_GPE1_OUTP      (0x01 << 2)
 550 #define S3C2410_GPE1_I2SSCLK   (0x02 << 2)
 551 #define S3C2400_GPE1_EINT1     (0x02 << 2)
 552 #define S3C2400_GPE1_nSS       (0x03 << 2)
 553 #define S3C2410_GPE1_MASK      (0x03 << 2)
 554
 555 #define S3C2410_GPE2           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
 556 #define S3C2410_GPE2_INP       (0x00 << 4)
 557 #define S3C2410_GPE2_OUTP      (0x01 << 4)
 558 #define S3C2410_GPE2_CDCLK     (0x02 << 4)
 559 #define S3C2400_GPE2_EINT2     (0x02 << 4)
 560 #define S3C2400_GPE2_I2SSDI    (0x03 << 4)
 561
 562 #define S3C2410_GPE3           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
 563 #define S3C2410_GPE3_INP       (0x00 << 6)
 564 #define S3C2410_GPE3_OUTP      (0x01 << 6)
 565 #define S3C2410_GPE3_I2SSDI    (0x02 << 6)
 566 #define S3C2400_GPE3_EINT3     (0x02 << 6)
 567 #define S3C2400_GPE3_nCTS1     (0x03 << 6)
 568 #define S3C2410_GPE3_nSS0      (0x03 << 6)
 569 #define S3C2410_GPE3_MASK      (0x03 << 6)
 570
 571 #define S3C2410_GPE4           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
 572 #define S3C2410_GPE4_INP       (0x00 << 8)
 573 #define S3C2410_GPE4_OUTP      (0x01 << 8)
 574 #define S3C2410_GPE4_I2SSDO    (0x02 << 8)
 575 #define S3C2400_GPE4_EINT4     (0x02 << 8)
 576 #define S3C2400_GPE4_nRTS1     (0x03 << 8)
 577 #define S3C2410_GPE4_I2SSDI    (0x03 << 8)
 578 #define S3C2410_GPE4_MASK      (0x03 << 8)
 579
 580 #define S3C2410_GPE5           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
 581 #define S3C2410_GPE5_INP       (0x00 << 10)
 582 #define S3C2410_GPE5_OUTP      (0x01 << 10)
 583 #define S3C2410_GPE5_SDCLK     (0x02 << 10)
 584 #define S3C2400_GPE5_EINT5     (0x02 << 10)
 585 #define S3C2400_GPE5_TCLK1     (0x03 << 10)
 586
 587 #define S3C2410_GPE6           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
 588 #define S3C2410_GPE6_INP       (0x00 << 12)
 589 #define S3C2410_GPE6_OUTP      (0x01 << 12)
 590 #define S3C2410_GPE6_SDCMD     (0x02 << 12)
 591 #define S3C2400_GPE6_EINT6     (0x02 << 12)
 592
 593 #define S3C2410_GPE7           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
 594 #define S3C2410_GPE7_INP       (0x00 << 14)
 595 #define S3C2410_GPE7_OUTP      (0x01 << 14)
 596 #define S3C2410_GPE7_SDDAT0    (0x02 << 14)
 597 #define S3C2400_GPE7_EINT7     (0x02 << 14)
 598
 599 #define S3C2410_GPE8           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
 600 #define S3C2410_GPE8_INP       (0x00 << 16)
 601 #define S3C2410_GPE8_OUTP      (0x01 << 16)
 602 #define S3C2410_GPE8_SDDAT1    (0x02 << 16)
 603 #define S3C2400_GPE8_nXDACK0   (0x02 << 16)
 604
 605 #define S3C2410_GPE9           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
 606 #define S3C2410_GPE9_INP       (0x00 << 18)
 607 #define S3C2410_GPE9_OUTP      (0x01 << 18)
 608 #define S3C2410_GPE9_SDDAT2    (0x02 << 18)
 609 #define S3C2400_GPE9_nXDACK1   (0x02 << 18)
 610 #define S3C2400_GPE9_nXBACK    (0x03 << 18)
 611
 612 #define S3C2410_GPE10          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
 613 #define S3C2410_GPE10_INP      (0x00 << 20)
 614 #define S3C2410_GPE10_OUTP     (0x01 << 20)
 615 #define S3C2410_GPE10_SDDAT3   (0x02 << 20)
 616 #define S3C2400_GPE10_nXDREQ0  (0x02 << 20)
 617
 618 #define S3C2410_GPE11          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
 619 #define S3C2410_GPE11_INP      (0x00 << 22)
 620 #define S3C2410_GPE11_OUTP     (0x01 << 22)
 621 #define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
 622 #define S3C2400_GPE11_nXDREQ1  (0x02 << 22)
 623 #define S3C2400_GPE11_nXBREQ   (0x03 << 22)
 624
 625 #define S3C2410_GPE12          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
 626 #define S3C2410_GPE12_INP      (0x00 << 24)
 627 #define S3C2410_GPE12_OUTP     (0x01 << 24)
 628 #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
 629
 630 #define S3C2410_GPE13          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
 631 #define S3C2410_GPE13_INP      (0x00 << 26)
 632 #define S3C2410_GPE13_OUTP     (0x01 << 26)
 633 #define S3C2410_GPE13_SPICLK0  (0x02 << 26)
 634
 635 #define S3C2410_GPE14          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
 636 #define S3C2410_GPE14_INP      (0x00 << 28)
 637 #define S3C2410_GPE14_OUTP     (0x01 << 28)
 638 #define S3C2410_GPE14_IICSCL   (0x02 << 28)
 639 #define S3C2410_GPE14_MASK     (0x03 << 28)
 640
 641 #define S3C2410_GPE15          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
 642 #define S3C2410_GPE15_INP      (0x00 << 30)
 643 #define S3C2410_GPE15_OUTP     (0x01 << 30)
 644 #define S3C2410_GPE15_IICSDA   (0x02 << 30)
 645 #define S3C2410_GPE15_MASK     (0x03 << 30)
 646
 647 #define S3C2440_GPE0_ACSYNC    (0x03 << 0)
 648 #define S3C2440_GPE1_ACBITCLK  (0x03 << 2)
 649 #define S3C2440_GPE2_ACRESET   (0x03 << 4)
 650 #define S3C2440_GPE3_ACIN      (0x03 << 6)
 651 #define S3C2440_GPE4_ACOUT     (0x03 << 8)
 652
 653 #define S3C2410_GPE_PUPDIS(x)  (1<<(x))
 654
 655 /* S3C2410:
 656  * Port F consists of 8 GPIO/Special function
 657  *
 658  * GPIO / interrupt inputs
 659  *
 660  * GPFCON has 2 bits for each of the input pins on port F
 661  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
 662  *
 663  * pull up works like all other ports.
 664  *
 665  * S3C2400:
 666  * Port F consists of 7 GPIO/Special function
 667  *
 668  * GPIO/serial/misc pins
 669 */
 670
 671 #define S3C2410_GPFCON     S3C2410_GPIOREG(0x50)
 672 #define S3C2410_GPFDAT     S3C2410_GPIOREG(0x54)
 673 #define S3C2410_GPFUP      S3C2410_GPIOREG(0x58)
 674
 675 #define S3C2400_GPFCON     S3C2410_GPIOREG(0x38)
 676 #define S3C2400_GPFDAT     S3C2410_GPIOREG(0x3C)
 677 #define S3C2400_GPFUP      S3C2410_GPIOREG(0x40)
 678
 679 #define S3C2410_GPF0        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
 680 #define S3C2410_GPF0_INP    (0x00 << 0)
 681 #define S3C2410_GPF0_OUTP   (0x01 << 0)
 682 #define S3C2410_GPF0_EINT0  (0x02 << 0)
 683 #define S3C2400_GPF0_RXD0   (0x02 << 0)
 684
 685 #define S3C2410_GPF1        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
 686 #define S3C2410_GPF1_INP    (0x00 << 2)
 687 #define S3C2410_GPF1_OUTP   (0x01 << 2)
 688 #define S3C2410_GPF1_EINT1  (0x02 << 2)
 689 #define S3C2400_GPF1_RXD1   (0x02 << 2)
 690 #define S3C2400_GPF1_IICSDA (0x03 << 2)
 691
 692 #define S3C2410_GPF2        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
 693 #define S3C2410_GPF2_INP    (0x00 << 4)
 694 #define S3C2410_GPF2_OUTP   (0x01 << 4)
 695 #define S3C2410_GPF2_EINT2  (0x02 << 4)
 696 #define S3C2400_GPF2_TXD0   (0x02 << 4)
 697
 698 #define S3C2410_GPF3        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
 699 #define S3C2410_GPF3_INP    (0x00 << 6)
 700 #define S3C2410_GPF3_OUTP   (0x01 << 6)
 701 #define S3C2410_GPF3_EINT3  (0x02 << 6)
 702 #define S3C2400_GPF3_TXD1   (0x02 << 6)
 703 #define S3C2400_GPF3_IICSCL (0x03 << 6)
 704
 705 #define S3C2410_GPF4        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
 706 #define S3C2410_GPF4_INP    (0x00 << 8)
 707 #define S3C2410_GPF4_OUTP   (0x01 << 8)
 708 #define S3C2410_GPF4_EINT4  (0x02 << 8)
 709 #define S3C2400_GPF4_nRTS0  (0x02 << 8)
 710 #define S3C2400_GPF4_nXBACK (0x03 << 8)
 711
 712 #define S3C2410_GPF5        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
 713 #define S3C2410_GPF5_INP    (0x00 << 10)
 714 #define S3C2410_GPF5_OUTP   (0x01 << 10)
 715 #define S3C2410_GPF5_EINT5  (0x02 << 10)
 716 #define S3C2400_GPF5_nCTS0  (0x02 << 10)
 717 #define S3C2400_GPF5_nXBREQ (0x03 << 10)
 718
 719 #define S3C2410_GPF6        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
 720 #define S3C2410_GPF6_INP    (0x00 << 12)
 721 #define S3C2410_GPF6_OUTP   (0x01 << 12)
 722 #define S3C2410_GPF6_EINT6  (0x02 << 12)
 723 #define S3C2400_GPF6_CLKOUT (0x02 << 12)
 724
 725 #define S3C2410_GPF7        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
 726 #define S3C2410_GPF7_INP    (0x00 << 14)
 727 #define S3C2410_GPF7_OUTP   (0x01 << 14)
 728 #define S3C2410_GPF7_EINT7  (0x02 << 14)
 729
 730 #define S3C2410_GPF_PUPDIS(x)  (1<<(x))
 731
 732 /* S3C2410:
 733  * Port G consists of 8 GPIO/IRQ/Special function
 734  *
 735  * GPGCON has 2 bits for each of the input pins on port F
 736  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
 737  *
 738  * pull up works like all other ports.
 739  *
 740  * S3C2400:
 741  * Port G consists of 10 GPIO/Special function
 742 */
 743
 744 #define S3C2410_GPGCON     S3C2410_GPIOREG(0x60)
 745 #define S3C2410_GPGDAT     S3C2410_GPIOREG(0x64)
 746 #define S3C2410_GPGUP      S3C2410_GPIOREG(0x68)
 747
 748 #define S3C2400_GPGCON     S3C2410_GPIOREG(0x44)
 749 #define S3C2400_GPGDAT     S3C2410_GPIOREG(0x48)
 750 #define S3C2400_GPGUP      S3C2410_GPIOREG(0x4C)
 751
 752 #define S3C2410_GPG0          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
 753 #define S3C2410_GPG0_INP      (0x00 << 0)
 754 #define S3C2410_GPG0_OUTP     (0x01 << 0)
 755 #define S3C2410_GPG0_EINT8    (0x02 << 0)
 756 #define S3C2400_GPG0_I2SLRCK  (0x02 << 0)
 757
 758 #define S3C2410_GPG1          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
 759 #define S3C2410_GPG1_INP      (0x00 << 2)
 760 #define S3C2410_GPG1_OUTP     (0x01 << 2)
 761 #define S3C2410_GPG1_EINT9    (0x02 << 2)
 762 #define S3C2400_GPG1_I2SSCLK  (0x02 << 2)
 763
 764 #define S3C2410_GPG2          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
 765 #define S3C2410_GPG2_INP      (0x00 << 4)
 766 #define S3C2410_GPG2_OUTP     (0x01 << 4)
 767 #define S3C2410_GPG2_EINT10   (0x02 << 4)
 768 #define S3C2400_GPG2_CDCLK    (0x02 << 4)
 769
 770 #define S3C2410_GPG3          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
 771 #define S3C2410_GPG3_INP      (0x00 << 6)
 772 #define S3C2410_GPG3_OUTP     (0x01 << 6)
 773 #define S3C2410_GPG3_EINT11   (0x02 << 6)
 774 #define S3C2400_GPG3_I2SSDO   (0x02 << 6)
 775 #define S3C2400_GPG3_I2SSDI   (0x03 << 6)
 776
 777 #define S3C2410_GPG4          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
 778 #define S3C2410_GPG4_INP      (0x00 << 8)
 779 #define S3C2410_GPG4_OUTP     (0x01 << 8)
 780 #define S3C2410_GPG4_EINT12   (0x02 << 8)
 781 #define S3C2400_GPG4_MMCCLK   (0x02 << 8)
 782 #define S3C2400_GPG4_I2SSDI   (0x03 << 8)
 783 #define S3C2410_GPG4_LCDPWREN (0x03 << 8)
 784
 785 #define S3C2410_GPG5          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
 786 #define S3C2410_GPG5_INP      (0x00 << 10)
 787 #define S3C2410_GPG5_OUTP     (0x01 << 10)
 788 #define S3C2410_GPG5_EINT13   (0x02 << 10)
 789 #define S3C2400_GPG5_MMCCMD   (0x02 << 10)
 790 #define S3C2400_GPG5_IICSDA   (0x03 << 10)
 791 #define S3C2410_GPG5_SPIMISO1 (0x03 << 10)
 792
 793 #define S3C2410_GPG6          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
 794 #define S3C2410_GPG6_INP      (0x00 << 12)
 795 #define S3C2410_GPG6_OUTP     (0x01 << 12)
 796 #define S3C2410_GPG6_EINT14   (0x02 << 12)
 797 #define S3C2400_GPG6_MMCDAT   (0x02 << 12)
 798 #define S3C2400_GPG6_IICSCL   (0x03 << 12)
 799 #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
 800
 801 #define S3C2410_GPG7          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
 802 #define S3C2410_GPG7_INP      (0x00 << 14)
 803 #define S3C2410_GPG7_OUTP     (0x01 << 14)
 804 #define S3C2410_GPG7_EINT15   (0x02 << 14)
 805 #define S3C2410_GPG7_SPICLK1  (0x03 << 14)
 806 #define S3C2400_GPG7_SPIMISO  (0x02 << 14)
 807 #define S3C2400_GPG7_IICSDA   (0x03 << 14)
 808
 809 #define S3C2410_GPG8          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
 810 #define S3C2410_GPG8_INP      (0x00 << 16)
 811 #define S3C2410_GPG8_OUTP     (0x01 << 16)
 812 #define S3C2410_GPG8_EINT16   (0x02 << 16)
 813 #define S3C2400_GPG8_SPIMOSI  (0x02 << 16)
 814 #define S3C2400_GPG8_IICSCL   (0x03 << 16)
 815
 816 #define S3C2410_GPG9          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
 817 #define S3C2410_GPG9_INP      (0x00 << 18)
 818 #define S3C2410_GPG9_OUTP     (0x01 << 18)
 819 #define S3C2410_GPG9_EINT17   (0x02 << 18)
 820 #define S3C2400_GPG9_SPICLK   (0x02 << 18)
 821 #define S3C2400_GPG9_MMCCLK   (0x03 << 18)
 822
 823 #define S3C2410_GPG10         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
 824 #define S3C2410_GPG10_INP     (0x00 << 20)
 825 #define S3C2410_GPG10_OUTP    (0x01 << 20)
 826 #define S3C2410_GPG10_EINT18  (0x02 << 20)
 827
 828 #define S3C2410_GPG11         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
 829 #define S3C2410_GPG11_INP     (0x00 << 22)
 830 #define S3C2410_GPG11_OUTP    (0x01 << 22)
 831 #define S3C2410_GPG11_EINT19  (0x02 << 22)
 832 #define S3C2410_GPG11_TCLK1   (0x03 << 22)
 833
 834 #define S3C2410_GPG12         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
 835 #define S3C2410_GPG12_INP     (0x00 << 24)
 836 #define S3C2410_GPG12_OUTP    (0x01 << 24)
 837 #define S3C2410_GPG12_EINT20  (0x02 << 24)
 838 #define S3C2410_GPG12_XMON    (0x03 << 24)
 839
 840 #define S3C2410_GPG13         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
 841 #define S3C2410_GPG13_INP     (0x00 << 26)
 842 #define S3C2410_GPG13_OUTP    (0x01 << 26)
 843 #define S3C2410_GPG13_EINT21  (0x02 << 26)
 844 #define S3C2410_GPG13_nXPON   (0x03 << 26)
 845
 846 #define S3C2410_GPG14         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
 847 #define S3C2410_GPG14_INP     (0x00 << 28)
 848 #define S3C2410_GPG14_OUTP    (0x01 << 28)
 849 #define S3C2410_GPG14_EINT22  (0x02 << 28)
 850 #define S3C2410_GPG14_YMON    (0x03 << 28)
 851
 852 #define S3C2410_GPG15         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
 853 #define S3C2410_GPG15_INP     (0x00 << 30)
 854 #define S3C2410_GPG15_OUTP    (0x01 << 30)
 855 #define S3C2410_GPG15_EINT23  (0x02 << 30)
 856 #define S3C2410_GPG15_nYPON   (0x03 << 30)
 857
 858
 859 #define S3C2410_GPG_PUPDIS(x)  (1<<(x))
 860
 861 /* Port H consists of11 GPIO/serial/Misc pins
 862  *
 863  * GPGCON has 2 bits for each of the input pins on port F
 864  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
 865  *
 866  * pull up works like all other ports.
 867 */
 868
 869 #define S3C2410_GPHCON     S3C2410_GPIOREG(0x70)
 870 #define S3C2410_GPHDAT     S3C2410_GPIOREG(0x74)
 871 #define S3C2410_GPHUP      S3C2410_GPIOREG(0x78)
 872
 873 #define S3C2410_GPH0        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
 874 #define S3C2410_GPH0_INP    (0x00 << 0)
 875 #define S3C2410_GPH0_OUTP   (0x01 << 0)
 876 #define S3C2410_GPH0_nCTS0  (0x02 << 0)
 877
 878 #define S3C2410_GPH1        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
 879 #define S3C2410_GPH1_INP    (0x00 << 2)
 880 #define S3C2410_GPH1_OUTP   (0x01 << 2)
 881 #define S3C2410_GPH1_nRTS0  (0x02 << 2)
 882
 883 #define S3C2410_GPH2        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
 884 #define S3C2410_GPH2_INP    (0x00 << 4)
 885 #define S3C2410_GPH2_OUTP   (0x01 << 4)
 886 #define S3C2410_GPH2_TXD0   (0x02 << 4)
 887
 888 #define S3C2410_GPH3        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
 889 #define S3C2410_GPH3_INP    (0x00 << 6)
 890 #define S3C2410_GPH3_OUTP   (0x01 << 6)
 891 #define S3C2410_GPH3_RXD0   (0x02 << 6)
 892
 893 #define S3C2410_GPH4        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
 894 #define S3C2410_GPH4_INP    (0x00 << 8)
 895 #define S3C2410_GPH4_OUTP   (0x01 << 8)
 896 #define S3C2410_GPH4_TXD1   (0x02 << 8)
 897
 898 #define S3C2410_GPH5        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
 899 #define S3C2410_GPH5_INP    (0x00 << 10)
 900 #define S3C2410_GPH5_OUTP   (0x01 << 10)
 901 #define S3C2410_GPH5_RXD1   (0x02 << 10)
 902
 903 #define S3C2410_GPH6        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
 904 #define S3C2410_GPH6_INP    (0x00 << 12)
 905 #define S3C2410_GPH6_OUTP   (0x01 << 12)
 906 #define S3C2410_GPH6_TXD2   (0x02 << 12)
 907 #define S3C2410_GPH6_nRTS1  (0x03 << 12)
 908
 909 #define S3C2410_GPH7        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
 910 #define S3C2410_GPH7_INP    (0x00 << 14)
 911 #define S3C2410_GPH7_OUTP   (0x01 << 14)
 912 #define S3C2410_GPH7_RXD2   (0x02 << 14)
 913 #define S3C2410_GPH7_nCTS1  (0x03 << 14)
 914
 915 #define S3C2410_GPH8        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
 916 #define S3C2410_GPH8_INP    (0x00 << 16)
 917 #define S3C2410_GPH8_OUTP   (0x01 << 16)
 918 #define S3C2410_GPH8_UCLK   (0x02 << 16)
 919
 920 #define S3C2410_GPH9          S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
 921 #define S3C2410_GPH9_INP      (0x00 << 18)
 922 #define S3C2410_GPH9_OUTP     (0x01 << 18)
 923 #define S3C2410_GPH9_CLKOUT0  (0x02 << 18)
 924
 925 #define S3C2410_GPH10         S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
 926 #define S3C2410_GPH10_INP     (0x00 << 20)
 927 #define S3C2410_GPH10_OUTP    (0x01 << 20)
 928 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
 929
 930 /* miscellaneous control */
 931 #define S3C2400_MISCCR     S3C2410_GPIOREG(0x54)
 932 #define S3C2410_MISCCR     S3C2410_GPIOREG(0x80)
 933 #define S3C2410_DCLKCON    S3C2410_GPIOREG(0x84)
 934
 935 /* see clock.h for dclk definitions */
 936
 937 /* pullup control on databus */
 938 #define S3C2410_MISCCR_SPUCR_HEN    (0<<0)
 939 #define S3C2410_MISCCR_SPUCR_HDIS   (1<<0)
 940 #define S3C2410_MISCCR_SPUCR_LEN    (0<<1)
 941 #define S3C2410_MISCCR_SPUCR_LDIS   (1<<1)
 942
 943 #define S3C2400_MISCCR_SPUCR_LEN    (0<<0)
 944 #define S3C2400_MISCCR_SPUCR_LDIS   (1<<0)
 945 #define S3C2400_MISCCR_SPUCR_HEN    (0<<1)
 946 #define S3C2400_MISCCR_SPUCR_HDIS   (1<<1)
 947
 948 #define S3C2400_MISCCR_HZ_STOPEN    (0<<2)
 949 #define S3C2400_MISCCR_HZ_STOPPREV  (1<<2)
 950
 951 #define S3C2410_MISCCR_USBDEV       (0<<3)
 952 #define S3C2410_MISCCR_USBHOST      (1<<3)
 953
 954 #define S3C2410_MISCCR_CLK0_MPLL    (0<<4)
 955 #define S3C2410_MISCCR_CLK0_UPLL    (1<<4)
 956 #define S3C2410_MISCCR_CLK0_FCLK    (2<<4)
 957 #define S3C2410_MISCCR_CLK0_HCLK    (3<<4)
 958 #define S3C2410_MISCCR_CLK0_PCLK    (4<<4)
 959 #define S3C2410_MISCCR_CLK0_DCLK0   (5<<4)
 960
 961 #define S3C2410_MISCCR_CLK1_MPLL    (0<<8)
 962 #define S3C2410_MISCCR_CLK1_UPLL    (1<<8)
 963 #define S3C2410_MISCCR_CLK1_FCLK    (2<<8)
 964 #define S3C2410_MISCCR_CLK1_HCLK    (3<<8)
 965 #define S3C2410_MISCCR_CLK1_PCLK    (4<<8)
 966 #define S3C2410_MISCCR_CLK1_DCLK1   (5<<8)
 967
 968 #define S3C2410_MISCCR_USBSUSPND0   (1<<12)
 969 #define S3C2410_MISCCR_USBSUSPND1   (1<<13)
 970
 971 #define S3C2410_MISCCR_nRSTCON      (1<<16)
 972
 973 #define S3C2410_MISCCR_nEN_SCLK0    (1<<17)
 974 #define S3C2410_MISCCR_nEN_SCLK1    (1<<18)
 975 #define S3C2410_MISCCR_nEN_SCLKE    (1<<19)
 976 #define S3C2410_MISCCR_SDSLEEP      (7<<17)
 977
 978 /* external interrupt control... */
 979 /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
 980  * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
 981  * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
 982  *
 983  * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
 984  *
 985  * Samsung datasheet p9-25
 986 */
 987 #define S3C2400_EXTINT0    S3C2410_GPIOREG(0x58)
 988 #define S3C2410_EXTINT0    S3C2410_GPIOREG(0x88)
 989 #define S3C2410_EXTINT1    S3C2410_GPIOREG(0x8C)
 990 #define S3C2410_EXTINT2    S3C2410_GPIOREG(0x90)
 991
 992 /* values for S3C2410_EXTINT0/1/2 */
 993 #define S3C2410_EXTINT_LOWLEV    (0x00)
 994 #define S3C2410_EXTINT_HILEV     (0x01)
 995 #define S3C2410_EXTINT_FALLEDGE  (0x02)
 996 #define S3C2410_EXTINT_RISEEDGE  (0x04)
 997 #define S3C2410_EXTINT_BOTHEDGE  (0x06)
 998
 999 /* interrupt filtering conrrol for EINT16..EINT23 */
1000 #define S3C2410_EINFLT0    S3C2410_GPIOREG(0x94)
1001 #define S3C2410_EINFLT1    S3C2410_GPIOREG(0x98)
1002 #define S3C2410_EINFLT2    S3C2410_GPIOREG(0x9C)
1003 #define S3C2410_EINFLT3    S3C2410_GPIOREG(0xA0)
1004
1005 /* values for interrupt filtering */
1006 #define S3C2410_EINTFLT_PCLK            (0x00)
1007 #define S3C2410_EINTFLT_EXTCLK          (1<<7)
1008 #define S3C2410_EINTFLT_WIDTHMSK(x)     ((x) & 0x3f)
1009
1010 /* removed EINTxxxx defs from here, not meant for this */
1011
1012 /* GSTATUS have miscellaneous information in them
1013  *
1014  */
1015
1016 #define S3C2410_GSTATUS0   S3C2410_GPIOREG(0x0AC)
1017 #define S3C2410_GSTATUS1   S3C2410_GPIOREG(0x0B0)
1018 #define S3C2410_GSTATUS2   S3C2410_GPIOREG(0x0B4)
1019 #define S3C2410_GSTATUS3   S3C2410_GPIOREG(0x0B8)
1020 #define S3C2410_GSTATUS4   S3C2410_GPIOREG(0x0BC)
1021
1022 #define S3C2410_GSTATUS0_nWAIT     (1<<3)
1023 #define S3C2410_GSTATUS0_NCON      (1<<2)
1024 #define S3C2410_GSTATUS0_RnB       (1<<1)
1025 #define S3C2410_GSTATUS0_nBATTFLT  (1<<0)
1026
1027 #define S3C2410_GSTATUS1_IDMASK    (0xffff0000)
1028 #define S3C2410_GSTATUS1_2410      (0x32410000)
1029 #define S3C2410_GSTATUS1_2440      (0x32440000)
1030
1031 #define S3C2410_GSTATUS2_WTRESET   (1<<2)
1032 #define S3C2410_GSTATUS2_OFFRESET  (1<<1)
1033 #define S3C2410_GSTATUS2_PONRESET  (1<<0)
1034
1035 /* open drain control register */
1036 #define S3C2400_OPENCR     S3C2410_GPIOREG(0x50)
1037
1038 #define S3C2400_OPENCR_OPC_RXD1DIS  (0<<0)
1039 #define S3C2400_OPENCR_OPC_RXD1EN   (1<<0)
1040 #define S3C2400_OPENCR_OPC_TXD1DIS  (0<<1)
1041 #define S3C2400_OPENCR_OPC_TXD1EN   (1<<1)
1042 #define S3C2400_OPENCR_OPC_CMDDIS   (0<<2)
1043 #define S3C2400_OPENCR_OPC_CMDEN    (1<<2)
1044 #define S3C2400_OPENCR_OPC_DATDIS   (0<<3)
1045 #define S3C2400_OPENCR_OPC_DATEN    (1<<3)
1046 #define S3C2400_OPENCR_OPC_MISODIS  (0<<4)
1047 #define S3C2400_OPENCR_OPC_MISOEN   (1<<4)
1048 #define S3C2400_OPENCR_OPC_MOSIDIS  (0<<5)
1049 #define S3C2400_OPENCR_OPC_MOSIEN   (1<<5)
1050
1051 #endif  /* __ASM_ARCH_REGS_GPIO_H */
1052