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[ARM] 3635/1: S3C24XX: Add S3C2412 core cpu support
[linux-2.6/openmoko-kernel/knife-kernel.git] / arch / ppc / syslib / mpc85xx_devices.c
blob7735336f5b8f51b758587053736c0f18ffad9ae9
1 /*
2 * MPC85xx Device descriptions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/serial_8250.h>
18 #include <linux/fsl_devices.h>
19 #include <asm/mpc85xx.h>
20 #include <asm/irq.h>
21 #include <asm/ppc_sys.h>
22
23 /* We use offsets for IORESOURCE_MEM since we do not know at compile time
24 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
25 */
26 struct gianfar_mdio_data mpc85xx_mdio_pdata = {
27 };
28
29 static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
30 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
31 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
32 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
33 };
34
35 static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
36 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
37 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
38 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
39 };
40
41 static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
42 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
43 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
44 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
45 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
46 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
47 };
48
49 static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
50 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
51 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
52 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
53 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
54 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
55 };
56
57 static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
58 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
59 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
60 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
61 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
62 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
63 };
64
65 static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
66 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
67 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
68 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
69 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
70 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
71 };
72
73 static struct gianfar_platform_data mpc85xx_fec_pdata = {
74 .device_flags = 0,
75 };
76
77 static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
78 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
79 };
80
81 static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
82 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
83 };
84
85 static struct plat_serial8250_port serial_platform_data[] = {
86 [0] = {
87 .mapbase = 0x4500,
88 .irq = MPC85xx_IRQ_DUART,
89 .iotype = UPIO_MEM,
90 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
91 },
92 [1] = {
93 .mapbase = 0x4600,
94 .irq = MPC85xx_IRQ_DUART,
95 .iotype = UPIO_MEM,
96 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
97 },
98 { },
99 };
100
101 struct platform_device ppc_sys_platform_devices[] = {
102 [MPC85xx_TSEC1] = {
103 .name = "fsl-gianfar",
104 .id = 1,
105 .dev.platform_data = &mpc85xx_tsec1_pdata,
106 .num_resources = 4,
107 .resource = (struct resource[]) {
108 {
109 .start = MPC85xx_ENET1_OFFSET,
110 .end = MPC85xx_ENET1_OFFSET +
111 MPC85xx_ENET1_SIZE - 1,
112 .flags = IORESOURCE_MEM,
113 },
114 {
115 .name = "tx",
116 .start = MPC85xx_IRQ_TSEC1_TX,
117 .end = MPC85xx_IRQ_TSEC1_TX,
118 .flags = IORESOURCE_IRQ,
119 },
120 {
121 .name = "rx",
122 .start = MPC85xx_IRQ_TSEC1_RX,
123 .end = MPC85xx_IRQ_TSEC1_RX,
124 .flags = IORESOURCE_IRQ,
125 },
126 {
127 .name = "error",
128 .start = MPC85xx_IRQ_TSEC1_ERROR,
129 .end = MPC85xx_IRQ_TSEC1_ERROR,
130 .flags = IORESOURCE_IRQ,
131 },
132 },
133 },
134 [MPC85xx_TSEC2] = {
135 .name = "fsl-gianfar",
136 .id = 2,
137 .dev.platform_data = &mpc85xx_tsec2_pdata,
138 .num_resources = 4,
139 .resource = (struct resource[]) {
140 {
141 .start = MPC85xx_ENET2_OFFSET,
142 .end = MPC85xx_ENET2_OFFSET +
143 MPC85xx_ENET2_SIZE - 1,
144 .flags = IORESOURCE_MEM,
145 },
146 {
147 .name = "tx",
148 .start = MPC85xx_IRQ_TSEC2_TX,
149 .end = MPC85xx_IRQ_TSEC2_TX,
150 .flags = IORESOURCE_IRQ,
151 },
152 {
153 .name = "rx",
154 .start = MPC85xx_IRQ_TSEC2_RX,
155 .end = MPC85xx_IRQ_TSEC2_RX,
156 .flags = IORESOURCE_IRQ,
157 },
158 {
159 .name = "error",
160 .start = MPC85xx_IRQ_TSEC2_ERROR,
161 .end = MPC85xx_IRQ_TSEC2_ERROR,
162 .flags = IORESOURCE_IRQ,
163 },
164 },
165 },
166 [MPC85xx_FEC] = {
167 .name = "fsl-gianfar",
168 .id = 3,
169 .dev.platform_data = &mpc85xx_fec_pdata,
170 .num_resources = 2,
171 .resource = (struct resource[]) {
172 {
173 .start = MPC85xx_ENET3_OFFSET,
174 .end = MPC85xx_ENET3_OFFSET +
175 MPC85xx_ENET3_SIZE - 1,
176 .flags = IORESOURCE_MEM,
177
178 },
179 {
180 .start = MPC85xx_IRQ_FEC,
181 .end = MPC85xx_IRQ_FEC,
182 .flags = IORESOURCE_IRQ,
183 },
184 },
185 },
186 [MPC85xx_IIC1] = {
187 .name = "fsl-i2c",
188 .id = 1,
189 .dev.platform_data = &mpc85xx_fsl_i2c_pdata,
190 .num_resources = 2,
191 .resource = (struct resource[]) {
192 {
193 .start = MPC85xx_IIC1_OFFSET,
194 .end = MPC85xx_IIC1_OFFSET +
195 MPC85xx_IIC1_SIZE - 1,
196 .flags = IORESOURCE_MEM,
197 },
198 {
199 .start = MPC85xx_IRQ_IIC1,
200 .end = MPC85xx_IRQ_IIC1,
201 .flags = IORESOURCE_IRQ,
202 },
203 },
204 },
205 [MPC85xx_DMA0] = {
206 .name = "fsl-dma",
207 .id = 0,
208 .num_resources = 2,
209 .resource = (struct resource[]) {
210 {
211 .start = MPC85xx_DMA0_OFFSET,
212 .end = MPC85xx_DMA0_OFFSET +
213 MPC85xx_DMA0_SIZE - 1,
214 .flags = IORESOURCE_MEM,
215 },
216 {
217 .start = MPC85xx_IRQ_DMA0,
218 .end = MPC85xx_IRQ_DMA0,
219 .flags = IORESOURCE_IRQ,
220 },
221 },
222 },
223 [MPC85xx_DMA1] = {
224 .name = "fsl-dma",
225 .id = 1,
226 .num_resources = 2,
227 .resource = (struct resource[]) {
228 {
229 .start = MPC85xx_DMA1_OFFSET,
230 .end = MPC85xx_DMA1_OFFSET +
231 MPC85xx_DMA1_SIZE - 1,
232 .flags = IORESOURCE_MEM,
233 },
234 {
235 .start = MPC85xx_IRQ_DMA1,
236 .end = MPC85xx_IRQ_DMA1,
237 .flags = IORESOURCE_IRQ,
238 },
239 },
240 },
241 [MPC85xx_DMA2] = {
242 .name = "fsl-dma",
243 .id = 2,
244 .num_resources = 2,
245 .resource = (struct resource[]) {
246 {
247 .start = MPC85xx_DMA2_OFFSET,
248 .end = MPC85xx_DMA2_OFFSET +
249 MPC85xx_DMA2_SIZE - 1,
250 .flags = IORESOURCE_MEM,
251 },
252 {
253 .start = MPC85xx_IRQ_DMA2,
254 .end = MPC85xx_IRQ_DMA2,
255 .flags = IORESOURCE_IRQ,
256 },
257 },
258 },
259 [MPC85xx_DMA3] = {
260 .name = "fsl-dma",
261 .id = 3,
262 .num_resources = 2,
263 .resource = (struct resource[]) {
264 {
265 .start = MPC85xx_DMA3_OFFSET,
266 .end = MPC85xx_DMA3_OFFSET +
267 MPC85xx_DMA3_SIZE - 1,
268 .flags = IORESOURCE_MEM,
269 },
270 {
271 .start = MPC85xx_IRQ_DMA3,
272 .end = MPC85xx_IRQ_DMA3,
273 .flags = IORESOURCE_IRQ,
274 },
275 },
276 },
277 [MPC85xx_DUART] = {
278 .name = "serial8250",
279 .id = PLAT8250_DEV_PLATFORM,
280 .dev.platform_data = serial_platform_data,
281 },
282 [MPC85xx_PERFMON] = {
283 .name = "fsl-perfmon",
284 .id = 1,
285 .num_resources = 2,
286 .resource = (struct resource[]) {
287 {
288 .start = MPC85xx_PERFMON_OFFSET,
289 .end = MPC85xx_PERFMON_OFFSET +
290 MPC85xx_PERFMON_SIZE - 1,
291 .flags = IORESOURCE_MEM,
292 },
293 {
294 .start = MPC85xx_IRQ_PERFMON,
295 .end = MPC85xx_IRQ_PERFMON,
296 .flags = IORESOURCE_IRQ,
297 },
298 },
299 },
300 [MPC85xx_SEC2] = {
301 .name = "fsl-sec2",
302 .id = 1,
303 .num_resources = 2,
304 .resource = (struct resource[]) {
305 {
306 .start = MPC85xx_SEC2_OFFSET,
307 .end = MPC85xx_SEC2_OFFSET +
308 MPC85xx_SEC2_SIZE - 1,
309 .flags = IORESOURCE_MEM,
310 },
311 {
312 .start = MPC85xx_IRQ_SEC2,
313 .end = MPC85xx_IRQ_SEC2,
314 .flags = IORESOURCE_IRQ,
315 },
316 },
317 },
318 [MPC85xx_CPM_FCC1] = {
319 .name = "fsl-cpm-fcc",
320 .id = 1,
321 .num_resources = 3,
322 .resource = (struct resource[]) {
323 {
324 .start = 0x91300,
325 .end = 0x9131F,
326 .flags = IORESOURCE_MEM,
327 },
328 {
329 .start = 0x91380,
330 .end = 0x9139F,
331 .flags = IORESOURCE_MEM,
332 },
333 {
334 .start = SIU_INT_FCC1,
335 .end = SIU_INT_FCC1,
336 .flags = IORESOURCE_IRQ,
337 },
338 },
339 },
340 [MPC85xx_CPM_FCC2] = {
341 .name = "fsl-cpm-fcc",
342 .id = 2,
343 .num_resources = 3,
344 .resource = (struct resource[]) {
345 {
346 .start = 0x91320,
347 .end = 0x9133F,
348 .flags = IORESOURCE_MEM,
349 },
350 {
351 .start = 0x913A0,
352 .end = 0x913CF,
353 .flags = IORESOURCE_MEM,
354 },
355 {
356 .start = SIU_INT_FCC2,
357 .end = SIU_INT_FCC2,
358 .flags = IORESOURCE_IRQ,
359 },
360 },
361 },
362 [MPC85xx_CPM_FCC3] = {
363 .name = "fsl-cpm-fcc",
364 .id = 3,
365 .num_resources = 3,
366 .resource = (struct resource[]) {
367 {
368 .start = 0x91340,
369 .end = 0x9135F,
370 .flags = IORESOURCE_MEM,
371 },
372 {
373 .start = 0x913D0,
374 .end = 0x913FF,
375 .flags = IORESOURCE_MEM,
376 },
377 {
378 .start = SIU_INT_FCC3,
379 .end = SIU_INT_FCC3,
380 .flags = IORESOURCE_IRQ,
381 },
382 },
383 },
384 [MPC85xx_CPM_I2C] = {
385 .name = "fsl-cpm-i2c",
386 .id = 1,
387 .num_resources = 2,
388 .resource = (struct resource[]) {
389 {
390 .start = 0x91860,
391 .end = 0x918BF,
392 .flags = IORESOURCE_MEM,
393 },
394 {
395 .start = SIU_INT_I2C,
396 .end = SIU_INT_I2C,
397 .flags = IORESOURCE_IRQ,
398 },
399 },
400 },
401 [MPC85xx_CPM_SCC1] = {
402 .name = "fsl-cpm-scc",
403 .id = 1,
404 .num_resources = 2,
405 .resource = (struct resource[]) {
406 {
407 .start = 0x91A00,
408 .end = 0x91A1F,
409 .flags = IORESOURCE_MEM,
410 },
411 {
412 .start = SIU_INT_SCC1,
413 .end = SIU_INT_SCC1,
414 .flags = IORESOURCE_IRQ,
415 },
416 },
417 },
418 [MPC85xx_CPM_SCC2] = {
419 .name = "fsl-cpm-scc",
420 .id = 2,
421 .num_resources = 2,
422 .resource = (struct resource[]) {
423 {
424 .start = 0x91A20,
425 .end = 0x91A3F,
426 .flags = IORESOURCE_MEM,
427 },
428 {
429 .start = SIU_INT_SCC2,
430 .end = SIU_INT_SCC2,
431 .flags = IORESOURCE_IRQ,
432 },
433 },
434 },
435 [MPC85xx_CPM_SCC3] = {
436 .name = "fsl-cpm-scc",
437 .id = 3,
438 .num_resources = 2,
439 .resource = (struct resource[]) {
440 {
441 .start = 0x91A40,
442 .end = 0x91A5F,
443 .flags = IORESOURCE_MEM,
444 },
445 {
446 .start = SIU_INT_SCC3,
447 .end = SIU_INT_SCC3,
448 .flags = IORESOURCE_IRQ,
449 },
450 },
451 },
452 [MPC85xx_CPM_SCC4] = {
453 .name = "fsl-cpm-scc",
454 .id = 4,
455 .num_resources = 2,
456 .resource = (struct resource[]) {
457 {
458 .start = 0x91A60,
459 .end = 0x91A7F,
460 .flags = IORESOURCE_MEM,
461 },
462 {
463 .start = SIU_INT_SCC4,
464 .end = SIU_INT_SCC4,
465 .flags = IORESOURCE_IRQ,
466 },
467 },
468 },
469 [MPC85xx_CPM_SPI] = {
470 .name = "fsl-cpm-spi",
471 .id = 1,
472 .num_resources = 2,
473 .resource = (struct resource[]) {
474 {
475 .start = 0x91AA0,
476 .end = 0x91AFF,
477 .flags = IORESOURCE_MEM,
478 },
479 {
480 .start = SIU_INT_SPI,
481 .end = SIU_INT_SPI,
482 .flags = IORESOURCE_IRQ,
483 },
484 },
485 },
486 [MPC85xx_CPM_MCC1] = {
487 .name = "fsl-cpm-mcc",
488 .id = 1,
489 .num_resources = 2,
490 .resource = (struct resource[]) {
491 {
492 .start = 0x91B30,
493 .end = 0x91B3F,
494 .flags = IORESOURCE_MEM,
495 },
496 {
497 .start = SIU_INT_MCC1,
498 .end = SIU_INT_MCC1,
499 .flags = IORESOURCE_IRQ,
500 },
501 },
502 },
503 [MPC85xx_CPM_MCC2] = {
504 .name = "fsl-cpm-mcc",
505 .id = 2,
506 .num_resources = 2,
507 .resource = (struct resource[]) {
508 {
509 .start = 0x91B50,
510 .end = 0x91B5F,
511 .flags = IORESOURCE_MEM,
512 },
513 {
514 .start = SIU_INT_MCC2,
515 .end = SIU_INT_MCC2,
516 .flags = IORESOURCE_IRQ,
517 },
518 },
519 },
520 [MPC85xx_CPM_SMC1] = {
521 .name = "fsl-cpm-smc",
522 .id = 1,
523 .num_resources = 2,
524 .resource = (struct resource[]) {
525 {
526 .start = 0x91A80,
527 .end = 0x91A8F,
528 .flags = IORESOURCE_MEM,
529 },
530 {
531 .start = SIU_INT_SMC1,
532 .end = SIU_INT_SMC1,
533 .flags = IORESOURCE_IRQ,
534 },
535 },
536 },
537 [MPC85xx_CPM_SMC2] = {
538 .name = "fsl-cpm-smc",
539 .id = 2,
540 .num_resources = 2,
541 .resource = (struct resource[]) {
542 {
543 .start = 0x91A90,
544 .end = 0x91A9F,
545 .flags = IORESOURCE_MEM,
546 },
547 {
548 .start = SIU_INT_SMC2,
549 .end = SIU_INT_SMC2,
550 .flags = IORESOURCE_IRQ,
551 },
552 },
553 },
554 [MPC85xx_CPM_USB] = {
555 .name = "fsl-cpm-usb",
556 .id = 2,
557 .num_resources = 2,
558 .resource = (struct resource[]) {
559 {
560 .start = 0x91B60,
561 .end = 0x91B7F,
562 .flags = IORESOURCE_MEM,
563 },
564 {
565 .start = SIU_INT_USB,
566 .end = SIU_INT_USB,
567 .flags = IORESOURCE_IRQ,
568 },
569 },
570 },
571 [MPC85xx_eTSEC1] = {
572 .name = "fsl-gianfar",
573 .id = 1,
574 .dev.platform_data = &mpc85xx_etsec1_pdata,
575 .num_resources = 4,
576 .resource = (struct resource[]) {
577 {
578 .start = MPC85xx_ENET1_OFFSET,
579 .end = MPC85xx_ENET1_OFFSET +
580 MPC85xx_ENET1_SIZE - 1,
581 .flags = IORESOURCE_MEM,
582 },
583 {
584 .name = "tx",
585 .start = MPC85xx_IRQ_TSEC1_TX,
586 .end = MPC85xx_IRQ_TSEC1_TX,
587 .flags = IORESOURCE_IRQ,
588 },
589 {
590 .name = "rx",
591 .start = MPC85xx_IRQ_TSEC1_RX,
592 .end = MPC85xx_IRQ_TSEC1_RX,
593 .flags = IORESOURCE_IRQ,
594 },
595 {
596 .name = "error",
597 .start = MPC85xx_IRQ_TSEC1_ERROR,
598 .end = MPC85xx_IRQ_TSEC1_ERROR,
599 .flags = IORESOURCE_IRQ,
600 },
601 },
602 },
603 [MPC85xx_eTSEC2] = {
604 .name = "fsl-gianfar",
605 .id = 2,
606 .dev.platform_data = &mpc85xx_etsec2_pdata,
607 .num_resources = 4,
608 .resource = (struct resource[]) {
609 {
610 .start = MPC85xx_ENET2_OFFSET,
611 .end = MPC85xx_ENET2_OFFSET +
612 MPC85xx_ENET2_SIZE - 1,
613 .flags = IORESOURCE_MEM,
614 },
615 {
616 .name = "tx",
617 .start = MPC85xx_IRQ_TSEC2_TX,
618 .end = MPC85xx_IRQ_TSEC2_TX,
619 .flags = IORESOURCE_IRQ,
620 },
621 {
622 .name = "rx",
623 .start = MPC85xx_IRQ_TSEC2_RX,
624 .end = MPC85xx_IRQ_TSEC2_RX,
625 .flags = IORESOURCE_IRQ,
626 },
627 {
628 .name = "error",
629 .start = MPC85xx_IRQ_TSEC2_ERROR,
630 .end = MPC85xx_IRQ_TSEC2_ERROR,
631 .flags = IORESOURCE_IRQ,
632 },
633 },
634 },
635 [MPC85xx_eTSEC3] = {
636 .name = "fsl-gianfar",
637 .id = 3,
638 .dev.platform_data = &mpc85xx_etsec3_pdata,
639 .num_resources = 4,
640 .resource = (struct resource[]) {
641 {
642 .start = MPC85xx_ENET3_OFFSET,
643 .end = MPC85xx_ENET3_OFFSET +
644 MPC85xx_ENET3_SIZE - 1,
645 .flags = IORESOURCE_MEM,
646 },
647 {
648 .name = "tx",
649 .start = MPC85xx_IRQ_TSEC3_TX,
650 .end = MPC85xx_IRQ_TSEC3_TX,
651 .flags = IORESOURCE_IRQ,
652 },
653 {
654 .name = "rx",
655 .start = MPC85xx_IRQ_TSEC3_RX,
656 .end = MPC85xx_IRQ_TSEC3_RX,
657 .flags = IORESOURCE_IRQ,
658 },
659 {
660 .name = "error",
661 .start = MPC85xx_IRQ_TSEC3_ERROR,
662 .end = MPC85xx_IRQ_TSEC3_ERROR,
663 .flags = IORESOURCE_IRQ,
664 },
665 },
666 },
667 [MPC85xx_eTSEC4] = {
668 .name = "fsl-gianfar",
669 .id = 4,
670 .dev.platform_data = &mpc85xx_etsec4_pdata,
671 .num_resources = 4,
672 .resource = (struct resource[]) {
673 {
674 .start = 0x27000,
675 .end = 0x27fff,
676 .flags = IORESOURCE_MEM,
677 },
678 {
679 .name = "tx",
680 .start = MPC85xx_IRQ_TSEC4_TX,
681 .end = MPC85xx_IRQ_TSEC4_TX,
682 .flags = IORESOURCE_IRQ,
683 },
684 {
685 .name = "rx",
686 .start = MPC85xx_IRQ_TSEC4_RX,
687 .end = MPC85xx_IRQ_TSEC4_RX,
688 .flags = IORESOURCE_IRQ,
689 },
690 {
691 .name = "error",
692 .start = MPC85xx_IRQ_TSEC4_ERROR,
693 .end = MPC85xx_IRQ_TSEC4_ERROR,
694 .flags = IORESOURCE_IRQ,
695 },
696 },
697 },
698 [MPC85xx_IIC2] = {
699 .name = "fsl-i2c",
700 .id = 2,
701 .dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
702 .num_resources = 2,
703 .resource = (struct resource[]) {
704 {
705 .start = 0x03100,
706 .end = 0x031ff,
707 .flags = IORESOURCE_MEM,
708 },
709 {
710 .start = MPC85xx_IRQ_IIC1,
711 .end = MPC85xx_IRQ_IIC1,
712 .flags = IORESOURCE_IRQ,
713 },
714 },
715 },
716 [MPC85xx_MDIO] = {
717 .name = "fsl-gianfar_mdio",
718 .id = 0,
719 .dev.platform_data = &mpc85xx_mdio_pdata,
720 .num_resources = 1,
721 .resource = (struct resource[]) {
722 {
723 .start = 0x24520,
724 .end = 0x2453f,
725 .flags = IORESOURCE_MEM,
726 },
727 },
728 },
729 };
730
731 static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
732 {
733 ppc_sys_fixup_mem_resource(pdev, CCSRBAR);
734 return 0;
735 }
736
737 static int __init mach_mpc85xx_init(void)
738 {
739 ppc_sys_device_fixup = mach_mpc85xx_fixup;
740 return 0;
741 }
742
743 postcore_initcall(mach_mpc85xx_init);
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