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[ARM] 4779/1: S3C2412: Add s3c2412_gpio_set_sleepcfg() call
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / net / 8139too.c
blobeef6fecfff2ac731eb7259896ea8853adc384c8c
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.28"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/ioport.h>
102 #include <linux/netdevice.h>
103 #include <linux/etherdevice.h>
104 #include <linux/rtnetlink.h>
105 #include <linux/delay.h>
106 #include <linux/ethtool.h>
107 #include <linux/mii.h>
108 #include <linux/completion.h>
109 #include <linux/crc32.h>
110 #include <asm/io.h>
111 #include <asm/uaccess.h>
112 #include <asm/irq.h>
113
114 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
115 #define PFX DRV_NAME ": "
116
117 /* Default Message level */
118 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
119 NETIF_MSG_PROBE | \
120 NETIF_MSG_LINK)
121
122
123 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
124 #ifdef CONFIG_8139TOO_PIO
125 #define USE_IO_OPS 1
126 #endif
127
128 /* define to 1, 2 or 3 to enable copious debugging info */
129 #define RTL8139_DEBUG 0
130
131 /* define to 1 to disable lightweight runtime debugging checks */
132 #undef RTL8139_NDEBUG
133
134
135 #if RTL8139_DEBUG
136 /* note: prints function name for you */
137 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
138 #else
139 # define DPRINTK(fmt, args...)
140 #endif
141
142 #ifdef RTL8139_NDEBUG
143 # define assert(expr) do {} while (0)
144 #else
145 # define assert(expr) \
146 if(unlikely(!(expr))) { \
147 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
148 #expr,__FILE__,__FUNCTION__,__LINE__); \
149 }
150 #endif
151
152
153 /* A few user-configurable values. */
154 /* media options */
155 #define MAX_UNITS 8
156 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
157 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
158
159 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
160 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
161 static int multicast_filter_limit = 32;
162
163 /* bitmapped message enable number */
164 static int debug = -1;
165
166 /*
167 * Receive ring size
168 * Warning: 64K ring has hardware issues and may lock up.
169 */
170 #if defined(CONFIG_SH_DREAMCAST)
171 #define RX_BUF_IDX 1 /* 16K ring */
172 #else
173 #define RX_BUF_IDX 2 /* 32K ring */
174 #endif
175 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
176 #define RX_BUF_PAD 16
177 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
178
179 #if RX_BUF_LEN == 65536
180 #define RX_BUF_TOT_LEN RX_BUF_LEN
181 #else
182 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
183 #endif
184
185 /* Number of Tx descriptor registers. */
186 #define NUM_TX_DESC 4
187
188 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
189 #define MAX_ETH_FRAME_SIZE 1536
190
191 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
192 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
193 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
194
195 /* PCI Tuning Parameters
196 Threshold is bytes transferred to chip before transmission starts. */
197 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
198
199 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
200 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
201 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
202 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
204
205 /* Operational parameters that usually are not changed. */
206 /* Time in jiffies before concluding the transmitter is hung. */
207 #define TX_TIMEOUT (6*HZ)
208
209
210 enum {
211 HAS_MII_XCVR = 0x010000,
212 HAS_CHIP_XCVR = 0x020000,
213 HAS_LNK_CHNG = 0x040000,
214 };
215
216 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
217 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
218 #define RTL_MIN_IO_SIZE 0x80
219 #define RTL8139B_IO_SIZE 256
220
221 #define RTL8129_CAPS HAS_MII_XCVR
222 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
223
224 typedef enum {
225 RTL8139 = 0,
226 RTL8129,
227 } board_t;
228
229
230 /* indexed by board_t, above */
231 static const struct {
232 const char *name;
233 u32 hw_flags;
234 } board_info[] __devinitdata = {
235 { "RealTek RTL8139", RTL8139_CAPS },
236 { "RealTek RTL8129", RTL8129_CAPS },
237 };
238
239
240 static struct pci_device_id rtl8139_pci_tbl[] = {
241 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260
261 #ifdef CONFIG_SH_SECUREEDGE5410
262 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
263 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
264 #endif
265 #ifdef CONFIG_8139TOO_8129
266 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
267 #endif
268
269 /* some crazy cards report invalid vendor ids like
270 * 0x0001 here. The other ids are valid and constant,
271 * so we simply don't match on the main vendor id.
272 */
273 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
274 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
276
277 {0,}
278 };
279 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
280
281 static struct {
282 const char str[ETH_GSTRING_LEN];
283 } ethtool_stats_keys[] = {
284 { "early_rx" },
285 { "tx_buf_mapped" },
286 { "tx_timeouts" },
287 { "rx_lost_in_ring" },
288 };
289
290 /* The rest of these values should never change. */
291
292 /* Symbolic offsets to registers. */
293 enum RTL8139_registers {
294 MAC0 = 0, /* Ethernet hardware address. */
295 MAR0 = 8, /* Multicast filter. */
296 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
297 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
298 RxBuf = 0x30,
299 ChipCmd = 0x37,
300 RxBufPtr = 0x38,
301 RxBufAddr = 0x3A,
302 IntrMask = 0x3C,
303 IntrStatus = 0x3E,
304 TxConfig = 0x40,
305 RxConfig = 0x44,
306 Timer = 0x48, /* A general-purpose counter. */
307 RxMissed = 0x4C, /* 24 bits valid, write clears. */
308 Cfg9346 = 0x50,
309 Config0 = 0x51,
310 Config1 = 0x52,
311 FlashReg = 0x54,
312 MediaStatus = 0x58,
313 Config3 = 0x59,
314 Config4 = 0x5A, /* absent on RTL-8139A */
315 HltClk = 0x5B,
316 MultiIntr = 0x5C,
317 TxSummary = 0x60,
318 BasicModeCtrl = 0x62,
319 BasicModeStatus = 0x64,
320 NWayAdvert = 0x66,
321 NWayLPAR = 0x68,
322 NWayExpansion = 0x6A,
323 /* Undocumented registers, but required for proper operation. */
324 FIFOTMS = 0x70, /* FIFO Control and test. */
325 CSCR = 0x74, /* Chip Status and Configuration Register. */
326 PARA78 = 0x78,
327 PARA7c = 0x7c, /* Magic transceiver parameter register. */
328 Config5 = 0xD8, /* absent on RTL-8139A */
329 };
330
331 enum ClearBitMasks {
332 MultiIntrClear = 0xF000,
333 ChipCmdClear = 0xE2,
334 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
335 };
336
337 enum ChipCmdBits {
338 CmdReset = 0x10,
339 CmdRxEnb = 0x08,
340 CmdTxEnb = 0x04,
341 RxBufEmpty = 0x01,
342 };
343
344 /* Interrupt register bits, using my own meaningful names. */
345 enum IntrStatusBits {
346 PCIErr = 0x8000,
347 PCSTimeout = 0x4000,
348 RxFIFOOver = 0x40,
349 RxUnderrun = 0x20,
350 RxOverflow = 0x10,
351 TxErr = 0x08,
352 TxOK = 0x04,
353 RxErr = 0x02,
354 RxOK = 0x01,
355
356 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
357 };
358
359 enum TxStatusBits {
360 TxHostOwns = 0x2000,
361 TxUnderrun = 0x4000,
362 TxStatOK = 0x8000,
363 TxOutOfWindow = 0x20000000,
364 TxAborted = 0x40000000,
365 TxCarrierLost = 0x80000000,
366 };
367 enum RxStatusBits {
368 RxMulticast = 0x8000,
369 RxPhysical = 0x4000,
370 RxBroadcast = 0x2000,
371 RxBadSymbol = 0x0020,
372 RxRunt = 0x0010,
373 RxTooLong = 0x0008,
374 RxCRCErr = 0x0004,
375 RxBadAlign = 0x0002,
376 RxStatusOK = 0x0001,
377 };
378
379 /* Bits in RxConfig. */
380 enum rx_mode_bits {
381 AcceptErr = 0x20,
382 AcceptRunt = 0x10,
383 AcceptBroadcast = 0x08,
384 AcceptMulticast = 0x04,
385 AcceptMyPhys = 0x02,
386 AcceptAllPhys = 0x01,
387 };
388
389 /* Bits in TxConfig. */
390 enum tx_config_bits {
391 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
392 TxIFGShift = 24,
393 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
394 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
395 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
396 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
397
398 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
399 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
400 TxClearAbt = (1 << 0), /* Clear abort (WO) */
401 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
402 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
403
404 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
405 };
406
407 /* Bits in Config1 */
408 enum Config1Bits {
409 Cfg1_PM_Enable = 0x01,
410 Cfg1_VPD_Enable = 0x02,
411 Cfg1_PIO = 0x04,
412 Cfg1_MMIO = 0x08,
413 LWAKE = 0x10, /* not on 8139, 8139A */
414 Cfg1_Driver_Load = 0x20,
415 Cfg1_LED0 = 0x40,
416 Cfg1_LED1 = 0x80,
417 SLEEP = (1 << 1), /* only on 8139, 8139A */
418 PWRDN = (1 << 0), /* only on 8139, 8139A */
419 };
420
421 /* Bits in Config3 */
422 enum Config3Bits {
423 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
424 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
425 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
426 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
427 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
428 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
429 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
430 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
431 };
432
433 /* Bits in Config4 */
434 enum Config4Bits {
435 LWPTN = (1 << 2), /* not on 8139, 8139A */
436 };
437
438 /* Bits in Config5 */
439 enum Config5Bits {
440 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
441 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
442 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
443 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
444 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
445 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
446 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
447 };
448
449 enum RxConfigBits {
450 /* rx fifo threshold */
451 RxCfgFIFOShift = 13,
452 RxCfgFIFONone = (7 << RxCfgFIFOShift),
453
454 /* Max DMA burst */
455 RxCfgDMAShift = 8,
456 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
457
458 /* rx ring buffer length */
459 RxCfgRcv8K = 0,
460 RxCfgRcv16K = (1 << 11),
461 RxCfgRcv32K = (1 << 12),
462 RxCfgRcv64K = (1 << 11) | (1 << 12),
463
464 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
465 RxNoWrap = (1 << 7),
466 };
467
468 /* Twister tuning parameters from RealTek.
469 Completely undocumented, but required to tune bad links on some boards. */
470 enum CSCRBits {
471 CSCR_LinkOKBit = 0x0400,
472 CSCR_LinkChangeBit = 0x0800,
473 CSCR_LinkStatusBits = 0x0f000,
474 CSCR_LinkDownOffCmd = 0x003c0,
475 CSCR_LinkDownCmd = 0x0f3c0,
476 };
477
478 enum Cfg9346Bits {
479 Cfg9346_Lock = 0x00,
480 Cfg9346_Unlock = 0xC0,
481 };
482
483 typedef enum {
484 CH_8139 = 0,
485 CH_8139_K,
486 CH_8139A,
487 CH_8139A_G,
488 CH_8139B,
489 CH_8130,
490 CH_8139C,
491 CH_8100,
492 CH_8100B_8139D,
493 CH_8101,
494 } chip_t;
495
496 enum chip_flags {
497 HasHltClk = (1 << 0),
498 HasLWake = (1 << 1),
499 };
500
501 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
502 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
503 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
504
505 /* directly indexed by chip_t, above */
506 static const struct {
507 const char *name;
508 u32 version; /* from RTL8139C/RTL8139D docs */
509 u32 flags;
510 } rtl_chip_info[] = {
511 { "RTL-8139",
512 HW_REVID(1, 0, 0, 0, 0, 0, 0),
513 HasHltClk,
514 },
515
516 { "RTL-8139 rev K",
517 HW_REVID(1, 1, 0, 0, 0, 0, 0),
518 HasHltClk,
519 },
520
521 { "RTL-8139A",
522 HW_REVID(1, 1, 1, 0, 0, 0, 0),
523 HasHltClk, /* XXX undocumented? */
524 },
525
526 { "RTL-8139A rev G",
527 HW_REVID(1, 1, 1, 0, 0, 1, 0),
528 HasHltClk, /* XXX undocumented? */
529 },
530
531 { "RTL-8139B",
532 HW_REVID(1, 1, 1, 1, 0, 0, 0),
533 HasLWake,
534 },
535
536 { "RTL-8130",
537 HW_REVID(1, 1, 1, 1, 1, 0, 0),
538 HasLWake,
539 },
540
541 { "RTL-8139C",
542 HW_REVID(1, 1, 1, 0, 1, 0, 0),
543 HasLWake,
544 },
545
546 { "RTL-8100",
547 HW_REVID(1, 1, 1, 1, 0, 1, 0),
548 HasLWake,
549 },
550
551 { "RTL-8100B/8139D",
552 HW_REVID(1, 1, 1, 0, 1, 0, 1),
553 HasHltClk /* XXX undocumented? */
554 | HasLWake,
555 },
556
557 { "RTL-8101",
558 HW_REVID(1, 1, 1, 0, 1, 1, 1),
559 HasLWake,
560 },
561 };
562
563 struct rtl_extra_stats {
564 unsigned long early_rx;
565 unsigned long tx_buf_mapped;
566 unsigned long tx_timeouts;
567 unsigned long rx_lost_in_ring;
568 };
569
570 struct rtl8139_private {
571 void __iomem *mmio_addr;
572 int drv_flags;
573 struct pci_dev *pci_dev;
574 u32 msg_enable;
575 struct napi_struct napi;
576 struct net_device *dev;
577 struct net_device_stats stats;
578
579 unsigned char *rx_ring;
580 unsigned int cur_rx; /* RX buf index of next pkt */
581 dma_addr_t rx_ring_dma;
582
583 unsigned int tx_flag;
584 unsigned long cur_tx;
585 unsigned long dirty_tx;
586 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
587 unsigned char *tx_bufs; /* Tx bounce buffer region. */
588 dma_addr_t tx_bufs_dma;
589
590 signed char phys[4]; /* MII device addresses. */
591
592 /* Twister tune state. */
593 char twistie, twist_row, twist_col;
594
595 unsigned int watchdog_fired : 1;
596 unsigned int default_port : 4; /* Last dev->if_port value. */
597 unsigned int have_thread : 1;
598
599 spinlock_t lock;
600 spinlock_t rx_lock;
601
602 chip_t chipset;
603 u32 rx_config;
604 struct rtl_extra_stats xstats;
605
606 struct delayed_work thread;
607
608 struct mii_if_info mii;
609 unsigned int regs_len;
610 unsigned long fifo_copy_timeout;
611 };
612
613 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
614 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
615 MODULE_LICENSE("GPL");
616 MODULE_VERSION(DRV_VERSION);
617
618 module_param(multicast_filter_limit, int, 0);
619 module_param_array(media, int, NULL, 0);
620 module_param_array(full_duplex, int, NULL, 0);
621 module_param(debug, int, 0);
622 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
623 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
624 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
625 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
626
627 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
628 static int rtl8139_open (struct net_device *dev);
629 static int mdio_read (struct net_device *dev, int phy_id, int location);
630 static void mdio_write (struct net_device *dev, int phy_id, int location,
631 int val);
632 static void rtl8139_start_thread(struct rtl8139_private *tp);
633 static void rtl8139_tx_timeout (struct net_device *dev);
634 static void rtl8139_init_ring (struct net_device *dev);
635 static int rtl8139_start_xmit (struct sk_buff *skb,
636 struct net_device *dev);
637 #ifdef CONFIG_NET_POLL_CONTROLLER
638 static void rtl8139_poll_controller(struct net_device *dev);
639 #endif
640 static int rtl8139_poll(struct napi_struct *napi, int budget);
641 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
642 static int rtl8139_close (struct net_device *dev);
643 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
644 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
645 static void rtl8139_set_rx_mode (struct net_device *dev);
646 static void __set_rx_mode (struct net_device *dev);
647 static void rtl8139_hw_start (struct net_device *dev);
648 static void rtl8139_thread (struct work_struct *work);
649 static void rtl8139_tx_timeout_task(struct work_struct *work);
650 static const struct ethtool_ops rtl8139_ethtool_ops;
651
652 /* write MMIO register, with flush */
653 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
654 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
655 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
656 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
657
658 /* write MMIO register */
659 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
660 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
661 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
662
663 /* read MMIO register */
664 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
665 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
666 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
667
668
669 static const u16 rtl8139_intr_mask =
670 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
671 TxErr | TxOK | RxErr | RxOK;
672
673 static const u16 rtl8139_norx_intr_mask =
674 PCIErr | PCSTimeout | RxUnderrun |
675 TxErr | TxOK | RxErr ;
676
677 #if RX_BUF_IDX == 0
678 static const unsigned int rtl8139_rx_config =
679 RxCfgRcv8K | RxNoWrap |
680 (RX_FIFO_THRESH << RxCfgFIFOShift) |
681 (RX_DMA_BURST << RxCfgDMAShift);
682 #elif RX_BUF_IDX == 1
683 static const unsigned int rtl8139_rx_config =
684 RxCfgRcv16K | RxNoWrap |
685 (RX_FIFO_THRESH << RxCfgFIFOShift) |
686 (RX_DMA_BURST << RxCfgDMAShift);
687 #elif RX_BUF_IDX == 2
688 static const unsigned int rtl8139_rx_config =
689 RxCfgRcv32K | RxNoWrap |
690 (RX_FIFO_THRESH << RxCfgFIFOShift) |
691 (RX_DMA_BURST << RxCfgDMAShift);
692 #elif RX_BUF_IDX == 3
693 static const unsigned int rtl8139_rx_config =
694 RxCfgRcv64K |
695 (RX_FIFO_THRESH << RxCfgFIFOShift) |
696 (RX_DMA_BURST << RxCfgDMAShift);
697 #else
698 #error "Invalid configuration for 8139_RXBUF_IDX"
699 #endif
700
701 static const unsigned int rtl8139_tx_config =
702 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
703
704 static void __rtl8139_cleanup_dev (struct net_device *dev)
705 {
706 struct rtl8139_private *tp = netdev_priv(dev);
707 struct pci_dev *pdev;
708
709 assert (dev != NULL);
710 assert (tp->pci_dev != NULL);
711 pdev = tp->pci_dev;
712
713 #ifdef USE_IO_OPS
714 if (tp->mmio_addr)
715 ioport_unmap (tp->mmio_addr);
716 #else
717 if (tp->mmio_addr)
718 pci_iounmap (pdev, tp->mmio_addr);
719 #endif /* USE_IO_OPS */
720
721 /* it's ok to call this even if we have no regions to free */
722 pci_release_regions (pdev);
723
724 free_netdev(dev);
725 pci_set_drvdata (pdev, NULL);
726 }
727
728
729 static void rtl8139_chip_reset (void __iomem *ioaddr)
730 {
731 int i;
732
733 /* Soft reset the chip. */
734 RTL_W8 (ChipCmd, CmdReset);
735
736 /* Check that the chip has finished the reset. */
737 for (i = 1000; i > 0; i--) {
738 barrier();
739 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
740 break;
741 udelay (10);
742 }
743 }
744
745
746 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
747 struct net_device **dev_out)
748 {
749 void __iomem *ioaddr;
750 struct net_device *dev;
751 struct rtl8139_private *tp;
752 u8 tmp8;
753 int rc, disable_dev_on_err = 0;
754 unsigned int i;
755 unsigned long pio_start, pio_end, pio_flags, pio_len;
756 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
757 u32 version;
758
759 assert (pdev != NULL);
760
761 *dev_out = NULL;
762
763 /* dev and priv zeroed in alloc_etherdev */
764 dev = alloc_etherdev (sizeof (*tp));
765 if (dev == NULL) {
766 dev_err(&pdev->dev, "Unable to alloc new net device\n");
767 return -ENOMEM;
768 }
769 SET_NETDEV_DEV(dev, &pdev->dev);
770
771 tp = netdev_priv(dev);
772 tp->pci_dev = pdev;
773
774 /* enable device (incl. PCI PM wakeup and hotplug setup) */
775 rc = pci_enable_device (pdev);
776 if (rc)
777 goto err_out;
778
779 pio_start = pci_resource_start (pdev, 0);
780 pio_end = pci_resource_end (pdev, 0);
781 pio_flags = pci_resource_flags (pdev, 0);
782 pio_len = pci_resource_len (pdev, 0);
783
784 mmio_start = pci_resource_start (pdev, 1);
785 mmio_end = pci_resource_end (pdev, 1);
786 mmio_flags = pci_resource_flags (pdev, 1);
787 mmio_len = pci_resource_len (pdev, 1);
788
789 /* set this immediately, we need to know before
790 * we talk to the chip directly */
791 DPRINTK("PIO region size == 0x%02X\n", pio_len);
792 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
793
794 #ifdef USE_IO_OPS
795 /* make sure PCI base addr 0 is PIO */
796 if (!(pio_flags & IORESOURCE_IO)) {
797 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
798 rc = -ENODEV;
799 goto err_out;
800 }
801 /* check for weird/broken PCI region reporting */
802 if (pio_len < RTL_MIN_IO_SIZE) {
803 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
804 rc = -ENODEV;
805 goto err_out;
806 }
807 #else
808 /* make sure PCI base addr 1 is MMIO */
809 if (!(mmio_flags & IORESOURCE_MEM)) {
810 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
811 rc = -ENODEV;
812 goto err_out;
813 }
814 if (mmio_len < RTL_MIN_IO_SIZE) {
815 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
816 rc = -ENODEV;
817 goto err_out;
818 }
819 #endif
820
821 rc = pci_request_regions (pdev, DRV_NAME);
822 if (rc)
823 goto err_out;
824 disable_dev_on_err = 1;
825
826 /* enable PCI bus-mastering */
827 pci_set_master (pdev);
828
829 #ifdef USE_IO_OPS
830 ioaddr = ioport_map(pio_start, pio_len);
831 if (!ioaddr) {
832 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
833 rc = -EIO;
834 goto err_out;
835 }
836 dev->base_addr = pio_start;
837 tp->mmio_addr = ioaddr;
838 tp->regs_len = pio_len;
839 #else
840 /* ioremap MMIO region */
841 ioaddr = pci_iomap(pdev, 1, 0);
842 if (ioaddr == NULL) {
843 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
844 rc = -EIO;
845 goto err_out;
846 }
847 dev->base_addr = (long) ioaddr;
848 tp->mmio_addr = ioaddr;
849 tp->regs_len = mmio_len;
850 #endif /* USE_IO_OPS */
851
852 /* Bring old chips out of low-power mode. */
853 RTL_W8 (HltClk, 'R');
854
855 /* check for missing/broken hardware */
856 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
857 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
858 rc = -EIO;
859 goto err_out;
860 }
861
862 /* identify chip attached to board */
863 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
864 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
865 if (version == rtl_chip_info[i].version) {
866 tp->chipset = i;
867 goto match;
868 }
869
870 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
871 dev_printk (KERN_DEBUG, &pdev->dev,
872 "unknown chip version, assuming RTL-8139\n");
873 dev_printk (KERN_DEBUG, &pdev->dev,
874 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
875 tp->chipset = 0;
876
877 match:
878 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
879 version, i, rtl_chip_info[i].name);
880
881 if (tp->chipset >= CH_8139B) {
882 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
883 DPRINTK("PCI PM wakeup\n");
884 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
885 (tmp8 & LWAKE))
886 new_tmp8 &= ~LWAKE;
887 new_tmp8 |= Cfg1_PM_Enable;
888 if (new_tmp8 != tmp8) {
889 RTL_W8 (Cfg9346, Cfg9346_Unlock);
890 RTL_W8 (Config1, tmp8);
891 RTL_W8 (Cfg9346, Cfg9346_Lock);
892 }
893 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
894 tmp8 = RTL_R8 (Config4);
895 if (tmp8 & LWPTN) {
896 RTL_W8 (Cfg9346, Cfg9346_Unlock);
897 RTL_W8 (Config4, tmp8 & ~LWPTN);
898 RTL_W8 (Cfg9346, Cfg9346_Lock);
899 }
900 }
901 } else {
902 DPRINTK("Old chip wakeup\n");
903 tmp8 = RTL_R8 (Config1);
904 tmp8 &= ~(SLEEP | PWRDN);
905 RTL_W8 (Config1, tmp8);
906 }
907
908 rtl8139_chip_reset (ioaddr);
909
910 *dev_out = dev;
911 return 0;
912
913 err_out:
914 __rtl8139_cleanup_dev (dev);
915 if (disable_dev_on_err)
916 pci_disable_device (pdev);
917 return rc;
918 }
919
920
921 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
922 const struct pci_device_id *ent)
923 {
924 struct net_device *dev = NULL;
925 struct rtl8139_private *tp;
926 int i, addr_len, option;
927 void __iomem *ioaddr;
928 static int board_idx = -1;
929 DECLARE_MAC_BUF(mac);
930
931 assert (pdev != NULL);
932 assert (ent != NULL);
933
934 board_idx++;
935
936 /* when we're built into the kernel, the driver version message
937 * is only printed if at least one 8139 board has been found
938 */
939 #ifndef MODULE
940 {
941 static int printed_version;
942 if (!printed_version++)
943 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
944 }
945 #endif
946
947 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
948 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
949 dev_info(&pdev->dev,
950 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
951 pdev->vendor, pdev->device, pdev->revision);
952 dev_info(&pdev->dev,
953 "Use the \"8139cp\" driver for improved performance and stability.\n");
954 }
955
956 i = rtl8139_init_board (pdev, &dev);
957 if (i < 0)
958 return i;
959
960 assert (dev != NULL);
961 tp = netdev_priv(dev);
962 tp->dev = dev;
963
964 ioaddr = tp->mmio_addr;
965 assert (ioaddr != NULL);
966
967 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
968 for (i = 0; i < 3; i++)
969 ((u16 *) (dev->dev_addr))[i] =
970 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
971 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
972
973 /* The Rtl8139-specific entries in the device structure. */
974 dev->open = rtl8139_open;
975 dev->hard_start_xmit = rtl8139_start_xmit;
976 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
977 dev->stop = rtl8139_close;
978 dev->get_stats = rtl8139_get_stats;
979 dev->set_multicast_list = rtl8139_set_rx_mode;
980 dev->do_ioctl = netdev_ioctl;
981 dev->ethtool_ops = &rtl8139_ethtool_ops;
982 dev->tx_timeout = rtl8139_tx_timeout;
983 dev->watchdog_timeo = TX_TIMEOUT;
984 #ifdef CONFIG_NET_POLL_CONTROLLER
985 dev->poll_controller = rtl8139_poll_controller;
986 #endif
987
988 /* note: the hardware is not capable of sg/csum/highdma, however
989 * through the use of skb_copy_and_csum_dev we enable these
990 * features
991 */
992 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
993
994 dev->irq = pdev->irq;
995
996 /* tp zeroed and aligned in alloc_etherdev */
997 tp = netdev_priv(dev);
998
999 /* note: tp->chipset set in rtl8139_init_board */
1000 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1001 tp->mmio_addr = ioaddr;
1002 tp->msg_enable =
1003 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1004 spin_lock_init (&tp->lock);
1005 spin_lock_init (&tp->rx_lock);
1006 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1007 tp->mii.dev = dev;
1008 tp->mii.mdio_read = mdio_read;
1009 tp->mii.mdio_write = mdio_write;
1010 tp->mii.phy_id_mask = 0x3f;
1011 tp->mii.reg_num_mask = 0x1f;
1012
1013 /* dev is fully set up and ready to use now */
1014 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1015 i = register_netdev (dev);
1016 if (i) goto err_out;
1017
1018 pci_set_drvdata (pdev, dev);
1019
1020 printk (KERN_INFO "%s: %s at 0x%lx, "
1021 "%s, IRQ %d\n",
1022 dev->name,
1023 board_info[ent->driver_data].name,
1024 dev->base_addr,
1025 print_mac(mac, dev->dev_addr),
1026 dev->irq);
1027
1028 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1029 dev->name, rtl_chip_info[tp->chipset].name);
1030
1031 /* Find the connected MII xcvrs.
1032 Doing this in open() would allow detecting external xcvrs later, but
1033 takes too much time. */
1034 #ifdef CONFIG_8139TOO_8129
1035 if (tp->drv_flags & HAS_MII_XCVR) {
1036 int phy, phy_idx = 0;
1037 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1038 int mii_status = mdio_read(dev, phy, 1);
1039 if (mii_status != 0xffff && mii_status != 0x0000) {
1040 u16 advertising = mdio_read(dev, phy, 4);
1041 tp->phys[phy_idx++] = phy;
1042 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1043 "advertising %4.4x.\n",
1044 dev->name, phy, mii_status, advertising);
1045 }
1046 }
1047 if (phy_idx == 0) {
1048 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1049 "transceiver.\n",
1050 dev->name);
1051 tp->phys[0] = 32;
1052 }
1053 } else
1054 #endif
1055 tp->phys[0] = 32;
1056 tp->mii.phy_id = tp->phys[0];
1057
1058 /* The lower four bits are the media type. */
1059 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1060 if (option > 0) {
1061 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1062 tp->default_port = option & 0xFF;
1063 if (tp->default_port)
1064 tp->mii.force_media = 1;
1065 }
1066 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1067 tp->mii.full_duplex = full_duplex[board_idx];
1068 if (tp->mii.full_duplex) {
1069 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1070 /* Changing the MII-advertised media because might prevent
1071 re-connection. */
1072 tp->mii.force_media = 1;
1073 }
1074 if (tp->default_port) {
1075 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1076 (option & 0x20 ? 100 : 10),
1077 (option & 0x10 ? "full" : "half"));
1078 mdio_write(dev, tp->phys[0], 0,
1079 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1080 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1081 }
1082
1083 /* Put the chip into low-power mode. */
1084 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1085 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1086
1087 return 0;
1088
1089 err_out:
1090 __rtl8139_cleanup_dev (dev);
1091 pci_disable_device (pdev);
1092 return i;
1093 }
1094
1095
1096 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1097 {
1098 struct net_device *dev = pci_get_drvdata (pdev);
1099
1100 assert (dev != NULL);
1101
1102 flush_scheduled_work();
1103
1104 unregister_netdev (dev);
1105
1106 __rtl8139_cleanup_dev (dev);
1107 pci_disable_device (pdev);
1108 }
1109
1110
1111 /* Serial EEPROM section. */
1112
1113 /* EEPROM_Ctrl bits. */
1114 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1115 #define EE_CS 0x08 /* EEPROM chip select. */
1116 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1117 #define EE_WRITE_0 0x00
1118 #define EE_WRITE_1 0x02
1119 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1120 #define EE_ENB (0x80 | EE_CS)
1121
1122 /* Delay between EEPROM clock transitions.
1123 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1124 */
1125
1126 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1127
1128 /* The EEPROM commands include the alway-set leading bit. */
1129 #define EE_WRITE_CMD (5)
1130 #define EE_READ_CMD (6)
1131 #define EE_ERASE_CMD (7)
1132
1133 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1134 {
1135 int i;
1136 unsigned retval = 0;
1137 int read_cmd = location | (EE_READ_CMD << addr_len);
1138
1139 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1140 RTL_W8 (Cfg9346, EE_ENB);
1141 eeprom_delay ();
1142
1143 /* Shift the read command bits out. */
1144 for (i = 4 + addr_len; i >= 0; i--) {
1145 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1146 RTL_W8 (Cfg9346, EE_ENB | dataval);
1147 eeprom_delay ();
1148 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1149 eeprom_delay ();
1150 }
1151 RTL_W8 (Cfg9346, EE_ENB);
1152 eeprom_delay ();
1153
1154 for (i = 16; i > 0; i--) {
1155 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1156 eeprom_delay ();
1157 retval =
1158 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1159 0);
1160 RTL_W8 (Cfg9346, EE_ENB);
1161 eeprom_delay ();
1162 }
1163
1164 /* Terminate the EEPROM access. */
1165 RTL_W8 (Cfg9346, ~EE_CS);
1166 eeprom_delay ();
1167
1168 return retval;
1169 }
1170
1171 /* MII serial management: mostly bogus for now. */
1172 /* Read and write the MII management registers using software-generated
1173 serial MDIO protocol.
1174 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1175 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1176 "overclocking" issues. */
1177 #define MDIO_DIR 0x80
1178 #define MDIO_DATA_OUT 0x04
1179 #define MDIO_DATA_IN 0x02
1180 #define MDIO_CLK 0x01
1181 #define MDIO_WRITE0 (MDIO_DIR)
1182 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1183
1184 #define mdio_delay() RTL_R8(Config4)
1185
1186
1187 static const char mii_2_8139_map[8] = {
1188 BasicModeCtrl,
1189 BasicModeStatus,
1190 0,
1191 0,
1192 NWayAdvert,
1193 NWayLPAR,
1194 NWayExpansion,
1195 0
1196 };
1197
1198
1199 #ifdef CONFIG_8139TOO_8129
1200 /* Syncronize the MII management interface by shifting 32 one bits out. */
1201 static void mdio_sync (void __iomem *ioaddr)
1202 {
1203 int i;
1204
1205 for (i = 32; i >= 0; i--) {
1206 RTL_W8 (Config4, MDIO_WRITE1);
1207 mdio_delay ();
1208 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1209 mdio_delay ();
1210 }
1211 }
1212 #endif
1213
1214 static int mdio_read (struct net_device *dev, int phy_id, int location)
1215 {
1216 struct rtl8139_private *tp = netdev_priv(dev);
1217 int retval = 0;
1218 #ifdef CONFIG_8139TOO_8129
1219 void __iomem *ioaddr = tp->mmio_addr;
1220 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1221 int i;
1222 #endif
1223
1224 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1225 void __iomem *ioaddr = tp->mmio_addr;
1226 return location < 8 && mii_2_8139_map[location] ?
1227 RTL_R16 (mii_2_8139_map[location]) : 0;
1228 }
1229
1230 #ifdef CONFIG_8139TOO_8129
1231 mdio_sync (ioaddr);
1232 /* Shift the read command bits out. */
1233 for (i = 15; i >= 0; i--) {
1234 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1235
1236 RTL_W8 (Config4, MDIO_DIR | dataval);
1237 mdio_delay ();
1238 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1239 mdio_delay ();
1240 }
1241
1242 /* Read the two transition, 16 data, and wire-idle bits. */
1243 for (i = 19; i > 0; i--) {
1244 RTL_W8 (Config4, 0);
1245 mdio_delay ();
1246 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1247 RTL_W8 (Config4, MDIO_CLK);
1248 mdio_delay ();
1249 }
1250 #endif
1251
1252 return (retval >> 1) & 0xffff;
1253 }
1254
1255
1256 static void mdio_write (struct net_device *dev, int phy_id, int location,
1257 int value)
1258 {
1259 struct rtl8139_private *tp = netdev_priv(dev);
1260 #ifdef CONFIG_8139TOO_8129
1261 void __iomem *ioaddr = tp->mmio_addr;
1262 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1263 int i;
1264 #endif
1265
1266 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1267 void __iomem *ioaddr = tp->mmio_addr;
1268 if (location == 0) {
1269 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1270 RTL_W16 (BasicModeCtrl, value);
1271 RTL_W8 (Cfg9346, Cfg9346_Lock);
1272 } else if (location < 8 && mii_2_8139_map[location])
1273 RTL_W16 (mii_2_8139_map[location], value);
1274 return;
1275 }
1276
1277 #ifdef CONFIG_8139TOO_8129
1278 mdio_sync (ioaddr);
1279
1280 /* Shift the command bits out. */
1281 for (i = 31; i >= 0; i--) {
1282 int dataval =
1283 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1284 RTL_W8 (Config4, dataval);
1285 mdio_delay ();
1286 RTL_W8 (Config4, dataval | MDIO_CLK);
1287 mdio_delay ();
1288 }
1289 /* Clear out extra bits. */
1290 for (i = 2; i > 0; i--) {
1291 RTL_W8 (Config4, 0);
1292 mdio_delay ();
1293 RTL_W8 (Config4, MDIO_CLK);
1294 mdio_delay ();
1295 }
1296 #endif
1297 }
1298
1299
1300 static int rtl8139_open (struct net_device *dev)
1301 {
1302 struct rtl8139_private *tp = netdev_priv(dev);
1303 int retval;
1304 void __iomem *ioaddr = tp->mmio_addr;
1305
1306 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1307 if (retval)
1308 return retval;
1309
1310 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1311 &tp->tx_bufs_dma, GFP_KERNEL);
1312 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1313 &tp->rx_ring_dma, GFP_KERNEL);
1314 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1315 free_irq(dev->irq, dev);
1316
1317 if (tp->tx_bufs)
1318 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1319 tp->tx_bufs, tp->tx_bufs_dma);
1320 if (tp->rx_ring)
1321 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1322 tp->rx_ring, tp->rx_ring_dma);
1323
1324 return -ENOMEM;
1325
1326 }
1327
1328 napi_enable(&tp->napi);
1329
1330 tp->mii.full_duplex = tp->mii.force_media;
1331 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1332
1333 rtl8139_init_ring (dev);
1334 rtl8139_hw_start (dev);
1335 netif_start_queue (dev);
1336
1337 if (netif_msg_ifup(tp))
1338 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
1339 " GP Pins %2.2x %s-duplex.\n", dev->name,
1340 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1341 dev->irq, RTL_R8 (MediaStatus),
1342 tp->mii.full_duplex ? "full" : "half");
1343
1344 rtl8139_start_thread(tp);
1345
1346 return 0;
1347 }
1348
1349
1350 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1351 {
1352 struct rtl8139_private *tp = netdev_priv(dev);
1353
1354 if (tp->phys[0] >= 0) {
1355 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1356 }
1357 }
1358
1359 /* Start the hardware at open or resume. */
1360 static void rtl8139_hw_start (struct net_device *dev)
1361 {
1362 struct rtl8139_private *tp = netdev_priv(dev);
1363 void __iomem *ioaddr = tp->mmio_addr;
1364 u32 i;
1365 u8 tmp;
1366
1367 /* Bring old chips out of low-power mode. */
1368 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1369 RTL_W8 (HltClk, 'R');
1370
1371 rtl8139_chip_reset (ioaddr);
1372
1373 /* unlock Config[01234] and BMCR register writes */
1374 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1375 /* Restore our idea of the MAC address. */
1376 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1377 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1378
1379 /* Must enable Tx/Rx before setting transfer thresholds! */
1380 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1381
1382 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1383 RTL_W32 (RxConfig, tp->rx_config);
1384 RTL_W32 (TxConfig, rtl8139_tx_config);
1385
1386 tp->cur_rx = 0;
1387
1388 rtl_check_media (dev, 1);
1389
1390 if (tp->chipset >= CH_8139B) {
1391 /* Disable magic packet scanning, which is enabled
1392 * when PM is enabled in Config1. It can be reenabled
1393 * via ETHTOOL_SWOL if desired. */
1394 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1395 }
1396
1397 DPRINTK("init buffer addresses\n");
1398
1399 /* Lock Config[01234] and BMCR register writes */
1400 RTL_W8 (Cfg9346, Cfg9346_Lock);
1401
1402 /* init Rx ring buffer DMA address */
1403 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1404
1405 /* init Tx buffer DMA addresses */
1406 for (i = 0; i < NUM_TX_DESC; i++)
1407 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1408
1409 RTL_W32 (RxMissed, 0);
1410
1411 rtl8139_set_rx_mode (dev);
1412
1413 /* no early-rx interrupts */
1414 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1415
1416 /* make sure RxTx has started */
1417 tmp = RTL_R8 (ChipCmd);
1418 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1419 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1420
1421 /* Enable all known interrupts by setting the interrupt mask. */
1422 RTL_W16 (IntrMask, rtl8139_intr_mask);
1423 }
1424
1425
1426 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1427 static void rtl8139_init_ring (struct net_device *dev)
1428 {
1429 struct rtl8139_private *tp = netdev_priv(dev);
1430 int i;
1431
1432 tp->cur_rx = 0;
1433 tp->cur_tx = 0;
1434 tp->dirty_tx = 0;
1435
1436 for (i = 0; i < NUM_TX_DESC; i++)
1437 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1438 }
1439
1440
1441 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1442 static int next_tick = 3 * HZ;
1443
1444 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1445 static inline void rtl8139_tune_twister (struct net_device *dev,
1446 struct rtl8139_private *tp) {}
1447 #else
1448 enum TwisterParamVals {
1449 PARA78_default = 0x78fa8388,
1450 PARA7c_default = 0xcb38de43, /* param[0][3] */
1451 PARA7c_xxx = 0xcb38de43,
1452 };
1453
1454 static const unsigned long param[4][4] = {
1455 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1456 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1457 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1458 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1459 };
1460
1461 static void rtl8139_tune_twister (struct net_device *dev,
1462 struct rtl8139_private *tp)
1463 {
1464 int linkcase;
1465 void __iomem *ioaddr = tp->mmio_addr;
1466
1467 /* This is a complicated state machine to configure the "twister" for
1468 impedance/echos based on the cable length.
1469 All of this is magic and undocumented.
1470 */
1471 switch (tp->twistie) {
1472 case 1:
1473 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1474 /* We have link beat, let us tune the twister. */
1475 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1476 tp->twistie = 2; /* Change to state 2. */
1477 next_tick = HZ / 10;
1478 } else {
1479 /* Just put in some reasonable defaults for when beat returns. */
1480 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1481 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1482 RTL_W32 (PARA78, PARA78_default);
1483 RTL_W32 (PARA7c, PARA7c_default);
1484 tp->twistie = 0; /* Bail from future actions. */
1485 }
1486 break;
1487 case 2:
1488 /* Read how long it took to hear the echo. */
1489 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1490 if (linkcase == 0x7000)
1491 tp->twist_row = 3;
1492 else if (linkcase == 0x3000)
1493 tp->twist_row = 2;
1494 else if (linkcase == 0x1000)
1495 tp->twist_row = 1;
1496 else
1497 tp->twist_row = 0;
1498 tp->twist_col = 0;
1499 tp->twistie = 3; /* Change to state 2. */
1500 next_tick = HZ / 10;
1501 break;
1502 case 3:
1503 /* Put out four tuning parameters, one per 100msec. */
1504 if (tp->twist_col == 0)
1505 RTL_W16 (FIFOTMS, 0);
1506 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1507 [(int) tp->twist_col]);
1508 next_tick = HZ / 10;
1509 if (++tp->twist_col >= 4) {
1510 /* For short cables we are done.
1511 For long cables (row == 3) check for mistune. */
1512 tp->twistie =
1513 (tp->twist_row == 3) ? 4 : 0;
1514 }
1515 break;
1516 case 4:
1517 /* Special case for long cables: check for mistune. */
1518 if ((RTL_R16 (CSCR) &
1519 CSCR_LinkStatusBits) == 0x7000) {
1520 tp->twistie = 0;
1521 break;
1522 } else {
1523 RTL_W32 (PARA7c, 0xfb38de03);
1524 tp->twistie = 5;
1525 next_tick = HZ / 10;
1526 }
1527 break;
1528 case 5:
1529 /* Retune for shorter cable (column 2). */
1530 RTL_W32 (FIFOTMS, 0x20);
1531 RTL_W32 (PARA78, PARA78_default);
1532 RTL_W32 (PARA7c, PARA7c_default);
1533 RTL_W32 (FIFOTMS, 0x00);
1534 tp->twist_row = 2;
1535 tp->twist_col = 0;
1536 tp->twistie = 3;
1537 next_tick = HZ / 10;
1538 break;
1539
1540 default:
1541 /* do nothing */
1542 break;
1543 }
1544 }
1545 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1546
1547 static inline void rtl8139_thread_iter (struct net_device *dev,
1548 struct rtl8139_private *tp,
1549 void __iomem *ioaddr)
1550 {
1551 int mii_lpa;
1552
1553 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1554
1555 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1556 int duplex = (mii_lpa & LPA_100FULL)
1557 || (mii_lpa & 0x01C0) == 0x0040;
1558 if (tp->mii.full_duplex != duplex) {
1559 tp->mii.full_duplex = duplex;
1560
1561 if (mii_lpa) {
1562 printk (KERN_INFO
1563 "%s: Setting %s-duplex based on MII #%d link"
1564 " partner ability of %4.4x.\n",
1565 dev->name,
1566 tp->mii.full_duplex ? "full" : "half",
1567 tp->phys[0], mii_lpa);
1568 } else {
1569 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1570 dev->name);
1571 }
1572 #if 0
1573 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1574 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1575 RTL_W8 (Cfg9346, Cfg9346_Lock);
1576 #endif
1577 }
1578 }
1579
1580 next_tick = HZ * 60;
1581
1582 rtl8139_tune_twister (dev, tp);
1583
1584 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1585 dev->name, RTL_R16 (NWayLPAR));
1586 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1587 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1588 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1589 dev->name, RTL_R8 (Config0),
1590 RTL_R8 (Config1));
1591 }
1592
1593 static void rtl8139_thread (struct work_struct *work)
1594 {
1595 struct rtl8139_private *tp =
1596 container_of(work, struct rtl8139_private, thread.work);
1597 struct net_device *dev = tp->mii.dev;
1598 unsigned long thr_delay = next_tick;
1599
1600 rtnl_lock();
1601
1602 if (!netif_running(dev))
1603 goto out_unlock;
1604
1605 if (tp->watchdog_fired) {
1606 tp->watchdog_fired = 0;
1607 rtl8139_tx_timeout_task(work);
1608 } else
1609 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1610
1611 if (tp->have_thread)
1612 schedule_delayed_work(&tp->thread, thr_delay);
1613 out_unlock:
1614 rtnl_unlock ();
1615 }
1616
1617 static void rtl8139_start_thread(struct rtl8139_private *tp)
1618 {
1619 tp->twistie = 0;
1620 if (tp->chipset == CH_8139_K)
1621 tp->twistie = 1;
1622 else if (tp->drv_flags & HAS_LNK_CHNG)
1623 return;
1624
1625 tp->have_thread = 1;
1626 tp->watchdog_fired = 0;
1627
1628 schedule_delayed_work(&tp->thread, next_tick);
1629 }
1630
1631 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1632 {
1633 tp->cur_tx = 0;
1634 tp->dirty_tx = 0;
1635
1636 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1637 }
1638
1639 static void rtl8139_tx_timeout_task (struct work_struct *work)
1640 {
1641 struct rtl8139_private *tp =
1642 container_of(work, struct rtl8139_private, thread.work);
1643 struct net_device *dev = tp->mii.dev;
1644 void __iomem *ioaddr = tp->mmio_addr;
1645 int i;
1646 u8 tmp8;
1647
1648 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1649 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1650 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1651 /* Emit info to figure out what went wrong. */
1652 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1653 dev->name, tp->cur_tx, tp->dirty_tx);
1654 for (i = 0; i < NUM_TX_DESC; i++)
1655 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1656 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1657 i == tp->dirty_tx % NUM_TX_DESC ?
1658 " (queue head)" : "");
1659
1660 tp->xstats.tx_timeouts++;
1661
1662 /* disable Tx ASAP, if not already */
1663 tmp8 = RTL_R8 (ChipCmd);
1664 if (tmp8 & CmdTxEnb)
1665 RTL_W8 (ChipCmd, CmdRxEnb);
1666
1667 spin_lock_bh(&tp->rx_lock);
1668 /* Disable interrupts by clearing the interrupt mask. */
1669 RTL_W16 (IntrMask, 0x0000);
1670
1671 /* Stop a shared interrupt from scavenging while we are. */
1672 spin_lock_irq(&tp->lock);
1673 rtl8139_tx_clear (tp);
1674 spin_unlock_irq(&tp->lock);
1675
1676 /* ...and finally, reset everything */
1677 if (netif_running(dev)) {
1678 rtl8139_hw_start (dev);
1679 netif_wake_queue (dev);
1680 }
1681 spin_unlock_bh(&tp->rx_lock);
1682 }
1683
1684 static void rtl8139_tx_timeout (struct net_device *dev)
1685 {
1686 struct rtl8139_private *tp = netdev_priv(dev);
1687
1688 tp->watchdog_fired = 1;
1689 if (!tp->have_thread) {
1690 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1691 schedule_delayed_work(&tp->thread, next_tick);
1692 }
1693 }
1694
1695 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1696 {
1697 struct rtl8139_private *tp = netdev_priv(dev);
1698 void __iomem *ioaddr = tp->mmio_addr;
1699 unsigned int entry;
1700 unsigned int len = skb->len;
1701 unsigned long flags;
1702
1703 /* Calculate the next Tx descriptor entry. */
1704 entry = tp->cur_tx % NUM_TX_DESC;
1705
1706 /* Note: the chip doesn't have auto-pad! */
1707 if (likely(len < TX_BUF_SIZE)) {
1708 if (len < ETH_ZLEN)
1709 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1710 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1711 dev_kfree_skb(skb);
1712 } else {
1713 dev_kfree_skb(skb);
1714 tp->stats.tx_dropped++;
1715 return 0;
1716 }
1717
1718 spin_lock_irqsave(&tp->lock, flags);
1719 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1720 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1721
1722 dev->trans_start = jiffies;
1723
1724 tp->cur_tx++;
1725 wmb();
1726
1727 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1728 netif_stop_queue (dev);
1729 spin_unlock_irqrestore(&tp->lock, flags);
1730
1731 if (netif_msg_tx_queued(tp))
1732 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1733 dev->name, len, entry);
1734
1735 return 0;
1736 }
1737
1738
1739 static void rtl8139_tx_interrupt (struct net_device *dev,
1740 struct rtl8139_private *tp,
1741 void __iomem *ioaddr)
1742 {
1743 unsigned long dirty_tx, tx_left;
1744
1745 assert (dev != NULL);
1746 assert (ioaddr != NULL);
1747
1748 dirty_tx = tp->dirty_tx;
1749 tx_left = tp->cur_tx - dirty_tx;
1750 while (tx_left > 0) {
1751 int entry = dirty_tx % NUM_TX_DESC;
1752 int txstatus;
1753
1754 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1755
1756 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1757 break; /* It still hasn't been Txed */
1758
1759 /* Note: TxCarrierLost is always asserted at 100mbps. */
1760 if (txstatus & (TxOutOfWindow | TxAborted)) {
1761 /* There was an major error, log it. */
1762 if (netif_msg_tx_err(tp))
1763 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1764 dev->name, txstatus);
1765 tp->stats.tx_errors++;
1766 if (txstatus & TxAborted) {
1767 tp->stats.tx_aborted_errors++;
1768 RTL_W32 (TxConfig, TxClearAbt);
1769 RTL_W16 (IntrStatus, TxErr);
1770 wmb();
1771 }
1772 if (txstatus & TxCarrierLost)
1773 tp->stats.tx_carrier_errors++;
1774 if (txstatus & TxOutOfWindow)
1775 tp->stats.tx_window_errors++;
1776 } else {
1777 if (txstatus & TxUnderrun) {
1778 /* Add 64 to the Tx FIFO threshold. */
1779 if (tp->tx_flag < 0x00300000)
1780 tp->tx_flag += 0x00020000;
1781 tp->stats.tx_fifo_errors++;
1782 }
1783 tp->stats.collisions += (txstatus >> 24) & 15;
1784 tp->stats.tx_bytes += txstatus & 0x7ff;
1785 tp->stats.tx_packets++;
1786 }
1787
1788 dirty_tx++;
1789 tx_left--;
1790 }
1791
1792 #ifndef RTL8139_NDEBUG
1793 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1794 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1795 dev->name, dirty_tx, tp->cur_tx);
1796 dirty_tx += NUM_TX_DESC;
1797 }
1798 #endif /* RTL8139_NDEBUG */
1799
1800 /* only wake the queue if we did work, and the queue is stopped */
1801 if (tp->dirty_tx != dirty_tx) {
1802 tp->dirty_tx = dirty_tx;
1803 mb();
1804 netif_wake_queue (dev);
1805 }
1806 }
1807
1808
1809 /* TODO: clean this up! Rx reset need not be this intensive */
1810 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1811 struct rtl8139_private *tp, void __iomem *ioaddr)
1812 {
1813 u8 tmp8;
1814 #ifdef CONFIG_8139_OLD_RX_RESET
1815 int tmp_work;
1816 #endif
1817
1818 if (netif_msg_rx_err (tp))
1819 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1820 dev->name, rx_status);
1821 tp->stats.rx_errors++;
1822 if (!(rx_status & RxStatusOK)) {
1823 if (rx_status & RxTooLong) {
1824 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1825 dev->name, rx_status);
1826 /* A.C.: The chip hangs here. */
1827 }
1828 if (rx_status & (RxBadSymbol | RxBadAlign))
1829 tp->stats.rx_frame_errors++;
1830 if (rx_status & (RxRunt | RxTooLong))
1831 tp->stats.rx_length_errors++;
1832 if (rx_status & RxCRCErr)
1833 tp->stats.rx_crc_errors++;
1834 } else {
1835 tp->xstats.rx_lost_in_ring++;
1836 }
1837
1838 #ifndef CONFIG_8139_OLD_RX_RESET
1839 tmp8 = RTL_R8 (ChipCmd);
1840 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1841 RTL_W8 (ChipCmd, tmp8);
1842 RTL_W32 (RxConfig, tp->rx_config);
1843 tp->cur_rx = 0;
1844 #else
1845 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1846
1847 /* disable receive */
1848 RTL_W8_F (ChipCmd, CmdTxEnb);
1849 tmp_work = 200;
1850 while (--tmp_work > 0) {
1851 udelay(1);
1852 tmp8 = RTL_R8 (ChipCmd);
1853 if (!(tmp8 & CmdRxEnb))
1854 break;
1855 }
1856 if (tmp_work <= 0)
1857 printk (KERN_WARNING PFX "rx stop wait too long\n");
1858 /* restart receive */
1859 tmp_work = 200;
1860 while (--tmp_work > 0) {
1861 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1862 udelay(1);
1863 tmp8 = RTL_R8 (ChipCmd);
1864 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1865 break;
1866 }
1867 if (tmp_work <= 0)
1868 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1869
1870 /* and reinitialize all rx related registers */
1871 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1872 /* Must enable Tx/Rx before setting transfer thresholds! */
1873 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1874
1875 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1876 RTL_W32 (RxConfig, tp->rx_config);
1877 tp->cur_rx = 0;
1878
1879 DPRINTK("init buffer addresses\n");
1880
1881 /* Lock Config[01234] and BMCR register writes */
1882 RTL_W8 (Cfg9346, Cfg9346_Lock);
1883
1884 /* init Rx ring buffer DMA address */
1885 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1886
1887 /* A.C.: Reset the multicast list. */
1888 __set_rx_mode (dev);
1889 #endif
1890 }
1891
1892 #if RX_BUF_IDX == 3
1893 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1894 u32 offset, unsigned int size)
1895 {
1896 u32 left = RX_BUF_LEN - offset;
1897
1898 if (size > left) {
1899 skb_copy_to_linear_data(skb, ring + offset, left);
1900 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1901 } else
1902 skb_copy_to_linear_data(skb, ring + offset, size);
1903 }
1904 #endif
1905
1906 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1907 {
1908 void __iomem *ioaddr = tp->mmio_addr;
1909 u16 status;
1910
1911 status = RTL_R16 (IntrStatus) & RxAckBits;
1912
1913 /* Clear out errors and receive interrupts */
1914 if (likely(status != 0)) {
1915 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1916 tp->stats.rx_errors++;
1917 if (status & RxFIFOOver)
1918 tp->stats.rx_fifo_errors++;
1919 }
1920 RTL_W16_F (IntrStatus, RxAckBits);
1921 }
1922 }
1923
1924 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1925 int budget)
1926 {
1927 void __iomem *ioaddr = tp->mmio_addr;
1928 int received = 0;
1929 unsigned char *rx_ring = tp->rx_ring;
1930 unsigned int cur_rx = tp->cur_rx;
1931 unsigned int rx_size = 0;
1932
1933 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1934 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1935 RTL_R16 (RxBufAddr),
1936 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1937
1938 while (netif_running(dev) && received < budget
1939 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1940 u32 ring_offset = cur_rx % RX_BUF_LEN;
1941 u32 rx_status;
1942 unsigned int pkt_size;
1943 struct sk_buff *skb;
1944
1945 rmb();
1946
1947 /* read size+status of next frame from DMA ring buffer */
1948 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1949 rx_size = rx_status >> 16;
1950 pkt_size = rx_size - 4;
1951
1952 if (netif_msg_rx_status(tp))
1953 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1954 " cur %4.4x.\n", dev->name, rx_status,
1955 rx_size, cur_rx);
1956 #if RTL8139_DEBUG > 2
1957 {
1958 int i;
1959 DPRINTK ("%s: Frame contents ", dev->name);
1960 for (i = 0; i < 70; i++)
1961 printk (" %2.2x",
1962 rx_ring[ring_offset + i]);
1963 printk (".\n");
1964 }
1965 #endif
1966
1967 /* Packet copy from FIFO still in progress.
1968 * Theoretically, this should never happen
1969 * since EarlyRx is disabled.
1970 */
1971 if (unlikely(rx_size == 0xfff0)) {
1972 if (!tp->fifo_copy_timeout)
1973 tp->fifo_copy_timeout = jiffies + 2;
1974 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1975 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1976 rx_size = 0;
1977 goto no_early_rx;
1978 }
1979 if (netif_msg_intr(tp)) {
1980 printk(KERN_DEBUG "%s: fifo copy in progress.",
1981 dev->name);
1982 }
1983 tp->xstats.early_rx++;
1984 break;
1985 }
1986
1987 no_early_rx:
1988 tp->fifo_copy_timeout = 0;
1989
1990 /* If Rx err or invalid rx_size/rx_status received
1991 * (which happens if we get lost in the ring),
1992 * Rx process gets reset, so we abort any further
1993 * Rx processing.
1994 */
1995 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1996 (rx_size < 8) ||
1997 (!(rx_status & RxStatusOK)))) {
1998 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
1999 received = -1;
2000 goto out;
2001 }
2002
2003 /* Malloc up new buffer, compatible with net-2e. */
2004 /* Omit the four octet CRC from the length. */
2005
2006 skb = dev_alloc_skb (pkt_size + 2);
2007 if (likely(skb)) {
2008 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2009 #if RX_BUF_IDX == 3
2010 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2011 #else
2012 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2013 #endif
2014 skb_put (skb, pkt_size);
2015
2016 skb->protocol = eth_type_trans (skb, dev);
2017
2018 dev->last_rx = jiffies;
2019 tp->stats.rx_bytes += pkt_size;
2020 tp->stats.rx_packets++;
2021
2022 netif_receive_skb (skb);
2023 } else {
2024 if (net_ratelimit())
2025 printk (KERN_WARNING
2026 "%s: Memory squeeze, dropping packet.\n",
2027 dev->name);
2028 tp->stats.rx_dropped++;
2029 }
2030 received++;
2031
2032 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2033 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2034
2035 rtl8139_isr_ack(tp);
2036 }
2037
2038 if (unlikely(!received || rx_size == 0xfff0))
2039 rtl8139_isr_ack(tp);
2040
2041 #if RTL8139_DEBUG > 1
2042 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2043 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2044 RTL_R16 (RxBufAddr),
2045 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2046 #endif
2047
2048 tp->cur_rx = cur_rx;
2049
2050 /*
2051 * The receive buffer should be mostly empty.
2052 * Tell NAPI to reenable the Rx irq.
2053 */
2054 if (tp->fifo_copy_timeout)
2055 received = budget;
2056
2057 out:
2058 return received;
2059 }
2060
2061
2062 static void rtl8139_weird_interrupt (struct net_device *dev,
2063 struct rtl8139_private *tp,
2064 void __iomem *ioaddr,
2065 int status, int link_changed)
2066 {
2067 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2068 dev->name, status);
2069
2070 assert (dev != NULL);
2071 assert (tp != NULL);
2072 assert (ioaddr != NULL);
2073
2074 /* Update the error count. */
2075 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2076 RTL_W32 (RxMissed, 0);
2077
2078 if ((status & RxUnderrun) && link_changed &&
2079 (tp->drv_flags & HAS_LNK_CHNG)) {
2080 rtl_check_media(dev, 0);
2081 status &= ~RxUnderrun;
2082 }
2083
2084 if (status & (RxUnderrun | RxErr))
2085 tp->stats.rx_errors++;
2086
2087 if (status & PCSTimeout)
2088 tp->stats.rx_length_errors++;
2089 if (status & RxUnderrun)
2090 tp->stats.rx_fifo_errors++;
2091 if (status & PCIErr) {
2092 u16 pci_cmd_status;
2093 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2094 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2095
2096 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2097 dev->name, pci_cmd_status);
2098 }
2099 }
2100
2101 static int rtl8139_poll(struct napi_struct *napi, int budget)
2102 {
2103 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2104 struct net_device *dev = tp->dev;
2105 void __iomem *ioaddr = tp->mmio_addr;
2106 int work_done;
2107
2108 spin_lock(&tp->rx_lock);
2109 work_done = 0;
2110 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2111 work_done += rtl8139_rx(dev, tp, budget);
2112
2113 if (work_done < budget) {
2114 unsigned long flags;
2115 /*
2116 * Order is important since data can get interrupted
2117 * again when we think we are done.
2118 */
2119 spin_lock_irqsave(&tp->lock, flags);
2120 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2121 __netif_rx_complete(dev, napi);
2122 spin_unlock_irqrestore(&tp->lock, flags);
2123 }
2124 spin_unlock(&tp->rx_lock);
2125
2126 return work_done;
2127 }
2128
2129 /* The interrupt handler does all of the Rx thread work and cleans up
2130 after the Tx thread. */
2131 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2132 {
2133 struct net_device *dev = (struct net_device *) dev_instance;
2134 struct rtl8139_private *tp = netdev_priv(dev);
2135 void __iomem *ioaddr = tp->mmio_addr;
2136 u16 status, ackstat;
2137 int link_changed = 0; /* avoid bogus "uninit" warning */
2138 int handled = 0;
2139
2140 spin_lock (&tp->lock);
2141 status = RTL_R16 (IntrStatus);
2142
2143 /* shared irq? */
2144 if (unlikely((status & rtl8139_intr_mask) == 0))
2145 goto out;
2146
2147 handled = 1;
2148
2149 /* h/w no longer present (hotplug?) or major error, bail */
2150 if (unlikely(status == 0xFFFF))
2151 goto out;
2152
2153 /* close possible race's with dev_close */
2154 if (unlikely(!netif_running(dev))) {
2155 RTL_W16 (IntrMask, 0);
2156 goto out;
2157 }
2158
2159 /* Acknowledge all of the current interrupt sources ASAP, but
2160 an first get an additional status bit from CSCR. */
2161 if (unlikely(status & RxUnderrun))
2162 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2163
2164 ackstat = status & ~(RxAckBits | TxErr);
2165 if (ackstat)
2166 RTL_W16 (IntrStatus, ackstat);
2167
2168 /* Receive packets are processed by poll routine.
2169 If not running start it now. */
2170 if (status & RxAckBits){
2171 if (netif_rx_schedule_prep(dev, &tp->napi)) {
2172 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2173 __netif_rx_schedule(dev, &tp->napi);
2174 }
2175 }
2176
2177 /* Check uncommon events with one test. */
2178 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2179 rtl8139_weird_interrupt (dev, tp, ioaddr,
2180 status, link_changed);
2181
2182 if (status & (TxOK | TxErr)) {
2183 rtl8139_tx_interrupt (dev, tp, ioaddr);
2184 if (status & TxErr)
2185 RTL_W16 (IntrStatus, TxErr);
2186 }
2187 out:
2188 spin_unlock (&tp->lock);
2189
2190 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2191 dev->name, RTL_R16 (IntrStatus));
2192 return IRQ_RETVAL(handled);
2193 }
2194
2195 #ifdef CONFIG_NET_POLL_CONTROLLER
2196 /*
2197 * Polling receive - used by netconsole and other diagnostic tools
2198 * to allow network i/o with interrupts disabled.
2199 */
2200 static void rtl8139_poll_controller(struct net_device *dev)
2201 {
2202 disable_irq(dev->irq);
2203 rtl8139_interrupt(dev->irq, dev);
2204 enable_irq(dev->irq);
2205 }
2206 #endif
2207
2208 static int rtl8139_close (struct net_device *dev)
2209 {
2210 struct rtl8139_private *tp = netdev_priv(dev);
2211 void __iomem *ioaddr = tp->mmio_addr;
2212 unsigned long flags;
2213
2214 netif_stop_queue(dev);
2215 napi_disable(&tp->napi);
2216
2217 if (netif_msg_ifdown(tp))
2218 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2219 dev->name, RTL_R16 (IntrStatus));
2220
2221 spin_lock_irqsave (&tp->lock, flags);
2222
2223 /* Stop the chip's Tx and Rx DMA processes. */
2224 RTL_W8 (ChipCmd, 0);
2225
2226 /* Disable interrupts by clearing the interrupt mask. */
2227 RTL_W16 (IntrMask, 0);
2228
2229 /* Update the error counts. */
2230 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2231 RTL_W32 (RxMissed, 0);
2232
2233 spin_unlock_irqrestore (&tp->lock, flags);
2234
2235 synchronize_irq (dev->irq); /* racy, but that's ok here */
2236 free_irq (dev->irq, dev);
2237
2238 rtl8139_tx_clear (tp);
2239
2240 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2241 tp->rx_ring, tp->rx_ring_dma);
2242 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2243 tp->tx_bufs, tp->tx_bufs_dma);
2244 tp->rx_ring = NULL;
2245 tp->tx_bufs = NULL;
2246
2247 /* Green! Put the chip in low-power mode. */
2248 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2249
2250 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2251 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2252
2253 return 0;
2254 }
2255
2256
2257 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2258 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2259 other threads or interrupts aren't messing with the 8139. */
2260 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2261 {
2262 struct rtl8139_private *np = netdev_priv(dev);
2263 void __iomem *ioaddr = np->mmio_addr;
2264
2265 spin_lock_irq(&np->lock);
2266 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2267 u8 cfg3 = RTL_R8 (Config3);
2268 u8 cfg5 = RTL_R8 (Config5);
2269
2270 wol->supported = WAKE_PHY | WAKE_MAGIC
2271 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2272
2273 wol->wolopts = 0;
2274 if (cfg3 & Cfg3_LinkUp)
2275 wol->wolopts |= WAKE_PHY;
2276 if (cfg3 & Cfg3_Magic)
2277 wol->wolopts |= WAKE_MAGIC;
2278 /* (KON)FIXME: See how netdev_set_wol() handles the
2279 following constants. */
2280 if (cfg5 & Cfg5_UWF)
2281 wol->wolopts |= WAKE_UCAST;
2282 if (cfg5 & Cfg5_MWF)
2283 wol->wolopts |= WAKE_MCAST;
2284 if (cfg5 & Cfg5_BWF)
2285 wol->wolopts |= WAKE_BCAST;
2286 }
2287 spin_unlock_irq(&np->lock);
2288 }
2289
2290
2291 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2292 that wol points to kernel memory and other threads or interrupts
2293 aren't messing with the 8139. */
2294 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2295 {
2296 struct rtl8139_private *np = netdev_priv(dev);
2297 void __iomem *ioaddr = np->mmio_addr;
2298 u32 support;
2299 u8 cfg3, cfg5;
2300
2301 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2302 ? (WAKE_PHY | WAKE_MAGIC
2303 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2304 : 0);
2305 if (wol->wolopts & ~support)
2306 return -EINVAL;
2307
2308 spin_lock_irq(&np->lock);
2309 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2310 if (wol->wolopts & WAKE_PHY)
2311 cfg3 |= Cfg3_LinkUp;
2312 if (wol->wolopts & WAKE_MAGIC)
2313 cfg3 |= Cfg3_Magic;
2314 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2315 RTL_W8 (Config3, cfg3);
2316 RTL_W8 (Cfg9346, Cfg9346_Lock);
2317
2318 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2319 /* (KON)FIXME: These are untested. We may have to set the
2320 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2321 documentation. */
2322 if (wol->wolopts & WAKE_UCAST)
2323 cfg5 |= Cfg5_UWF;
2324 if (wol->wolopts & WAKE_MCAST)
2325 cfg5 |= Cfg5_MWF;
2326 if (wol->wolopts & WAKE_BCAST)
2327 cfg5 |= Cfg5_BWF;
2328 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2329 spin_unlock_irq(&np->lock);
2330
2331 return 0;
2332 }
2333
2334 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2335 {
2336 struct rtl8139_private *np = netdev_priv(dev);
2337 strcpy(info->driver, DRV_NAME);
2338 strcpy(info->version, DRV_VERSION);
2339 strcpy(info->bus_info, pci_name(np->pci_dev));
2340 info->regdump_len = np->regs_len;
2341 }
2342
2343 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2344 {
2345 struct rtl8139_private *np = netdev_priv(dev);
2346 spin_lock_irq(&np->lock);
2347 mii_ethtool_gset(&np->mii, cmd);
2348 spin_unlock_irq(&np->lock);
2349 return 0;
2350 }
2351
2352 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2353 {
2354 struct rtl8139_private *np = netdev_priv(dev);
2355 int rc;
2356 spin_lock_irq(&np->lock);
2357 rc = mii_ethtool_sset(&np->mii, cmd);
2358 spin_unlock_irq(&np->lock);
2359 return rc;
2360 }
2361
2362 static int rtl8139_nway_reset(struct net_device *dev)
2363 {
2364 struct rtl8139_private *np = netdev_priv(dev);
2365 return mii_nway_restart(&np->mii);
2366 }
2367
2368 static u32 rtl8139_get_link(struct net_device *dev)
2369 {
2370 struct rtl8139_private *np = netdev_priv(dev);
2371 return mii_link_ok(&np->mii);
2372 }
2373
2374 static u32 rtl8139_get_msglevel(struct net_device *dev)
2375 {
2376 struct rtl8139_private *np = netdev_priv(dev);
2377 return np->msg_enable;
2378 }
2379
2380 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2381 {
2382 struct rtl8139_private *np = netdev_priv(dev);
2383 np->msg_enable = datum;
2384 }
2385
2386 /* TODO: we are too slack to do reg dumping for pio, for now */
2387 #ifdef CONFIG_8139TOO_PIO
2388 #define rtl8139_get_regs_len NULL
2389 #define rtl8139_get_regs NULL
2390 #else
2391 static int rtl8139_get_regs_len(struct net_device *dev)
2392 {
2393 struct rtl8139_private *np = netdev_priv(dev);
2394 return np->regs_len;
2395 }
2396
2397 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2398 {
2399 struct rtl8139_private *np = netdev_priv(dev);
2400
2401 regs->version = RTL_REGS_VER;
2402
2403 spin_lock_irq(&np->lock);
2404 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2405 spin_unlock_irq(&np->lock);
2406 }
2407 #endif /* CONFIG_8139TOO_MMIO */
2408
2409 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2410 {
2411 switch (sset) {
2412 case ETH_SS_STATS:
2413 return RTL_NUM_STATS;
2414 default:
2415 return -EOPNOTSUPP;
2416 }
2417 }
2418
2419 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2420 {
2421 struct rtl8139_private *np = netdev_priv(dev);
2422
2423 data[0] = np->xstats.early_rx;
2424 data[1] = np->xstats.tx_buf_mapped;
2425 data[2] = np->xstats.tx_timeouts;
2426 data[3] = np->xstats.rx_lost_in_ring;
2427 }
2428
2429 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2430 {
2431 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2432 }
2433
2434 static const struct ethtool_ops rtl8139_ethtool_ops = {
2435 .get_drvinfo = rtl8139_get_drvinfo,
2436 .get_settings = rtl8139_get_settings,
2437 .set_settings = rtl8139_set_settings,
2438 .get_regs_len = rtl8139_get_regs_len,
2439 .get_regs = rtl8139_get_regs,
2440 .nway_reset = rtl8139_nway_reset,
2441 .get_link = rtl8139_get_link,
2442 .get_msglevel = rtl8139_get_msglevel,
2443 .set_msglevel = rtl8139_set_msglevel,
2444 .get_wol = rtl8139_get_wol,
2445 .set_wol = rtl8139_set_wol,
2446 .get_strings = rtl8139_get_strings,
2447 .get_sset_count = rtl8139_get_sset_count,
2448 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2449 };
2450
2451 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2452 {
2453 struct rtl8139_private *np = netdev_priv(dev);
2454 int rc;
2455
2456 if (!netif_running(dev))
2457 return -EINVAL;
2458
2459 spin_lock_irq(&np->lock);
2460 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2461 spin_unlock_irq(&np->lock);
2462
2463 return rc;
2464 }
2465
2466
2467 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2468 {
2469 struct rtl8139_private *tp = netdev_priv(dev);
2470 void __iomem *ioaddr = tp->mmio_addr;
2471 unsigned long flags;
2472
2473 if (netif_running(dev)) {
2474 spin_lock_irqsave (&tp->lock, flags);
2475 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2476 RTL_W32 (RxMissed, 0);
2477 spin_unlock_irqrestore (&tp->lock, flags);
2478 }
2479
2480 return &tp->stats;
2481 }
2482
2483 /* Set or clear the multicast filter for this adaptor.
2484 This routine is not state sensitive and need not be SMP locked. */
2485
2486 static void __set_rx_mode (struct net_device *dev)
2487 {
2488 struct rtl8139_private *tp = netdev_priv(dev);
2489 void __iomem *ioaddr = tp->mmio_addr;
2490 u32 mc_filter[2]; /* Multicast hash filter */
2491 int i, rx_mode;
2492 u32 tmp;
2493
2494 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2495 dev->name, dev->flags, RTL_R32 (RxConfig));
2496
2497 /* Note: do not reorder, GCC is clever about common statements. */
2498 if (dev->flags & IFF_PROMISC) {
2499 rx_mode =
2500 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2501 AcceptAllPhys;
2502 mc_filter[1] = mc_filter[0] = 0xffffffff;
2503 } else if ((dev->mc_count > multicast_filter_limit)
2504 || (dev->flags & IFF_ALLMULTI)) {
2505 /* Too many to filter perfectly -- accept all multicasts. */
2506 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2507 mc_filter[1] = mc_filter[0] = 0xffffffff;
2508 } else {
2509 struct dev_mc_list *mclist;
2510 rx_mode = AcceptBroadcast | AcceptMyPhys;
2511 mc_filter[1] = mc_filter[0] = 0;
2512 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2513 i++, mclist = mclist->next) {
2514 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2515
2516 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2517 rx_mode |= AcceptMulticast;
2518 }
2519 }
2520
2521 /* We can safely update without stopping the chip. */
2522 tmp = rtl8139_rx_config | rx_mode;
2523 if (tp->rx_config != tmp) {
2524 RTL_W32_F (RxConfig, tmp);
2525 tp->rx_config = tmp;
2526 }
2527 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2528 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2529 }
2530
2531 static void rtl8139_set_rx_mode (struct net_device *dev)
2532 {
2533 unsigned long flags;
2534 struct rtl8139_private *tp = netdev_priv(dev);
2535
2536 spin_lock_irqsave (&tp->lock, flags);
2537 __set_rx_mode(dev);
2538 spin_unlock_irqrestore (&tp->lock, flags);
2539 }
2540
2541 #ifdef CONFIG_PM
2542
2543 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2544 {
2545 struct net_device *dev = pci_get_drvdata (pdev);
2546 struct rtl8139_private *tp = netdev_priv(dev);
2547 void __iomem *ioaddr = tp->mmio_addr;
2548 unsigned long flags;
2549
2550 pci_save_state (pdev);
2551
2552 if (!netif_running (dev))
2553 return 0;
2554
2555 netif_device_detach (dev);
2556
2557 spin_lock_irqsave (&tp->lock, flags);
2558
2559 /* Disable interrupts, stop Tx and Rx. */
2560 RTL_W16 (IntrMask, 0);
2561 RTL_W8 (ChipCmd, 0);
2562
2563 /* Update the error counts. */
2564 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2565 RTL_W32 (RxMissed, 0);
2566
2567 spin_unlock_irqrestore (&tp->lock, flags);
2568
2569 pci_set_power_state (pdev, PCI_D3hot);
2570
2571 return 0;
2572 }
2573
2574
2575 static int rtl8139_resume (struct pci_dev *pdev)
2576 {
2577 struct net_device *dev = pci_get_drvdata (pdev);
2578
2579 pci_restore_state (pdev);
2580 if (!netif_running (dev))
2581 return 0;
2582 pci_set_power_state (pdev, PCI_D0);
2583 rtl8139_init_ring (dev);
2584 rtl8139_hw_start (dev);
2585 netif_device_attach (dev);
2586 return 0;
2587 }
2588
2589 #endif /* CONFIG_PM */
2590
2591
2592 static struct pci_driver rtl8139_pci_driver = {
2593 .name = DRV_NAME,
2594 .id_table = rtl8139_pci_tbl,
2595 .probe = rtl8139_init_one,
2596 .remove = __devexit_p(rtl8139_remove_one),
2597 #ifdef CONFIG_PM
2598 .suspend = rtl8139_suspend,
2599 .resume = rtl8139_resume,
2600 #endif /* CONFIG_PM */
2601 };
2602
2603
2604 static int __init rtl8139_init_module (void)
2605 {
2606 /* when we're a module, we always print a version message,
2607 * even if no 8139 board is found.
2608 */
2609 #ifdef MODULE
2610 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2611 #endif
2612
2613 return pci_register_driver(&rtl8139_pci_driver);
2614 }
2615
2616
2617 static void __exit rtl8139_cleanup_module (void)
2618 {
2619 pci_unregister_driver (&rtl8139_pci_driver);
2620 }
2621
2622
2623 module_init(rtl8139_init_module);
2624 module_exit(rtl8139_cleanup_module);
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