arch/ppc/platforms/katana.c

   1 /*
   2  * arch/ppc/platforms/katana.c
   3  *
   4  * Board setup routines for the Artesyn Katana cPCI boards.
   5  *
   6  * Author: Tim Montgomery <timm@artesyncp.com>
   7  * Maintained by: Mark A. Greer <mgreer@mvista.com>
   8  *
   9  * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
  10  * Based on code done by - Mark A. Greer <mgreer@mvista.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms of the GNU General Public License as published by the
  14  * Free Software Foundation; either version 2 of the License, or (at your
  15  * option) any later version.
  16  */
  17 /*
  18  * Supports the Artesyn 750i, 752i, and 3750.  The 752i is virtually identical
  19  * to the 750i except that it has an mv64460 bridge.
  20  */
  21 #include <linux/config.h>
  22 #include <linux/kernel.h>
  23 #include <linux/pci.h>
  24 #include <linux/kdev_t.h>
  25 #include <linux/console.h>
  26 #include <linux/initrd.h>
  27 #include <linux/root_dev.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/mtd/physmap.h>
  31 #include <linux/mv643xx.h>
  32 #include <linux/platform_device.h>
  33 #ifdef CONFIG_BOOTIMG
  34 #include <linux/bootimg.h>
  35 #endif
  36 #include <asm/io.h>
  37 #include <asm/unistd.h>
  38 #include <asm/page.h>
  39 #include <asm/time.h>
  40 #include <asm/smp.h>
  41 #include <asm/todc.h>
  42 #include <asm/bootinfo.h>
  43 #include <asm/ppcboot.h>
  44 #include <asm/mv64x60.h>
  45 #include <platforms/katana.h>
  46 #include <asm/machdep.h>
  47
  48 static struct mv64x60_handle    bh;
  49 static katana_id_t              katana_id;
  50 static void __iomem             *cpld_base;
  51 static void __iomem             *sram_base;
  52 static u32                      katana_flash_size_0;
  53 static u32                      katana_flash_size_1;
  54 static u32                      katana_bus_frequency;
  55 static struct pci_controller    katana_hose_a;
  56
  57 unsigned char   __res[sizeof(bd_t)];
  58
  59 /* PCI Interrupt routing */
  60 static int __init
  61 katana_irq_lookup_750i(unsigned char idsel, unsigned char pin)
  62 {
  63         static char pci_irq_table[][4] = {
  64                 /*
  65                  * PCI IDSEL/INTPIN->INTLINE
  66                  *       A   B   C   D
  67                  */
  68                 /* IDSEL 4  (PMC 1) */
  69                 { KATANA_PCI_INTB_IRQ_750i, KATANA_PCI_INTC_IRQ_750i,
  70                         KATANA_PCI_INTD_IRQ_750i, KATANA_PCI_INTA_IRQ_750i },
  71                 /* IDSEL 5  (PMC 2) */
  72                 { KATANA_PCI_INTC_IRQ_750i, KATANA_PCI_INTD_IRQ_750i,
  73                         KATANA_PCI_INTA_IRQ_750i, KATANA_PCI_INTB_IRQ_750i },
  74                 /* IDSEL 6 (T8110) */
  75                 {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
  76                 /* IDSEL 7 (unused) */
  77                 {0, 0, 0, 0 },
  78                 /* IDSEL 8 (Intel 82544) (752i only but doesn't harm 750i) */
  79                 {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
  80         };
  81         const long min_idsel = 4, max_idsel = 8, irqs_per_slot = 4;
  82
  83         return PCI_IRQ_TABLE_LOOKUP;
  84 }
  85
  86 static int __init
  87 katana_irq_lookup_3750(unsigned char idsel, unsigned char pin)
  88 {
  89         static char pci_irq_table[][4] = {
  90                 /*
  91                  * PCI IDSEL/INTPIN->INTLINE
  92                  *       A   B   C   D
  93                  */
  94                 { KATANA_PCI_INTA_IRQ_3750, 0, 0, 0 }, /* IDSEL 3 (BCM5691) */
  95                 { KATANA_PCI_INTB_IRQ_3750, 0, 0, 0 }, /* IDSEL 4 (MV64360 #2)*/
  96                 { KATANA_PCI_INTC_IRQ_3750, 0, 0, 0 }, /* IDSEL 5 (MV64360 #3)*/
  97         };
  98         const long min_idsel = 3, max_idsel = 5, irqs_per_slot = 4;
  99
 100         return PCI_IRQ_TABLE_LOOKUP;
 101 }
 102
 103 static int __init
 104 katana_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 105 {
 106         switch (katana_id) {
 107         case KATANA_ID_750I:
 108         case KATANA_ID_752I:
 109                 return katana_irq_lookup_750i(idsel, pin);
 110
 111         case KATANA_ID_3750:
 112                 return katana_irq_lookup_3750(idsel, pin);
 113
 114         default:
 115                 printk(KERN_ERR "Bogus board ID\n");
 116                 return 0;
 117         }
 118 }
 119
 120 /* Board info retrieval routines */
 121 void __init
 122 katana_get_board_id(void)
 123 {
 124         switch (in_8(cpld_base + KATANA_CPLD_PRODUCT_ID)) {
 125         case KATANA_PRODUCT_ID_3750:
 126                 katana_id = KATANA_ID_3750;
 127                 break;
 128
 129         case KATANA_PRODUCT_ID_750i:
 130                 katana_id = KATANA_ID_750I;
 131                 break;
 132
 133         case KATANA_PRODUCT_ID_752i:
 134                 katana_id = KATANA_ID_752I;
 135                 break;
 136
 137         default:
 138                 printk(KERN_ERR "Unsupported board\n");
 139         }
 140 }
 141
 142 int __init
 143 katana_get_proc_num(void)
 144 {
 145         u16             val;
 146         u8              save_exclude;
 147         static int      proc = -1;
 148         static u8       first_time = 1;
 149
 150         if (first_time) {
 151                 if (katana_id != KATANA_ID_3750)
 152                         proc = 0;
 153                 else {
 154                         save_exclude = mv64x60_pci_exclude_bridge;
 155                         mv64x60_pci_exclude_bridge = 0;
 156
 157                         early_read_config_word(bh.hose_b, 0,
 158                                 PCI_DEVFN(0,0), PCI_DEVICE_ID, &val);
 159
 160                         mv64x60_pci_exclude_bridge = save_exclude;
 161
 162                         switch(val) {
 163                         case PCI_DEVICE_ID_KATANA_3750_PROC0:
 164                                 proc = 0;
 165                                 break;
 166
 167                         case PCI_DEVICE_ID_KATANA_3750_PROC1:
 168                                 proc = 1;
 169                                 break;
 170
 171                         case PCI_DEVICE_ID_KATANA_3750_PROC2:
 172                                 proc = 2;
 173                                 break;
 174
 175                         default:
 176                                 printk(KERN_ERR "Bogus Device ID\n");
 177                         }
 178                 }
 179
 180                 first_time = 0;
 181         }
 182
 183         return proc;
 184 }
 185
 186 static inline int
 187 katana_is_monarch(void)
 188 {
 189         return in_8(cpld_base + KATANA_CPLD_BD_CFG_3) &
 190                 KATANA_CPLD_BD_CFG_3_MONARCH;
 191 }
 192
 193 static void __init
 194 katana_setup_bridge(void)
 195 {
 196         struct pci_controller hose;
 197         struct mv64x60_setup_info si;
 198         void __iomem *vaddr;
 199         int i;
 200         u32 v;
 201         u16 val, type;
 202         u8 save_exclude;
 203
 204         /*
 205          * Some versions of the Katana firmware mistakenly change the vendor
 206          * & device id fields in the bridge's pci device (visible via pci
 207          * config accesses).  This breaks mv64x60_init() because those values
 208          * are used to identify the type of bridge that's there.  Artesyn
 209          * claims that the subsystem vendor/device id's will have the correct
 210          * Marvell values so this code puts back the correct values from there.
 211          */
 212         memset(&hose, 0, sizeof(hose));
 213         vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE);
 214         setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR,
 215                 vaddr + MV64x60_PCI0_CONFIG_DATA);
 216         save_exclude = mv64x60_pci_exclude_bridge;
 217         mv64x60_pci_exclude_bridge = 0;
 218
 219         early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
 220
 221         if (val != PCI_VENDOR_ID_MARVELL) {
 222                 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
 223                         PCI_SUBSYSTEM_VENDOR_ID, &val);
 224                 early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
 225                         PCI_VENDOR_ID, val);
 226                 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
 227                         PCI_SUBSYSTEM_ID, &val);
 228                 early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
 229                         PCI_DEVICE_ID, val);
 230         }
 231
 232         /*
 233          * While we're in here, set the hotswap register correctly.
 234          * Turn off blue LED; mask ENUM#, clear insertion & extraction bits.
 235          */
 236         early_read_config_dword(&hose, 0, PCI_DEVFN(0, 0),
 237                 MV64360_PCICFG_CPCI_HOTSWAP, &v);
 238         v &= ~(1<<19);
 239         v |= ((1<<17) | (1<<22) | (1<<23));
 240         early_write_config_dword(&hose, 0, PCI_DEVFN(0, 0),
 241                 MV64360_PCICFG_CPCI_HOTSWAP, v);
 242
 243         /* While we're at it, grab the bridge type for later */
 244         early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &type);
 245
 246         mv64x60_pci_exclude_bridge = save_exclude;
 247         iounmap(vaddr);
 248
 249         memset(&si, 0, sizeof(si));
 250
 251         si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
 252
 253         si.pci_1.enable_bus = 1;
 254         si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
 255         si.pci_1.pci_io.pci_base_hi = 0;
 256         si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
 257         si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
 258         si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
 259         si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
 260         si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
 261         si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
 262         si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
 263         si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
 264         si.pci_1.pci_cmd_bits = 0;
 265         si.pci_1.latency_timer = 0x80;
 266
 267         for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
 268 #if defined(CONFIG_NOT_COHERENT_CACHE)
 269                 si.cpu_prot_options[i] = 0;
 270                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
 271                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
 272                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
 273
 274                 si.pci_1.acc_cntl_options[i] =
 275                         MV64360_PCI_ACC_CNTL_SNOOP_NONE |
 276                         MV64360_PCI_ACC_CNTL_SWAP_NONE |
 277                         MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
 278                         MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 279 #else
 280                 si.cpu_prot_options[i] = 0;
 281                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;
 282                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;
 283                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;
 284
 285                 si.pci_1.acc_cntl_options[i] =
 286                         MV64360_PCI_ACC_CNTL_SNOOP_WB |
 287                         MV64360_PCI_ACC_CNTL_SWAP_NONE |
 288                         MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
 289                         ((type == PCI_DEVICE_ID_MARVELL_MV64360) ?
 290                                 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES :
 291                                 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES);
 292 #endif
 293         }
 294
 295         /* Lookup PCI host bridges */
 296         if (mv64x60_init(&bh, &si))
 297                 printk(KERN_WARNING "Bridge initialization failed.\n");
 298
 299         pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
 300         ppc_md.pci_swizzle = common_swizzle;
 301         ppc_md.pci_map_irq = katana_map_irq;
 302         ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
 303
 304         mv64x60_set_bus(&bh, 1, 0);
 305         bh.hose_b->first_busno = 0;
 306         bh.hose_b->last_busno = 0xff;
 307
 308         /*
 309          * Need to access hotswap reg which is in the pci config area of the
 310          * bridge's hose 0.  Note that pcibios_alloc_controller() can't be used
 311          * to alloc hose_a b/c that would make hose 0 known to the generic
 312          * pci code which we don't want.
 313          */
 314         bh.hose_a = &katana_hose_a;
 315         setup_indirect_pci_nomap(bh.hose_a,
 316                 bh.v_base + MV64x60_PCI0_CONFIG_ADDR,
 317                 bh.v_base + MV64x60_PCI0_CONFIG_DATA);
 318 }
 319
 320 /* Bridge & platform setup routines */
 321 void __init
 322 katana_intr_setup(void)
 323 {
 324         if (bh.type == MV64x60_TYPE_MV64460) /* As per instns from Marvell */
 325                 mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, 1 << 15);
 326
 327         /* MPP 8, 9, and 10 */
 328         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
 329
 330         /* MPP 14 */
 331         if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I))
 332                 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0x0f000000);
 333
 334         /*
 335          * Define GPP 8,9,and 10 interrupt polarity as active low
 336          * input signal and level triggered
 337          */
 338         mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
 339         mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
 340
 341         if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
 342                 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, (1<<14));
 343                 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, (1<<14));
 344         }
 345
 346         /* Config GPP intr ctlr to respond to level trigger */
 347         mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
 348
 349         if (bh.type == MV64x60_TYPE_MV64360) {
 350                 /* Erratum FEr PCI-#9 */
 351                 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD,
 352                                 (1<<4) | (1<<5) | (1<<6) | (1<<7));
 353                 mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, (1<<8) | (1<<9));
 354         } else {
 355                 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<6) | (1<<7));
 356                 mv64x60_set_bits(&bh, MV64x60_PCI1_CMD,
 357                                 (1<<4) | (1<<5) | (1<<8) | (1<<9));
 358         }
 359
 360         /*
 361          * Dismiss and then enable interrupt on GPP interrupt cause
 362          * for CPU #0
 363          */
 364         mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
 365         mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
 366
 367         if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
 368                 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1<<14));
 369                 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1<<14));
 370         }
 371
 372         /*
 373          * Dismiss and then enable interrupt on CPU #0 high cause reg
 374          * BIT25 summarizes GPP interrupts 8-15
 375          */
 376         mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
 377 }
 378
 379 void __init
 380 katana_setup_peripherals(void)
 381 {
 382         u32 base;
 383
 384         /* Set up windows for boot CS, soldered & socketed flash, and CPLD */
 385         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 386                  KATANA_BOOT_WINDOW_BASE, KATANA_BOOT_WINDOW_SIZE, 0);
 387         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 388
 389         /* Assume firmware set up window sizes correctly for dev 0 & 1 */
 390         mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, &base,
 391                 &katana_flash_size_0);
 392
 393         if (katana_flash_size_0 > 0) {
 394                 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
 395                          KATANA_SOLDERED_FLASH_BASE, katana_flash_size_0, 0);
 396                 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
 397         }
 398
 399         mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, &base,
 400                 &katana_flash_size_1);
 401
 402         if (katana_flash_size_1 > 0) {
 403                 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
 404                          (KATANA_SOLDERED_FLASH_BASE + katana_flash_size_0),
 405                          katana_flash_size_1, 0);
 406                 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
 407         }
 408
 409         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
 410                  KATANA_SOCKET_BASE, KATANA_SOCKETED_FLASH_SIZE, 0);
 411         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
 412
 413         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
 414                  KATANA_CPLD_BASE, KATANA_CPLD_SIZE, 0);
 415         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
 416         cpld_base = ioremap(KATANA_CPLD_BASE, KATANA_CPLD_SIZE);
 417
 418         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 419                  KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
 420         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 421         sram_base = ioremap(KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
 422
 423         /* Set up Enet->SRAM window */
 424         mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
 425                 KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
 426         bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
 427
 428         /* Give enet r/w access to memory region */
 429         mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
 430         mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
 431         mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
 432
 433         mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
 434         mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
 435                          ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
 436
 437         /* Must wait until window set up before retrieving board id */
 438         katana_get_board_id();
 439
 440         /* Enumerate pci bus (must know board id before getting proc number) */
 441         if (katana_get_proc_num() == 0)
 442                 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 0);
 443
 444 #if defined(CONFIG_NOT_COHERENT_CACHE)
 445         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
 446 #else
 447         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
 448 #endif
 449
 450         /*
 451          * Setting the SRAM to 0. Note that this generates parity errors on
 452          * internal data path in SRAM since it's first time accessing it
 453          * while after reset it's not configured.
 454          */
 455         memset(sram_base, 0, MV64360_SRAM_SIZE);
 456
 457         /* Only processor zero [on 3750] is an PCI interrupt controller */
 458         if (katana_get_proc_num() == 0)
 459                 katana_intr_setup();
 460 }
 461
 462 static void __init
 463 katana_enable_ipmi(void)
 464 {
 465         u8 reset_out;
 466
 467         /* Enable access to IPMI ctlr by clearing IPMI PORTSEL bit in CPLD */
 468         reset_out = in_8(cpld_base + KATANA_CPLD_RESET_OUT);
 469         reset_out &= ~KATANA_CPLD_RESET_OUT_PORTSEL;
 470         out_8(cpld_base + KATANA_CPLD_RESET_OUT, reset_out);
 471 }
 472
 473 static void __init
 474 katana_setup_arch(void)
 475 {
 476         if (ppc_md.progress)
 477                 ppc_md.progress("katana_setup_arch: enter", 0);
 478
 479         set_tb(0, 0);
 480
 481 #ifdef CONFIG_BLK_DEV_INITRD
 482         if (initrd_start)
 483                 ROOT_DEV = Root_RAM0;
 484         else
 485 #endif
 486 #ifdef   CONFIG_ROOT_NFS
 487                 ROOT_DEV = Root_NFS;
 488 #else
 489                 ROOT_DEV = Root_SDA2;
 490 #endif
 491
 492         /*
 493          * Set up the L2CR register.
 494          *
 495          * 750FX has only L2E, L2PE (bits 2-8 are reserved)
 496          * DD2.0 has bug that requires the L2 to be in WRT mode
 497          * avoid dirty data in cache
 498          */
 499         if (PVR_REV(mfspr(SPRN_PVR)) == 0x0200) {
 500                 printk(KERN_INFO "DD2.0 detected. Setting L2 cache"
 501                         "to Writethrough mode\n");
 502                 _set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2WT);
 503         } else
 504                 _set_L2CR(L2CR_L2E | L2CR_L2PE);
 505
 506         if (ppc_md.progress)
 507                 ppc_md.progress("katana_setup_arch: calling setup_bridge", 0);
 508
 509         katana_setup_bridge();
 510         katana_setup_peripherals();
 511         katana_enable_ipmi();
 512
 513         katana_bus_frequency = katana_bus_freq(cpld_base);
 514
 515         printk(KERN_INFO "Artesyn Communication Products, LLC - Katana(TM)\n");
 516         if (ppc_md.progress)
 517                 ppc_md.progress("katana_setup_arch: exit", 0);
 518 }
 519
 520 void
 521 katana_fixup_resources(struct pci_dev *dev)
 522 {
 523         u16     v16;
 524
 525         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES>>2);
 526
 527         pci_read_config_word(dev, PCI_COMMAND, &v16);
 528         v16 |= PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK;
 529         pci_write_config_word(dev, PCI_COMMAND, v16);
 530 }
 531
 532 static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */
 533          0,  0,  2,  2,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,/* 0-15*/
 534         16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40,  0 /*16-31*/
 535 };
 536
 537 static int
 538 katana_get_cpu_freq(void)
 539 {
 540         unsigned long   pll_cfg;
 541
 542         pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27;
 543         return katana_bus_frequency * cpu_750xx[pll_cfg]/2;
 544 }
 545
 546 /* Platform device data fixup routines. */
 547 #if defined(CONFIG_SERIAL_MPSC)
 548 static void __init
 549 katana_fixup_mpsc_pdata(struct platform_device *pdev)
 550 {
 551         struct mpsc_pdata *pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
 552         bd_t *bdp = (bd_t *)__res;
 553
 554         if (bdp->bi_baudrate)
 555                 pdata->default_baud = bdp->bi_baudrate;
 556         else
 557                 pdata->default_baud = KATANA_DEFAULT_BAUD;
 558
 559         pdata->max_idle = 40;
 560         pdata->brg_clk_src = KATANA_MPSC_CLK_SRC;
 561         /*
 562          * TCLK (not SysCLk) is routed to BRG, then to the MPSC.  On most parts,
 563          * TCLK == SysCLK but on 64460, they are separate pins.
 564          * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
 565          */
 566         pdata->brg_clk_freq = min(katana_bus_frequency, MV64x60_TCLK_FREQ_MAX);
 567 }
 568 #endif
 569
 570 #if defined(CONFIG_MV643XX_ETH)
 571 static void __init
 572 katana_fixup_eth_pdata(struct platform_device *pdev)
 573 {
 574         struct mv643xx_eth_platform_data *eth_pd;
 575         static u16 phy_addr[] = {
 576                 KATANA_ETH0_PHY_ADDR,
 577                 KATANA_ETH1_PHY_ADDR,
 578                 KATANA_ETH2_PHY_ADDR,
 579         };
 580
 581         eth_pd = pdev->dev.platform_data;
 582         eth_pd->force_phy_addr = 1;
 583         eth_pd->phy_addr = phy_addr[pdev->id];
 584         eth_pd->tx_queue_size = KATANA_ETH_TX_QUEUE_SIZE;
 585         eth_pd->rx_queue_size = KATANA_ETH_RX_QUEUE_SIZE;
 586 }
 587 #endif
 588
 589 #if defined(CONFIG_SYSFS)
 590 static void __init
 591 katana_fixup_mv64xxx_pdata(struct platform_device *pdev)
 592 {
 593         struct mv64xxx_pdata *pdata = (struct mv64xxx_pdata *)
 594                 pdev->dev.platform_data;
 595
 596         /* Katana supports the mv64xxx hotswap register */
 597         pdata->hs_reg_valid = 1;
 598 }
 599 #endif
 600
 601 static int __init
 602 katana_platform_notify(struct device *dev)
 603 {
 604         static struct {
 605                 char    *bus_id;
 606                 void    ((*rtn)(struct platform_device *pdev));
 607         } dev_map[] = {
 608 #if defined(CONFIG_SERIAL_MPSC)
 609                 { MPSC_CTLR_NAME ".0", katana_fixup_mpsc_pdata },
 610                 { MPSC_CTLR_NAME ".1", katana_fixup_mpsc_pdata },
 611 #endif
 612 #if defined(CONFIG_MV643XX_ETH)
 613                 { MV643XX_ETH_NAME ".0", katana_fixup_eth_pdata },
 614                 { MV643XX_ETH_NAME ".1", katana_fixup_eth_pdata },
 615                 { MV643XX_ETH_NAME ".2", katana_fixup_eth_pdata },
 616 #endif
 617 #if defined(CONFIG_SYSFS)
 618                 { MV64XXX_DEV_NAME ".0", katana_fixup_mv64xxx_pdata },
 619 #endif
 620         };
 621         struct platform_device  *pdev;
 622         int     i;
 623
 624         if (dev && dev->bus_id)
 625                 for (i=0; i<ARRAY_SIZE(dev_map); i++)
 626                         if (!strncmp(dev->bus_id, dev_map[i].bus_id,
 627                                         BUS_ID_SIZE)) {
 628                                 pdev = container_of(dev,
 629                                         struct platform_device, dev);
 630                                 dev_map[i].rtn(pdev);
 631                         }
 632
 633         return 0;
 634 }
 635
 636 #ifdef CONFIG_MTD_PHYSMAP
 637
 638 #ifndef MB
 639 #define MB      (1 << 20)
 640 #endif
 641
 642 /*
 643  * MTD Layout depends on amount of soldered FLASH in system. Sizes in MB.
 644  *
 645  * FLASH Amount:        128     64      32      16
 646  * -------------        ---     --      --      --
 647  * Monitor:             1       1       1       1
 648  * Primary Kernel:      1.5     1.5     1.5     1.5
 649  * Primary fs:          30      30      <end>   <end>
 650  * Secondary Kernel:    1.5     1.5     N/A     N/A
 651  * Secondary fs:        <end>   <end>   N/A     N/A
 652  * User:                <overlays entire FLASH except for "Monitor" section>
 653  */
 654 static int __init
 655 katana_setup_mtd(void)
 656 {
 657         u32     size;
 658         int     ptbl_entries;
 659         static struct mtd_partition     *ptbl;
 660
 661         size = katana_flash_size_0 + katana_flash_size_1;
 662         if (!size)
 663                 return -ENOMEM;
 664
 665         ptbl_entries = (size >= (64*MB)) ? 6 : 4;
 666
 667         if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition),
 668                         GFP_KERNEL)) == NULL) {
 669                 printk(KERN_WARNING "Can't alloc MTD partition table\n");
 670                 return -ENOMEM;
 671         }
 672         memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition));
 673
 674         ptbl[0].name = "Monitor";
 675         ptbl[0].size = KATANA_MTD_MONITOR_SIZE;
 676         ptbl[1].name = "Primary Kernel";
 677         ptbl[1].offset = MTDPART_OFS_NXTBLK;
 678         ptbl[1].size = 0x00180000; /* 1.5 MB */
 679         ptbl[2].name = "Primary Filesystem";
 680         ptbl[2].offset = MTDPART_OFS_APPEND;
 681         ptbl[2].size = MTDPART_SIZ_FULL; /* Correct for 16 & 32 MB */
 682         ptbl[ptbl_entries-1].name = "User FLASH";
 683         ptbl[ptbl_entries-1].offset = KATANA_MTD_MONITOR_SIZE;
 684         ptbl[ptbl_entries-1].size = MTDPART_SIZ_FULL;
 685
 686         if (size >= (64*MB)) {
 687                 ptbl[2].size = 30*MB;
 688                 ptbl[3].name = "Secondary Kernel";
 689                 ptbl[3].offset = MTDPART_OFS_NXTBLK;
 690                 ptbl[3].size = 0x00180000; /* 1.5 MB */
 691                 ptbl[4].name = "Secondary Filesystem";
 692                 ptbl[4].offset = MTDPART_OFS_APPEND;
 693                 ptbl[4].size = MTDPART_SIZ_FULL;
 694         }
 695
 696         physmap_map.size = size;
 697         physmap_set_partitions(ptbl, ptbl_entries);
 698         return 0;
 699 }
 700 arch_initcall(katana_setup_mtd);
 701 #endif
 702
 703 static void
 704 katana_restart(char *cmd)
 705 {
 706         ulong   i = 10000000;
 707
 708         /* issue hard reset to the reset command register */
 709         out_8(cpld_base + KATANA_CPLD_RST_CMD, KATANA_CPLD_RST_CMD_HR);
 710
 711         while (i-- > 0) ;
 712         panic("restart failed\n");
 713 }
 714
 715 static void
 716 katana_halt(void)
 717 {
 718         u8      v;
 719
 720         /* Turn on blue LED to indicate its okay to remove */
 721         if (katana_id == KATANA_ID_750I) {
 722                 u32     v;
 723                 u8      save_exclude;
 724
 725                 /* Set LOO bit in cPCI HotSwap reg of hose 0 to turn on LED. */
 726                 save_exclude = mv64x60_pci_exclude_bridge;
 727                 mv64x60_pci_exclude_bridge = 0;
 728                 early_read_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0),
 729                         MV64360_PCICFG_CPCI_HOTSWAP, &v);
 730                 v &= 0xff;
 731                 v |= (1 << 19);
 732                 early_write_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0),
 733                         MV64360_PCICFG_CPCI_HOTSWAP, v);
 734                 mv64x60_pci_exclude_bridge = save_exclude;
 735         } else if (katana_id == KATANA_ID_752I) {
 736                    v = in_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF);
 737                    v |= HSL_PLD_HOT_SWAP_LED_BIT;
 738                    out_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF, v);
 739         }
 740
 741         while (1) ;
 742         /* NOTREACHED */
 743 }
 744
 745 static void
 746 katana_power_off(void)
 747 {
 748         katana_halt();
 749         /* NOTREACHED */
 750 }
 751
 752 static int
 753 katana_show_cpuinfo(struct seq_file *m)
 754 {
 755         char    *s;
 756
 757         seq_printf(m, "cpu freq\t: %dMHz\n",
 758                 (katana_get_cpu_freq() + 500000) / 1000000);
 759         seq_printf(m, "bus freq\t: %ldMHz\n",
 760                 ((long)katana_bus_frequency + 500000) / 1000000);
 761         seq_printf(m, "vendor\t\t: Artesyn Communication Products, LLC\n");
 762
 763         seq_printf(m, "board\t\t: ");
 764         switch (katana_id) {
 765         case KATANA_ID_3750:
 766                 seq_printf(m, "Katana 3750");
 767                 break;
 768
 769         case KATANA_ID_750I:
 770                 seq_printf(m, "Katana 750i");
 771                 break;
 772
 773         case KATANA_ID_752I:
 774                 seq_printf(m, "Katana 752i");
 775                 break;
 776
 777         default:
 778                 seq_printf(m, "Unknown");
 779                 break;
 780         }
 781         seq_printf(m, " (product id: 0x%x)\n",
 782                    in_8(cpld_base + KATANA_CPLD_PRODUCT_ID));
 783
 784         seq_printf(m, "pci mode\t: %sMonarch\n",
 785                 katana_is_monarch()? "" : "Non-");
 786         seq_printf(m, "hardware rev\t: 0x%x\n",
 787                    in_8(cpld_base+KATANA_CPLD_HARDWARE_VER));
 788         seq_printf(m, "pld rev\t\t: 0x%x\n",
 789                    in_8(cpld_base + KATANA_CPLD_PLD_VER));
 790
 791         switch(bh.type) {
 792         case MV64x60_TYPE_GT64260A:
 793                 s = "gt64260a";
 794                 break;
 795         case MV64x60_TYPE_GT64260B:
 796                 s = "gt64260b";
 797                 break;
 798         case MV64x60_TYPE_MV64360:
 799                 s = "mv64360";
 800                 break;
 801         case MV64x60_TYPE_MV64460:
 802                 s = "mv64460";
 803                 break;
 804         default:
 805                 s = "Unknown";
 806         }
 807         seq_printf(m, "bridge type\t: %s\n", s);
 808         seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev);
 809 #if defined(CONFIG_NOT_COHERENT_CACHE)
 810         seq_printf(m, "coherency\t: %s\n", "off");
 811 #else
 812         seq_printf(m, "coherency\t: %s\n", "on");
 813 #endif
 814
 815         return 0;
 816 }
 817
 818 static void __init
 819 katana_calibrate_decr(void)
 820 {
 821         u32 freq;
 822
 823         freq = katana_bus_frequency / 4;
 824
 825         printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
 826                (long)freq / 1000000, (long)freq % 1000000);
 827
 828         tb_ticks_per_jiffy = freq / HZ;
 829         tb_to_us = mulhwu_scale_factor(freq, 1000000);
 830 }
 831
 832 /*
 833  * The katana supports both uImage and zImage.  If uImage, get the mem size
 834  * from the bd info.  If zImage, the bootwrapper adds a BI_MEMSIZE entry in
 835  * the bi_rec data which is sucked out and put into boot_mem_size by
 836  * parse_bootinfo().  MMU_init() will then use the boot_mem_size for the mem
 837  * size and not call this routine.  The only way this will fail is when a uImage
 838  * is used but the fw doesn't pass in a valid bi_memsize.  This should never
 839  * happen, though.
 840  */
 841 unsigned long __init
 842 katana_find_end_of_memory(void)
 843 {
 844         bd_t *bdp = (bd_t *)__res;
 845         return bdp->bi_memsize;
 846 }
 847
 848 #if defined(CONFIG_I2C_MV64XXX) && defined(CONFIG_SENSORS_M41T00)
 849 extern ulong    m41t00_get_rtc_time(void);
 850 extern int      m41t00_set_rtc_time(ulong);
 851
 852 static int __init
 853 katana_rtc_hookup(void)
 854 {
 855         struct timespec tv;
 856
 857         ppc_md.get_rtc_time = m41t00_get_rtc_time;
 858         ppc_md.set_rtc_time = m41t00_set_rtc_time;
 859
 860         tv.tv_nsec = 0;
 861         tv.tv_sec = (ppc_md.get_rtc_time)();
 862         do_settimeofday(&tv);
 863
 864         return 0;
 865 }
 866 late_initcall(katana_rtc_hookup);
 867 #endif
 868
 869 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
 870 static void __init
 871 katana_map_io(void)
 872 {
 873         io_block_mapping(0xf8100000, 0xf8100000, 0x00020000, _PAGE_IO);
 874 }
 875 #endif
 876
 877 void __init
 878 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 879               unsigned long r6, unsigned long r7)
 880 {
 881         parse_bootinfo(find_bootinfo());
 882
 883         /* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)
 884          * are non-zero, then we should use the board info from the bd_t
 885          * structure and the cmdline pointed to by r6 instead of the
 886          * information from birecs, if any.  Otherwise, use the information
 887          * from birecs as discovered by the preceeding call to
 888          * parse_bootinfo().  This rule should work with both PPCBoot, which
 889          * uses a bd_t board info structure, and the kernel boot wrapper,
 890          * which uses birecs.
 891          */
 892         if (r3 && r6) {
 893                 /* copy board info structure */
 894                 memcpy((void *)__res, (void *)(r3+KERNELBASE), sizeof(bd_t));
 895                 /* copy command line */
 896                 *(char *)(r7+KERNELBASE) = 0;
 897                 strcpy(cmd_line, (char *)(r6+KERNELBASE));
 898         }
 899
 900 #ifdef CONFIG_BLK_DEV_INITRD
 901         /* take care of initrd if we have one */
 902         if (r4) {
 903                 initrd_start = r4 + KERNELBASE;
 904                 initrd_end = r5 + KERNELBASE;
 905         }
 906 #endif /* CONFIG_BLK_DEV_INITRD */
 907
 908         isa_mem_base = 0;
 909
 910         ppc_md.setup_arch = katana_setup_arch;
 911         ppc_md.pcibios_fixup_resources = katana_fixup_resources;
 912         ppc_md.show_cpuinfo = katana_show_cpuinfo;
 913         ppc_md.init_IRQ = mv64360_init_irq;
 914         ppc_md.get_irq = mv64360_get_irq;
 915         ppc_md.restart = katana_restart;
 916         ppc_md.power_off = katana_power_off;
 917         ppc_md.halt = katana_halt;
 918         ppc_md.find_end_of_memory = katana_find_end_of_memory;
 919         ppc_md.calibrate_decr = katana_calibrate_decr;
 920
 921 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
 922         ppc_md.setup_io_mappings = katana_map_io;
 923         ppc_md.progress = mv64x60_mpsc_progress;
 924         mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
 925 #endif
 926
 927 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
 928         platform_notify = katana_platform_notify;
 929 #endif
 930 }