include/asm-blackfin/mach-bf527/bfin_serial_5xx.h

   1 /*
   2  * file:        include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
   3  * based on:
   4  * author:
   5  *
   6  * created:
   7  * description:
   8  *      blackfin serial driver head file
   9  * rev:
  10  *
  11  * modified:
  12  *
  13  *
  14  * bugs:         enter bugs at http://blackfin.uclinux.org/
  15  *
  16  * this program is free software; you can redistribute it and/or modify
  17  * it under the terms of the gnu general public license as published by
  18  * the free software foundation; either version 2, or (at your option)
  19  * any later version.
  20  *
  21  * this program is distributed in the hope that it will be useful,
  22  * but without any warranty; without even the implied warranty of
  23  * merchantability or fitness for a particular purpose.  see the
  24  * gnu general public license for more details.
  25  *
  26  * you should have received a copy of the gnu general public license
  27  * along with this program; see the file copying.
  28  * if not, write to the free software foundation,
  29  * 59 temple place - suite 330, boston, ma 02111-1307, usa.
  30  */
  31
  32 #include <linux/serial.h>
  33 #include <asm/dma.h>
  34 #include <asm/portmux.h>
  35
  36 #define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
  37 #define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
  38 #define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
  39 #define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
  40 #define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
  41 #define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
  42 #define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  43
  44 #define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
  45 #define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
  46 #define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
  47 #define UART_SET_IER(uart, v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
  48 #define UART_CLEAR_IER(uart, v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
  49 #define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
  50 #define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
  51 #define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
  52
  53 #define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
  54 #define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
  55
  56 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
  57 # define CONFIG_SERIAL_BFIN_CTSRTS
  58
  59 # ifndef CONFIG_UART0_CTS_PIN
  60 #  define CONFIG_UART0_CTS_PIN -1
  61 # endif
  62
  63 # ifndef CONFIG_UART0_RTS_PIN
  64 #  define CONFIG_UART0_RTS_PIN -1
  65 # endif
  66
  67 # ifndef CONFIG_UART1_CTS_PIN
  68 #  define CONFIG_UART1_CTS_PIN -1
  69 # endif
  70
  71 # ifndef CONFIG_UART1_RTS_PIN
  72 #  define CONFIG_UART1_RTS_PIN -1
  73 # endif
  74 #endif
  75 /*
  76  * The pin configuration is different from schematic
  77  */
  78 struct bfin_serial_port {
  79         struct uart_port port;
  80         unsigned int old_status;
  81         unsigned int lsr;
  82 #ifdef CONFIG_SERIAL_BFIN_DMA
  83         int tx_done;
  84         int tx_count;
  85         struct circ_buf rx_dma_buf;
  86         struct timer_list rx_dma_timer;
  87         int rx_dma_nrows;
  88         unsigned int tx_dma_channel;
  89         unsigned int rx_dma_channel;
  90         struct work_struct tx_dma_workqueue;
  91 #endif
  92 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  93         struct work_struct cts_workqueue;
  94         int cts_pin;
  95         int rts_pin;
  96 #endif
  97 };
  98
  99 /* The hardware clears the LSR bits upon read, so we need to cache
 100  * some of the more fun bits in software so they don't get lost
 101  * when checking the LSR in other code paths (TX).
 102  */
 103 static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
 104 {
 105         unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
 106         uart->lsr |= (lsr & (BI|FE|PE|OE));
 107         return lsr | uart->lsr;
 108 }
 109
 110 static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
 111 {
 112         uart->lsr = 0;
 113         bfin_write16(uart->port.membase + OFFSET_LSR, -1);
 114 }
 115
 116 struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
 117 struct bfin_serial_res {
 118         unsigned long uart_base_addr;
 119         int uart_irq;
 120 #ifdef CONFIG_SERIAL_BFIN_DMA
 121         unsigned int uart_tx_dma_channel;
 122         unsigned int uart_rx_dma_channel;
 123 #endif
 124 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 125         int uart_cts_pin;
 126         int uart_rts_pin;
 127 #endif
 128 };
 129
 130 struct bfin_serial_res bfin_serial_resource[] = {
 131 #ifdef CONFIG_SERIAL_BFIN_UART0
 132         {
 133          0xFFC00400,
 134          IRQ_UART0_RX,
 135 #ifdef CONFIG_SERIAL_BFIN_DMA
 136          CH_UART0_TX,
 137          CH_UART0_RX,
 138 #endif
 139 #ifdef CONFIG_BFIN_UART0_CTSRTS
 140          CONFIG_UART0_CTS_PIN,
 141          CONFIG_UART0_RTS_PIN,
 142 #endif
 143          },
 144 #endif
 145 #ifdef CONFIG_SERIAL_BFIN_UART1
 146         {
 147          0xFFC02000,
 148          IRQ_UART1_RX,
 149 #ifdef CONFIG_SERIAL_BFIN_DMA
 150          CH_UART1_TX,
 151          CH_UART1_RX,
 152 #endif
 153 #ifdef CONFIG_BFIN_UART1_CTSRTS
 154          CONFIG_UART1_CTS_PIN,
 155          CONFIG_UART1_RTS_PIN,
 156 #endif
 157          },
 158 #endif
 159 };
 160
 161 int nr_ports = ARRAY_SIZE(bfin_serial_resource);
 162
 163 #define DRIVER_NAME "bfin-uart"
 164
 165 static void bfin_serial_hw_init(struct bfin_serial_port *uart)
 166 {
 167
 168 #ifdef CONFIG_SERIAL_BFIN_UART0
 169         peripheral_request(P_UART0_TX, DRIVER_NAME);
 170         peripheral_request(P_UART0_RX, DRIVER_NAME);
 171 #endif
 172
 173 #ifdef CONFIG_SERIAL_BFIN_UART1
 174         peripheral_request(P_UART1_TX, DRIVER_NAME);
 175         peripheral_request(P_UART1_RX, DRIVER_NAME);
 176 #endif
 177
 178 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 179         if (uart->cts_pin >= 0) {
 180                 gpio_request(uart->cts_pin, DRIVER_NAME);
 181                 gpio_direction_input(uart->cts_pin);
 182         }
 183
 184         if (uart->rts_pin >= 0) {
 185                 gpio_request(uart->rts_pin, DRIVER_NAME);
 186                 gpio_direction_output(uart->rts_pin, 0);
 187         }
 188 #endif
 189 }