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[SCSI] sym2: Use DMA_40BIT_MASK constant
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / scsi / sata_sil24.c
blobe0d6f194f54f50217b047083300c32133b35e18e
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31 #include <asm/io.h>
32
33 #define DRV_NAME "sata_sil24"
34 #define DRV_VERSION "0.23"
35
36 /*
37 * Port request block (PRB) 32 bytes
38 */
39 struct sil24_prb {
40 u16 ctrl;
41 u16 prot;
42 u32 rx_cnt;
43 u8 fis[6 * 4];
44 };
45
46 /*
47 * Scatter gather entry (SGE) 16 bytes
48 */
49 struct sil24_sge {
50 u64 addr;
51 u32 cnt;
52 u32 flags;
53 };
54
55 /*
56 * Port multiplier
57 */
58 struct sil24_port_multiplier {
59 u32 diag;
60 u32 sactive;
61 };
62
63 enum {
64 /*
65 * Global controller registers (128 bytes @ BAR0)
66 */
67 /* 32 bit regs */
68 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
69 HOST_CTRL = 0x40,
70 HOST_IRQ_STAT = 0x44,
71 HOST_PHY_CFG = 0x48,
72 HOST_BIST_CTRL = 0x50,
73 HOST_BIST_PTRN = 0x54,
74 HOST_BIST_STAT = 0x58,
75 HOST_MEM_BIST_STAT = 0x5c,
76 HOST_FLASH_CMD = 0x70,
77 /* 8 bit regs */
78 HOST_FLASH_DATA = 0x74,
79 HOST_TRANSITION_DETECT = 0x75,
80 HOST_GPIO_CTRL = 0x76,
81 HOST_I2C_ADDR = 0x78, /* 32 bit */
82 HOST_I2C_DATA = 0x7c,
83 HOST_I2C_XFER_CNT = 0x7e,
84 HOST_I2C_CTRL = 0x7f,
85
86 /* HOST_SLOT_STAT bits */
87 HOST_SSTAT_ATTN = (1 << 31),
88
89 /*
90 * Port registers
91 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
92 */
93 PORT_REGS_SIZE = 0x2000,
94 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
95
96 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
97 /* 32 bit regs */
98 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
99 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
100 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
101 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
102 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
103 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
104 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
105 PORT_CMD_ERR = 0x1024, /* command error number */
106 PORT_FIS_CFG = 0x1028,
107 PORT_FIFO_THRES = 0x102c,
108 /* 16 bit regs */
109 PORT_DECODE_ERR_CNT = 0x1040,
110 PORT_DECODE_ERR_THRESH = 0x1042,
111 PORT_CRC_ERR_CNT = 0x1044,
112 PORT_CRC_ERR_THRESH = 0x1046,
113 PORT_HSHK_ERR_CNT = 0x1048,
114 PORT_HSHK_ERR_THRESH = 0x104a,
115 /* 32 bit regs */
116 PORT_PHY_CFG = 0x1050,
117 PORT_SLOT_STAT = 0x1800,
118 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
119 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
120 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
121 PORT_SCONTROL = 0x1f00,
122 PORT_SSTATUS = 0x1f04,
123 PORT_SERROR = 0x1f08,
124 PORT_SACTIVE = 0x1f0c,
125
126 /* PORT_CTRL_STAT bits */
127 PORT_CS_PORT_RST = (1 << 0), /* port reset */
128 PORT_CS_DEV_RST = (1 << 1), /* device reset */
129 PORT_CS_INIT = (1 << 2), /* port initialize */
130 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
131 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
132 PORT_CS_RESUME = (1 << 6), /* port resume */
133 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
134 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
135 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
136
137 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
138 /* bits[11:0] are masked */
139 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
140 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
141 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
142 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
143 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
144 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
145 PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */
146 PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */
147
148 /* bits[27:16] are unmasked (raw) */
149 PORT_IRQ_RAW_SHIFT = 16,
150 PORT_IRQ_MASKED_MASK = 0x7ff,
151 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
152
153 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
154 PORT_IRQ_STEER_SHIFT = 30,
155 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
156
157 /* PORT_CMD_ERR constants */
158 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
159 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
160 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
161 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
162 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
163 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
164 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
165 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
166 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
167 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
168 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
169 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
170 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
171 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
172 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
173 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
174 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
175 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
176 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
177 PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */
178 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
179 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
180
181 /* bits of PRB control field */
182 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
183 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
184 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
185 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
186 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
187
188 /* PRB protocol field */
189 PRB_PROT_PACKET = (1 << 0),
190 PRB_PROT_TCQ = (1 << 1),
191 PRB_PROT_NCQ = (1 << 2),
192 PRB_PROT_READ = (1 << 3),
193 PRB_PROT_WRITE = (1 << 4),
194 PRB_PROT_TRANSPARENT = (1 << 5),
195
196 /*
197 * Other constants
198 */
199 SGE_TRM = (1 << 31), /* Last SGE in chain */
200 SGE_LNK = (1 << 30), /* linked list
201 Points to SGT, not SGE */
202 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
203 data address ignored */
204
205 /* board id */
206 BID_SIL3124 = 0,
207 BID_SIL3132 = 1,
208 BID_SIL3131 = 2,
209
210 IRQ_STAT_4PORTS = 0xf,
211 };
212
213 struct sil24_ata_block {
214 struct sil24_prb prb;
215 struct sil24_sge sge[LIBATA_MAX_PRD];
216 };
217
218 struct sil24_atapi_block {
219 struct sil24_prb prb;
220 u8 cdb[16];
221 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
222 };
223
224 union sil24_cmd_block {
225 struct sil24_ata_block ata;
226 struct sil24_atapi_block atapi;
227 };
228
229 /*
230 * ap->private_data
231 *
232 * The preview driver always returned 0 for status. We emulate it
233 * here from the previous interrupt.
234 */
235 struct sil24_port_priv {
236 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
237 dma_addr_t cmd_block_dma; /* DMA base addr for them */
238 struct ata_taskfile tf; /* Cached taskfile registers */
239 };
240
241 /* ap->host_set->private_data */
242 struct sil24_host_priv {
243 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
244 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
245 };
246
247 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev);
248 static u8 sil24_check_status(struct ata_port *ap);
249 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
250 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
251 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
252 static void sil24_phy_reset(struct ata_port *ap);
253 static void sil24_qc_prep(struct ata_queued_cmd *qc);
254 static int sil24_qc_issue(struct ata_queued_cmd *qc);
255 static void sil24_irq_clear(struct ata_port *ap);
256 static void sil24_eng_timeout(struct ata_port *ap);
257 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
258 static int sil24_port_start(struct ata_port *ap);
259 static void sil24_port_stop(struct ata_port *ap);
260 static void sil24_host_stop(struct ata_host_set *host_set);
261 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
262
263 static const struct pci_device_id sil24_pci_tbl[] = {
264 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
265 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
266 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
267 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
268 { } /* terminate list */
269 };
270
271 static struct pci_driver sil24_pci_driver = {
272 .name = DRV_NAME,
273 .id_table = sil24_pci_tbl,
274 .probe = sil24_init_one,
275 .remove = ata_pci_remove_one, /* safe? */
276 };
277
278 static struct scsi_host_template sil24_sht = {
279 .module = THIS_MODULE,
280 .name = DRV_NAME,
281 .ioctl = ata_scsi_ioctl,
282 .queuecommand = ata_scsi_queuecmd,
283 .eh_strategy_handler = ata_scsi_error,
284 .can_queue = ATA_DEF_QUEUE,
285 .this_id = ATA_SHT_THIS_ID,
286 .sg_tablesize = LIBATA_MAX_PRD,
287 .max_sectors = ATA_MAX_SECTORS,
288 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
289 .emulated = ATA_SHT_EMULATED,
290 .use_clustering = ATA_SHT_USE_CLUSTERING,
291 .proc_name = DRV_NAME,
292 .dma_boundary = ATA_DMA_BOUNDARY,
293 .slave_configure = ata_scsi_slave_config,
294 .bios_param = ata_std_bios_param,
295 .ordered_flush = 1, /* NCQ not supported yet */
296 };
297
298 static const struct ata_port_operations sil24_ops = {
299 .port_disable = ata_port_disable,
300
301 .dev_config = sil24_dev_config,
302
303 .check_status = sil24_check_status,
304 .check_altstatus = sil24_check_status,
305 .dev_select = ata_noop_dev_select,
306
307 .tf_read = sil24_tf_read,
308
309 .phy_reset = sil24_phy_reset,
310
311 .qc_prep = sil24_qc_prep,
312 .qc_issue = sil24_qc_issue,
313
314 .eng_timeout = sil24_eng_timeout,
315
316 .irq_handler = sil24_interrupt,
317 .irq_clear = sil24_irq_clear,
318
319 .scr_read = sil24_scr_read,
320 .scr_write = sil24_scr_write,
321
322 .port_start = sil24_port_start,
323 .port_stop = sil24_port_stop,
324 .host_stop = sil24_host_stop,
325 };
326
327 /*
328 * Use bits 30-31 of host_flags to encode available port numbers.
329 * Current maxium is 4.
330 */
331 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
332 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
333
334 static struct ata_port_info sil24_port_info[] = {
335 /* sil_3124 */
336 {
337 .sht = &sil24_sht,
338 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
339 ATA_FLAG_SRST | ATA_FLAG_MMIO |
340 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(4),
341 .pio_mask = 0x1f, /* pio0-4 */
342 .mwdma_mask = 0x07, /* mwdma0-2 */
343 .udma_mask = 0x3f, /* udma0-5 */
344 .port_ops = &sil24_ops,
345 },
346 /* sil_3132 */
347 {
348 .sht = &sil24_sht,
349 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
350 ATA_FLAG_SRST | ATA_FLAG_MMIO |
351 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(2),
352 .pio_mask = 0x1f, /* pio0-4 */
353 .mwdma_mask = 0x07, /* mwdma0-2 */
354 .udma_mask = 0x3f, /* udma0-5 */
355 .port_ops = &sil24_ops,
356 },
357 /* sil_3131/sil_3531 */
358 {
359 .sht = &sil24_sht,
360 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
361 ATA_FLAG_SRST | ATA_FLAG_MMIO |
362 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(1),
363 .pio_mask = 0x1f, /* pio0-4 */
364 .mwdma_mask = 0x07, /* mwdma0-2 */
365 .udma_mask = 0x3f, /* udma0-5 */
366 .port_ops = &sil24_ops,
367 },
368 };
369
370 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev)
371 {
372 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
373
374 if (ap->cdb_len == 16)
375 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
376 else
377 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
378 }
379
380 static inline void sil24_update_tf(struct ata_port *ap)
381 {
382 struct sil24_port_priv *pp = ap->private_data;
383 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
384 struct sil24_prb __iomem *prb = port;
385 u8 fis[6 * 4];
386
387 memcpy_fromio(fis, prb->fis, 6 * 4);
388 ata_tf_from_fis(fis, &pp->tf);
389 }
390
391 static u8 sil24_check_status(struct ata_port *ap)
392 {
393 struct sil24_port_priv *pp = ap->private_data;
394 return pp->tf.command;
395 }
396
397 static int sil24_scr_map[] = {
398 [SCR_CONTROL] = 0,
399 [SCR_STATUS] = 1,
400 [SCR_ERROR] = 2,
401 [SCR_ACTIVE] = 3,
402 };
403
404 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
405 {
406 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
407 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
408 void __iomem *addr;
409 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
410 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
411 }
412 return 0xffffffffU;
413 }
414
415 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
416 {
417 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
418 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
419 void __iomem *addr;
420 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
421 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
422 }
423 }
424
425 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
426 {
427 struct sil24_port_priv *pp = ap->private_data;
428 *tf = pp->tf;
429 }
430
431 static int sil24_issue_SRST(struct ata_port *ap)
432 {
433 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
434 struct sil24_port_priv *pp = ap->private_data;
435 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
436 dma_addr_t paddr = pp->cmd_block_dma;
437 u32 irq_enable, irq_stat;
438 int cnt;
439
440 /* temporarily turn off IRQs during SRST */
441 irq_enable = readl(port + PORT_IRQ_ENABLE_SET);
442 writel(irq_enable, port + PORT_IRQ_ENABLE_CLR);
443
444 /*
445 * XXX: Not sure whether the following sleep is needed or not.
446 * The original driver had it. So....
447 */
448 msleep(10);
449
450 prb->ctrl = PRB_CTRL_SRST;
451 prb->fis[1] = 0; /* no PM yet */
452
453 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
454
455 for (cnt = 0; cnt < 100; cnt++) {
456 irq_stat = readl(port + PORT_IRQ_STAT);
457 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
458
459 irq_stat >>= PORT_IRQ_RAW_SHIFT;
460 if (irq_stat & (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR))
461 break;
462
463 msleep(1);
464 }
465
466 /* restore IRQs */
467 writel(irq_enable, port + PORT_IRQ_ENABLE_SET);
468
469 if (!(irq_stat & PORT_IRQ_COMPLETE))
470 return -1;
471
472 /* update TF */
473 sil24_update_tf(ap);
474 return 0;
475 }
476
477 static void sil24_phy_reset(struct ata_port *ap)
478 {
479 struct sil24_port_priv *pp = ap->private_data;
480
481 __sata_phy_reset(ap);
482 if (ap->flags & ATA_FLAG_PORT_DISABLED)
483 return;
484
485 if (sil24_issue_SRST(ap) < 0) {
486 printk(KERN_ERR DRV_NAME
487 " ata%u: SRST failed, disabling port\n", ap->id);
488 ap->ops->port_disable(ap);
489 return;
490 }
491
492 ap->device->class = ata_dev_classify(&pp->tf);
493 }
494
495 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
496 struct sil24_sge *sge)
497 {
498 struct scatterlist *sg;
499 unsigned int idx = 0;
500
501 ata_for_each_sg(sg, qc) {
502 sge->addr = cpu_to_le64(sg_dma_address(sg));
503 sge->cnt = cpu_to_le32(sg_dma_len(sg));
504 if (ata_sg_is_last(sg, qc))
505 sge->flags = cpu_to_le32(SGE_TRM);
506 else
507 sge->flags = 0;
508
509 sge++;
510 idx++;
511 }
512 }
513
514 static void sil24_qc_prep(struct ata_queued_cmd *qc)
515 {
516 struct ata_port *ap = qc->ap;
517 struct sil24_port_priv *pp = ap->private_data;
518 union sil24_cmd_block *cb = pp->cmd_block + qc->tag;
519 struct sil24_prb *prb;
520 struct sil24_sge *sge;
521
522 switch (qc->tf.protocol) {
523 case ATA_PROT_PIO:
524 case ATA_PROT_DMA:
525 case ATA_PROT_NODATA:
526 prb = &cb->ata.prb;
527 sge = cb->ata.sge;
528 prb->ctrl = 0;
529 break;
530
531 case ATA_PROT_ATAPI:
532 case ATA_PROT_ATAPI_DMA:
533 case ATA_PROT_ATAPI_NODATA:
534 prb = &cb->atapi.prb;
535 sge = cb->atapi.sge;
536 memset(cb->atapi.cdb, 0, 32);
537 memcpy(cb->atapi.cdb, qc->cdb, ap->cdb_len);
538
539 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
540 if (qc->tf.flags & ATA_TFLAG_WRITE)
541 prb->ctrl = PRB_CTRL_PACKET_WRITE;
542 else
543 prb->ctrl = PRB_CTRL_PACKET_READ;
544 } else
545 prb->ctrl = 0;
546
547 break;
548
549 default:
550 prb = NULL; /* shut up, gcc */
551 sge = NULL;
552 BUG();
553 }
554
555 ata_tf_to_fis(&qc->tf, prb->fis, 0);
556
557 if (qc->flags & ATA_QCFLAG_DMAMAP)
558 sil24_fill_sg(qc, sge);
559 }
560
561 static int sil24_qc_issue(struct ata_queued_cmd *qc)
562 {
563 struct ata_port *ap = qc->ap;
564 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
565 struct sil24_port_priv *pp = ap->private_data;
566 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
567
568 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
569 return 0;
570 }
571
572 static void sil24_irq_clear(struct ata_port *ap)
573 {
574 /* unused */
575 }
576
577 static int __sil24_restart_controller(void __iomem *port)
578 {
579 u32 tmp;
580 int cnt;
581
582 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
583
584 /* Max ~10ms */
585 for (cnt = 0; cnt < 10000; cnt++) {
586 tmp = readl(port + PORT_CTRL_STAT);
587 if (tmp & PORT_CS_RDY)
588 return 0;
589 udelay(1);
590 }
591
592 return -1;
593 }
594
595 static void sil24_restart_controller(struct ata_port *ap)
596 {
597 if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr))
598 printk(KERN_ERR DRV_NAME
599 " ata%u: failed to restart controller\n", ap->id);
600 }
601
602 static int __sil24_reset_controller(void __iomem *port)
603 {
604 int cnt;
605 u32 tmp;
606
607 /* Reset controller state. Is this correct? */
608 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
609 readl(port + PORT_CTRL_STAT); /* sync */
610
611 /* Max ~100ms */
612 for (cnt = 0; cnt < 1000; cnt++) {
613 udelay(100);
614 tmp = readl(port + PORT_CTRL_STAT);
615 if (!(tmp & PORT_CS_DEV_RST))
616 break;
617 }
618
619 if (tmp & PORT_CS_DEV_RST)
620 return -1;
621
622 if (tmp & PORT_CS_RDY)
623 return 0;
624
625 return __sil24_restart_controller(port);
626 }
627
628 static void sil24_reset_controller(struct ata_port *ap)
629 {
630 printk(KERN_NOTICE DRV_NAME
631 " ata%u: resetting controller...\n", ap->id);
632 if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr))
633 printk(KERN_ERR DRV_NAME
634 " ata%u: failed to reset controller\n", ap->id);
635 }
636
637 static void sil24_eng_timeout(struct ata_port *ap)
638 {
639 struct ata_queued_cmd *qc;
640
641 qc = ata_qc_from_tag(ap, ap->active_tag);
642 if (!qc) {
643 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
644 ap->id);
645 return;
646 }
647
648 /*
649 * hack alert! We cannot use the supplied completion
650 * function from inside the ->eh_strategy_handler() thread.
651 * libata is the only user of ->eh_strategy_handler() in
652 * any kernel, so the default scsi_done() assumes it is
653 * not being called from the SCSI EH.
654 */
655 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
656 qc->scsidone = scsi_finish_command;
657 ata_qc_complete(qc, AC_ERR_OTHER);
658
659 sil24_reset_controller(ap);
660 }
661
662 static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
663 {
664 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
665 struct sil24_port_priv *pp = ap->private_data;
666 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
667 u32 irq_stat, cmd_err, sstatus, serror;
668 unsigned int err_mask;
669
670 irq_stat = readl(port + PORT_IRQ_STAT);
671 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
672
673 if (!(irq_stat & PORT_IRQ_ERROR)) {
674 /* ignore non-completion, non-error irqs for now */
675 printk(KERN_WARNING DRV_NAME
676 "ata%u: non-error exception irq (irq_stat %x)\n",
677 ap->id, irq_stat);
678 return;
679 }
680
681 cmd_err = readl(port + PORT_CMD_ERR);
682 sstatus = readl(port + PORT_SSTATUS);
683 serror = readl(port + PORT_SERROR);
684 if (serror)
685 writel(serror, port + PORT_SERROR);
686
687 /*
688 * Don't log ATAPI device errors. They're supposed to happen
689 * and any serious errors will be logged using sense data by
690 * the SCSI layer.
691 */
692 if (ap->device[0].class != ATA_DEV_ATAPI || cmd_err > PORT_CERR_SDB)
693 printk("ata%u: error interrupt on port%d\n"
694 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
695 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
696
697 if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
698 /*
699 * Device is reporting error, tf registers are valid.
700 */
701 sil24_update_tf(ap);
702 err_mask = ac_err_mask(pp->tf.command);
703 sil24_restart_controller(ap);
704 } else {
705 /*
706 * Other errors. libata currently doesn't have any
707 * mechanism to report these errors. Just turn on
708 * ATA_ERR.
709 */
710 err_mask = AC_ERR_OTHER;
711 sil24_reset_controller(ap);
712 }
713
714 if (qc)
715 ata_qc_complete(qc, err_mask);
716 }
717
718 static inline void sil24_host_intr(struct ata_port *ap)
719 {
720 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
721 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
722 u32 slot_stat;
723
724 slot_stat = readl(port + PORT_SLOT_STAT);
725 if (!(slot_stat & HOST_SSTAT_ATTN)) {
726 struct sil24_port_priv *pp = ap->private_data;
727 /*
728 * !HOST_SSAT_ATTN guarantees successful completion,
729 * so reading back tf registers is unnecessary for
730 * most commands. TODO: read tf registers for
731 * commands which require these values on successful
732 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
733 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
734 */
735 sil24_update_tf(ap);
736
737 if (qc)
738 ata_qc_complete(qc, ac_err_mask(pp->tf.command));
739 } else
740 sil24_error_intr(ap, slot_stat);
741 }
742
743 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
744 {
745 struct ata_host_set *host_set = dev_instance;
746 struct sil24_host_priv *hpriv = host_set->private_data;
747 unsigned handled = 0;
748 u32 status;
749 int i;
750
751 status = readl(hpriv->host_base + HOST_IRQ_STAT);
752
753 if (status == 0xffffffff) {
754 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
755 "PCI fault or device removal?\n");
756 goto out;
757 }
758
759 if (!(status & IRQ_STAT_4PORTS))
760 goto out;
761
762 spin_lock(&host_set->lock);
763
764 for (i = 0; i < host_set->n_ports; i++)
765 if (status & (1 << i)) {
766 struct ata_port *ap = host_set->ports[i];
767 if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED)) {
768 sil24_host_intr(host_set->ports[i]);
769 handled++;
770 } else
771 printk(KERN_ERR DRV_NAME
772 ": interrupt from disabled port %d\n", i);
773 }
774
775 spin_unlock(&host_set->lock);
776 out:
777 return IRQ_RETVAL(handled);
778 }
779
780 static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
781 {
782 const size_t cb_size = sizeof(*pp->cmd_block);
783
784 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
785 }
786
787 static int sil24_port_start(struct ata_port *ap)
788 {
789 struct device *dev = ap->host_set->dev;
790 struct sil24_port_priv *pp;
791 union sil24_cmd_block *cb;
792 size_t cb_size = sizeof(*cb);
793 dma_addr_t cb_dma;
794 int rc = -ENOMEM;
795
796 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
797 if (!pp)
798 goto err_out;
799
800 pp->tf.command = ATA_DRDY;
801
802 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
803 if (!cb)
804 goto err_out_pp;
805 memset(cb, 0, cb_size);
806
807 rc = ata_pad_alloc(ap, dev);
808 if (rc)
809 goto err_out_pad;
810
811 pp->cmd_block = cb;
812 pp->cmd_block_dma = cb_dma;
813
814 ap->private_data = pp;
815
816 return 0;
817
818 err_out_pad:
819 sil24_cblk_free(pp, dev);
820 err_out_pp:
821 kfree(pp);
822 err_out:
823 return rc;
824 }
825
826 static void sil24_port_stop(struct ata_port *ap)
827 {
828 struct device *dev = ap->host_set->dev;
829 struct sil24_port_priv *pp = ap->private_data;
830
831 sil24_cblk_free(pp, dev);
832 ata_pad_free(ap, dev);
833 kfree(pp);
834 }
835
836 static void sil24_host_stop(struct ata_host_set *host_set)
837 {
838 struct sil24_host_priv *hpriv = host_set->private_data;
839
840 iounmap(hpriv->host_base);
841 iounmap(hpriv->port_base);
842 kfree(hpriv);
843 }
844
845 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
846 {
847 static int printed_version = 0;
848 unsigned int board_id = (unsigned int)ent->driver_data;
849 struct ata_port_info *pinfo = &sil24_port_info[board_id];
850 struct ata_probe_ent *probe_ent = NULL;
851 struct sil24_host_priv *hpriv = NULL;
852 void __iomem *host_base = NULL;
853 void __iomem *port_base = NULL;
854 int i, rc;
855
856 if (!printed_version++)
857 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
858
859 rc = pci_enable_device(pdev);
860 if (rc)
861 return rc;
862
863 rc = pci_request_regions(pdev, DRV_NAME);
864 if (rc)
865 goto out_disable;
866
867 rc = -ENOMEM;
868 /* ioremap mmio registers */
869 host_base = ioremap(pci_resource_start(pdev, 0),
870 pci_resource_len(pdev, 0));
871 if (!host_base)
872 goto out_free;
873 port_base = ioremap(pci_resource_start(pdev, 2),
874 pci_resource_len(pdev, 2));
875 if (!port_base)
876 goto out_free;
877
878 /* allocate & init probe_ent and hpriv */
879 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
880 if (!probe_ent)
881 goto out_free;
882
883 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
884 if (!hpriv)
885 goto out_free;
886
887 memset(probe_ent, 0, sizeof(*probe_ent));
888 probe_ent->dev = pci_dev_to_dev(pdev);
889 INIT_LIST_HEAD(&probe_ent->node);
890
891 probe_ent->sht = pinfo->sht;
892 probe_ent->host_flags = pinfo->host_flags;
893 probe_ent->pio_mask = pinfo->pio_mask;
894 probe_ent->udma_mask = pinfo->udma_mask;
895 probe_ent->port_ops = pinfo->port_ops;
896 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
897
898 probe_ent->irq = pdev->irq;
899 probe_ent->irq_flags = SA_SHIRQ;
900 probe_ent->mmio_base = port_base;
901 probe_ent->private_data = hpriv;
902
903 memset(hpriv, 0, sizeof(*hpriv));
904 hpriv->host_base = host_base;
905 hpriv->port_base = port_base;
906
907 /*
908 * Configure the device
909 */
910 /*
911 * FIXME: This device is certainly 64-bit capable. We just
912 * don't know how to use it. After fixing 32bit activation in
913 * this function, enable 64bit masks here.
914 */
915 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
916 if (rc) {
917 dev_printk(KERN_ERR, &pdev->dev,
918 "32-bit DMA enable failed\n");
919 goto out_free;
920 }
921 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
922 if (rc) {
923 dev_printk(KERN_ERR, &pdev->dev,
924 "32-bit consistent DMA enable failed\n");
925 goto out_free;
926 }
927
928 /* GPIO off */
929 writel(0, host_base + HOST_FLASH_CMD);
930
931 /* Mask interrupts during initialization */
932 writel(0, host_base + HOST_CTRL);
933
934 for (i = 0; i < probe_ent->n_ports; i++) {
935 void __iomem *port = port_base + i * PORT_REGS_SIZE;
936 unsigned long portu = (unsigned long)port;
937 u32 tmp;
938 int cnt;
939
940 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
941 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
942
943 ata_std_ports(&probe_ent->port[i]);
944
945 /* Initial PHY setting */
946 writel(0x20c, port + PORT_PHY_CFG);
947
948 /* Clear port RST */
949 tmp = readl(port + PORT_CTRL_STAT);
950 if (tmp & PORT_CS_PORT_RST) {
951 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
952 readl(port + PORT_CTRL_STAT); /* sync */
953 for (cnt = 0; cnt < 10; cnt++) {
954 msleep(10);
955 tmp = readl(port + PORT_CTRL_STAT);
956 if (!(tmp & PORT_CS_PORT_RST))
957 break;
958 }
959 if (tmp & PORT_CS_PORT_RST)
960 dev_printk(KERN_ERR, &pdev->dev,
961 "failed to clear port RST\n");
962 }
963
964 /* Zero error counters. */
965 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
966 writel(0x8000, port + PORT_CRC_ERR_THRESH);
967 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
968 writel(0x0000, port + PORT_DECODE_ERR_CNT);
969 writel(0x0000, port + PORT_CRC_ERR_CNT);
970 writel(0x0000, port + PORT_HSHK_ERR_CNT);
971
972 /* FIXME: 32bit activation? */
973 writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
974 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
975
976 /* Configure interrupts */
977 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
978 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS,
979 port + PORT_IRQ_ENABLE_SET);
980
981 /* Clear interrupts */
982 writel(0x0fff0fff, port + PORT_IRQ_STAT);
983 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
984
985 /* Clear port multiplier enable and resume bits */
986 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
987
988 /* Reset itself */
989 if (__sil24_reset_controller(port))
990 dev_printk(KERN_ERR, &pdev->dev,
991 "failed to reset controller\n");
992 }
993
994 /* Turn on interrupts */
995 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
996
997 pci_set_master(pdev);
998
999 /* FIXME: check ata_device_add return value */
1000 ata_device_add(probe_ent);
1001
1002 kfree(probe_ent);
1003 return 0;
1004
1005 out_free:
1006 if (host_base)
1007 iounmap(host_base);
1008 if (port_base)
1009 iounmap(port_base);
1010 kfree(probe_ent);
1011 kfree(hpriv);
1012 pci_release_regions(pdev);
1013 out_disable:
1014 pci_disable_device(pdev);
1015 return rc;
1016 }
1017
1018 static int __init sil24_init(void)
1019 {
1020 return pci_module_init(&sil24_pci_driver);
1021 }
1022
1023 static void __exit sil24_exit(void)
1024 {
1025 pci_unregister_driver(&sil24_pci_driver);
1026 }
1027
1028 MODULE_AUTHOR("Tejun Heo");
1029 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1030 MODULE_LICENSE("GPL");
1031 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1032
1033 module_init(sil24_init);
1034 module_exit(sil24_exit);
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