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[SCSI] sym2: Use DMA_40BIT_MASK constant
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / scsi / sata_promise.c
blob8a8e3e3ef0ed3bbaebe61e9713cfaab005f47820
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include <asm/io.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.03"
50
51
52 enum {
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_TBG_MODE = 0x41, /* TBG mode */
56 PDC_FLASH_CTL = 0x44, /* Flash control register */
57 PDC_PCI_CTL = 0x48, /* PCI control and status register */
58 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
59 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
61 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
62
63 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
64 (1<<8) | (1<<9) | (1<<10),
65
66 board_2037x = 0, /* FastTrak S150 TX2plus */
67 board_20319 = 1, /* FastTrak S150 TX4 */
68 board_20619 = 2, /* FastTrak TX4000 */
69
70 PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */
71
72 PDC_RESET = (1 << 11), /* HDMA reset */
73 };
74
75
76 struct pdc_port_priv {
77 u8 *pkt;
78 dma_addr_t pkt_dma;
79 };
80
81 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
82 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
83 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
84 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
85 static void pdc_eng_timeout(struct ata_port *ap);
86 static int pdc_port_start(struct ata_port *ap);
87 static void pdc_port_stop(struct ata_port *ap);
88 static void pdc_pata_phy_reset(struct ata_port *ap);
89 static void pdc_sata_phy_reset(struct ata_port *ap);
90 static void pdc_qc_prep(struct ata_queued_cmd *qc);
91 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
92 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
93 static void pdc_irq_clear(struct ata_port *ap);
94 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
95
96
97 static struct scsi_host_template pdc_ata_sht = {
98 .module = THIS_MODULE,
99 .name = DRV_NAME,
100 .ioctl = ata_scsi_ioctl,
101 .queuecommand = ata_scsi_queuecmd,
102 .eh_strategy_handler = ata_scsi_error,
103 .can_queue = ATA_DEF_QUEUE,
104 .this_id = ATA_SHT_THIS_ID,
105 .sg_tablesize = LIBATA_MAX_PRD,
106 .max_sectors = ATA_MAX_SECTORS,
107 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
108 .emulated = ATA_SHT_EMULATED,
109 .use_clustering = ATA_SHT_USE_CLUSTERING,
110 .proc_name = DRV_NAME,
111 .dma_boundary = ATA_DMA_BOUNDARY,
112 .slave_configure = ata_scsi_slave_config,
113 .bios_param = ata_std_bios_param,
114 .ordered_flush = 1,
115 };
116
117 static const struct ata_port_operations pdc_sata_ops = {
118 .port_disable = ata_port_disable,
119 .tf_load = pdc_tf_load_mmio,
120 .tf_read = ata_tf_read,
121 .check_status = ata_check_status,
122 .exec_command = pdc_exec_command_mmio,
123 .dev_select = ata_std_dev_select,
124
125 .phy_reset = pdc_sata_phy_reset,
126
127 .qc_prep = pdc_qc_prep,
128 .qc_issue = pdc_qc_issue_prot,
129 .eng_timeout = pdc_eng_timeout,
130 .irq_handler = pdc_interrupt,
131 .irq_clear = pdc_irq_clear,
132
133 .scr_read = pdc_sata_scr_read,
134 .scr_write = pdc_sata_scr_write,
135 .port_start = pdc_port_start,
136 .port_stop = pdc_port_stop,
137 .host_stop = ata_pci_host_stop,
138 };
139
140 static const struct ata_port_operations pdc_pata_ops = {
141 .port_disable = ata_port_disable,
142 .tf_load = pdc_tf_load_mmio,
143 .tf_read = ata_tf_read,
144 .check_status = ata_check_status,
145 .exec_command = pdc_exec_command_mmio,
146 .dev_select = ata_std_dev_select,
147
148 .phy_reset = pdc_pata_phy_reset,
149
150 .qc_prep = pdc_qc_prep,
151 .qc_issue = pdc_qc_issue_prot,
152 .eng_timeout = pdc_eng_timeout,
153 .irq_handler = pdc_interrupt,
154 .irq_clear = pdc_irq_clear,
155
156 .port_start = pdc_port_start,
157 .port_stop = pdc_port_stop,
158 .host_stop = ata_pci_host_stop,
159 };
160
161 static struct ata_port_info pdc_port_info[] = {
162 /* board_2037x */
163 {
164 .sht = &pdc_ata_sht,
165 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
166 ATA_FLAG_SRST | ATA_FLAG_MMIO,
167 .pio_mask = 0x1f, /* pio0-4 */
168 .mwdma_mask = 0x07, /* mwdma0-2 */
169 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
170 .port_ops = &pdc_sata_ops,
171 },
172
173 /* board_20319 */
174 {
175 .sht = &pdc_ata_sht,
176 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
177 ATA_FLAG_SRST | ATA_FLAG_MMIO,
178 .pio_mask = 0x1f, /* pio0-4 */
179 .mwdma_mask = 0x07, /* mwdma0-2 */
180 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
181 .port_ops = &pdc_sata_ops,
182 },
183
184 /* board_20619 */
185 {
186 .sht = &pdc_ata_sht,
187 .host_flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
188 ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS,
189 .pio_mask = 0x1f, /* pio0-4 */
190 .mwdma_mask = 0x07, /* mwdma0-2 */
191 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
192 .port_ops = &pdc_pata_ops,
193 },
194 };
195
196 static const struct pci_device_id pdc_ata_pci_tbl[] = {
197 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
198 board_2037x },
199 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
200 board_2037x },
201 { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
202 board_2037x },
203 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
204 board_2037x },
205 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
206 board_2037x },
207 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
208 board_2037x },
209 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
210 board_2037x },
211 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
212 board_2037x },
213 { PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
214 board_2037x },
215
216 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
217 board_20319 },
218 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
219 board_20319 },
220 { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
221 board_20319 },
222 { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
223 board_20319 },
224 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
225 board_20319 },
226
227 { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
228 board_20619 },
229
230 { } /* terminate list */
231 };
232
233
234 static struct pci_driver pdc_ata_pci_driver = {
235 .name = DRV_NAME,
236 .id_table = pdc_ata_pci_tbl,
237 .probe = pdc_ata_init_one,
238 .remove = ata_pci_remove_one,
239 };
240
241
242 static int pdc_port_start(struct ata_port *ap)
243 {
244 struct device *dev = ap->host_set->dev;
245 struct pdc_port_priv *pp;
246 int rc;
247
248 rc = ata_port_start(ap);
249 if (rc)
250 return rc;
251
252 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
253 if (!pp) {
254 rc = -ENOMEM;
255 goto err_out;
256 }
257 memset(pp, 0, sizeof(*pp));
258
259 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
260 if (!pp->pkt) {
261 rc = -ENOMEM;
262 goto err_out_kfree;
263 }
264
265 ap->private_data = pp;
266
267 return 0;
268
269 err_out_kfree:
270 kfree(pp);
271 err_out:
272 ata_port_stop(ap);
273 return rc;
274 }
275
276
277 static void pdc_port_stop(struct ata_port *ap)
278 {
279 struct device *dev = ap->host_set->dev;
280 struct pdc_port_priv *pp = ap->private_data;
281
282 ap->private_data = NULL;
283 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
284 kfree(pp);
285 ata_port_stop(ap);
286 }
287
288
289 static void pdc_reset_port(struct ata_port *ap)
290 {
291 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
292 unsigned int i;
293 u32 tmp;
294
295 for (i = 11; i > 0; i--) {
296 tmp = readl(mmio);
297 if (tmp & PDC_RESET)
298 break;
299
300 udelay(100);
301
302 tmp |= PDC_RESET;
303 writel(tmp, mmio);
304 }
305
306 tmp &= ~PDC_RESET;
307 writel(tmp, mmio);
308 readl(mmio); /* flush */
309 }
310
311 static void pdc_sata_phy_reset(struct ata_port *ap)
312 {
313 pdc_reset_port(ap);
314 sata_phy_reset(ap);
315 }
316
317 static void pdc_pata_phy_reset(struct ata_port *ap)
318 {
319 /* FIXME: add cable detect. Don't assume 40-pin cable */
320 ap->cbl = ATA_CBL_PATA40;
321 ap->udma_mask &= ATA_UDMA_MASK_40C;
322
323 pdc_reset_port(ap);
324 ata_port_probe(ap);
325 ata_bus_reset(ap);
326 }
327
328 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
329 {
330 if (sc_reg > SCR_CONTROL)
331 return 0xffffffffU;
332 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
333 }
334
335
336 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
337 u32 val)
338 {
339 if (sc_reg > SCR_CONTROL)
340 return;
341 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
342 }
343
344 static void pdc_qc_prep(struct ata_queued_cmd *qc)
345 {
346 struct pdc_port_priv *pp = qc->ap->private_data;
347 unsigned int i;
348
349 VPRINTK("ENTER\n");
350
351 switch (qc->tf.protocol) {
352 case ATA_PROT_DMA:
353 ata_qc_prep(qc);
354 /* fall through */
355
356 case ATA_PROT_NODATA:
357 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
358 qc->dev->devno, pp->pkt);
359
360 if (qc->tf.flags & ATA_TFLAG_LBA48)
361 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
362 else
363 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
364
365 pdc_pkt_footer(&qc->tf, pp->pkt, i);
366 break;
367
368 default:
369 break;
370 }
371 }
372
373 static void pdc_eng_timeout(struct ata_port *ap)
374 {
375 struct ata_host_set *host_set = ap->host_set;
376 u8 drv_stat;
377 struct ata_queued_cmd *qc;
378 unsigned long flags;
379
380 DPRINTK("ENTER\n");
381
382 spin_lock_irqsave(&host_set->lock, flags);
383
384 qc = ata_qc_from_tag(ap, ap->active_tag);
385 if (!qc) {
386 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
387 ap->id);
388 goto out;
389 }
390
391 /* hack alert! We cannot use the supplied completion
392 * function from inside the ->eh_strategy_handler() thread.
393 * libata is the only user of ->eh_strategy_handler() in
394 * any kernel, so the default scsi_done() assumes it is
395 * not being called from the SCSI EH.
396 */
397 qc->scsidone = scsi_finish_command;
398
399 switch (qc->tf.protocol) {
400 case ATA_PROT_DMA:
401 case ATA_PROT_NODATA:
402 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
403 drv_stat = ata_wait_idle(ap);
404 ata_qc_complete(qc, __ac_err_mask(drv_stat));
405 break;
406
407 default:
408 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
409
410 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
411 ap->id, qc->tf.command, drv_stat);
412
413 ata_qc_complete(qc, ac_err_mask(drv_stat));
414 break;
415 }
416
417 out:
418 spin_unlock_irqrestore(&host_set->lock, flags);
419 DPRINTK("EXIT\n");
420 }
421
422 static inline unsigned int pdc_host_intr( struct ata_port *ap,
423 struct ata_queued_cmd *qc)
424 {
425 unsigned int handled = 0, err_mask = 0;
426 u32 tmp;
427 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
428
429 tmp = readl(mmio);
430 if (tmp & PDC_ERR_MASK) {
431 err_mask = AC_ERR_DEV;
432 pdc_reset_port(ap);
433 }
434
435 switch (qc->tf.protocol) {
436 case ATA_PROT_DMA:
437 case ATA_PROT_NODATA:
438 err_mask |= ac_err_mask(ata_wait_idle(ap));
439 ata_qc_complete(qc, err_mask);
440 handled = 1;
441 break;
442
443 default:
444 ap->stats.idle_irq++;
445 break;
446 }
447
448 return handled;
449 }
450
451 static void pdc_irq_clear(struct ata_port *ap)
452 {
453 struct ata_host_set *host_set = ap->host_set;
454 void __iomem *mmio = host_set->mmio_base;
455
456 readl(mmio + PDC_INT_SEQMASK);
457 }
458
459 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
460 {
461 struct ata_host_set *host_set = dev_instance;
462 struct ata_port *ap;
463 u32 mask = 0;
464 unsigned int i, tmp;
465 unsigned int handled = 0;
466 void __iomem *mmio_base;
467
468 VPRINTK("ENTER\n");
469
470 if (!host_set || !host_set->mmio_base) {
471 VPRINTK("QUICK EXIT\n");
472 return IRQ_NONE;
473 }
474
475 mmio_base = host_set->mmio_base;
476
477 /* reading should also clear interrupts */
478 mask = readl(mmio_base + PDC_INT_SEQMASK);
479
480 if (mask == 0xffffffff) {
481 VPRINTK("QUICK EXIT 2\n");
482 return IRQ_NONE;
483 }
484 mask &= 0xffff; /* only 16 tags possible */
485 if (!mask) {
486 VPRINTK("QUICK EXIT 3\n");
487 return IRQ_NONE;
488 }
489
490 spin_lock(&host_set->lock);
491
492 writel(mask, mmio_base + PDC_INT_SEQMASK);
493
494 for (i = 0; i < host_set->n_ports; i++) {
495 VPRINTK("port %u\n", i);
496 ap = host_set->ports[i];
497 tmp = mask & (1 << (i + 1));
498 if (tmp && ap &&
499 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
500 struct ata_queued_cmd *qc;
501
502 qc = ata_qc_from_tag(ap, ap->active_tag);
503 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
504 handled += pdc_host_intr(ap, qc);
505 }
506 }
507
508 spin_unlock(&host_set->lock);
509
510 VPRINTK("EXIT\n");
511
512 return IRQ_RETVAL(handled);
513 }
514
515 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
516 {
517 struct ata_port *ap = qc->ap;
518 struct pdc_port_priv *pp = ap->private_data;
519 unsigned int port_no = ap->port_no;
520 u8 seq = (u8) (port_no + 1);
521
522 VPRINTK("ENTER, ap %p\n", ap);
523
524 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
525 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
526
527 pp->pkt[2] = seq;
528 wmb(); /* flush PRD, pkt writes */
529 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
530 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
531 }
532
533 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
534 {
535 switch (qc->tf.protocol) {
536 case ATA_PROT_DMA:
537 case ATA_PROT_NODATA:
538 pdc_packet_start(qc);
539 return 0;
540
541 case ATA_PROT_ATAPI_DMA:
542 BUG();
543 break;
544
545 default:
546 break;
547 }
548
549 return ata_qc_issue_prot(qc);
550 }
551
552 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
553 {
554 WARN_ON (tf->protocol == ATA_PROT_DMA ||
555 tf->protocol == ATA_PROT_NODATA);
556 ata_tf_load(ap, tf);
557 }
558
559
560 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
561 {
562 WARN_ON (tf->protocol == ATA_PROT_DMA ||
563 tf->protocol == ATA_PROT_NODATA);
564 ata_exec_command(ap, tf);
565 }
566
567
568 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
569 {
570 port->cmd_addr = base;
571 port->data_addr = base;
572 port->feature_addr =
573 port->error_addr = base + 0x4;
574 port->nsect_addr = base + 0x8;
575 port->lbal_addr = base + 0xc;
576 port->lbam_addr = base + 0x10;
577 port->lbah_addr = base + 0x14;
578 port->device_addr = base + 0x18;
579 port->command_addr =
580 port->status_addr = base + 0x1c;
581 port->altstatus_addr =
582 port->ctl_addr = base + 0x38;
583 }
584
585
586 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
587 {
588 void __iomem *mmio = pe->mmio_base;
589 u32 tmp;
590
591 /*
592 * Except for the hotplug stuff, this is voodoo from the
593 * Promise driver. Label this entire section
594 * "TODO: figure out why we do this"
595 */
596
597 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
598 tmp = readl(mmio + PDC_FLASH_CTL);
599 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
600 writel(tmp, mmio + PDC_FLASH_CTL);
601
602 /* clear plug/unplug flags for all ports */
603 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
604 writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR);
605
606 /* mask plug/unplug ints */
607 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
608 writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR);
609
610 /* reduce TBG clock to 133 Mhz. */
611 tmp = readl(mmio + PDC_TBG_MODE);
612 tmp &= ~0x30000; /* clear bit 17, 16*/
613 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
614 writel(tmp, mmio + PDC_TBG_MODE);
615
616 readl(mmio + PDC_TBG_MODE); /* flush */
617 msleep(10);
618
619 /* adjust slew rate control register. */
620 tmp = readl(mmio + PDC_SLEW_CTL);
621 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
622 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
623 writel(tmp, mmio + PDC_SLEW_CTL);
624 }
625
626 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
627 {
628 static int printed_version;
629 struct ata_probe_ent *probe_ent = NULL;
630 unsigned long base;
631 void __iomem *mmio_base;
632 unsigned int board_idx = (unsigned int) ent->driver_data;
633 int pci_dev_busy = 0;
634 int rc;
635
636 if (!printed_version++)
637 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
638
639 /*
640 * If this driver happens to only be useful on Apple's K2, then
641 * we should check that here as it has a normal Serverworks ID
642 */
643 rc = pci_enable_device(pdev);
644 if (rc)
645 return rc;
646
647 rc = pci_request_regions(pdev, DRV_NAME);
648 if (rc) {
649 pci_dev_busy = 1;
650 goto err_out;
651 }
652
653 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
654 if (rc)
655 goto err_out_regions;
656 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
657 if (rc)
658 goto err_out_regions;
659
660 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
661 if (probe_ent == NULL) {
662 rc = -ENOMEM;
663 goto err_out_regions;
664 }
665
666 memset(probe_ent, 0, sizeof(*probe_ent));
667 probe_ent->dev = pci_dev_to_dev(pdev);
668 INIT_LIST_HEAD(&probe_ent->node);
669
670 mmio_base = pci_iomap(pdev, 3, 0);
671 if (mmio_base == NULL) {
672 rc = -ENOMEM;
673 goto err_out_free_ent;
674 }
675 base = (unsigned long) mmio_base;
676
677 probe_ent->sht = pdc_port_info[board_idx].sht;
678 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
679 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
680 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
681 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
682 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
683
684 probe_ent->irq = pdev->irq;
685 probe_ent->irq_flags = SA_SHIRQ;
686 probe_ent->mmio_base = mmio_base;
687
688 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
689 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
690
691 probe_ent->port[0].scr_addr = base + 0x400;
692 probe_ent->port[1].scr_addr = base + 0x500;
693
694 /* notice 4-port boards */
695 switch (board_idx) {
696 case board_20319:
697 probe_ent->n_ports = 4;
698
699 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
700 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
701
702 probe_ent->port[2].scr_addr = base + 0x600;
703 probe_ent->port[3].scr_addr = base + 0x700;
704 break;
705 case board_2037x:
706 probe_ent->n_ports = 2;
707 break;
708 case board_20619:
709 probe_ent->n_ports = 4;
710
711 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
712 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
713
714 probe_ent->port[2].scr_addr = base + 0x600;
715 probe_ent->port[3].scr_addr = base + 0x700;
716 break;
717 default:
718 BUG();
719 break;
720 }
721
722 pci_set_master(pdev);
723
724 /* initialize adapter */
725 pdc_host_init(board_idx, probe_ent);
726
727 /* FIXME: check ata_device_add return value */
728 ata_device_add(probe_ent);
729 kfree(probe_ent);
730
731 return 0;
732
733 err_out_free_ent:
734 kfree(probe_ent);
735 err_out_regions:
736 pci_release_regions(pdev);
737 err_out:
738 if (!pci_dev_busy)
739 pci_disable_device(pdev);
740 return rc;
741 }
742
743
744 static int __init pdc_ata_init(void)
745 {
746 return pci_module_init(&pdc_ata_pci_driver);
747 }
748
749
750 static void __exit pdc_ata_exit(void)
751 {
752 pci_unregister_driver(&pdc_ata_pci_driver);
753 }
754
755
756 MODULE_AUTHOR("Jeff Garzik");
757 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
758 MODULE_LICENSE("GPL");
759 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
760 MODULE_VERSION(DRV_VERSION);
761
762 module_init(pdc_ata_init);
763 module_exit(pdc_ata_exit);
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