2 * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
19 #include <linux/irq.h>
21 #include <asm/sections.h>
24 #include <asm/pci-bridge.h>
25 #include <asm/machdep.h>
26 #include <asm/iommu.h>
27 #include <asm/ppc-pci.h>
32 #define DBG(x...) printk(x)
37 static struct pci_controller
*u3_agp
, *u3_ht
, *u4_pcie
;
39 static int __init
fixup_one_level_bus_range(struct device_node
*node
, int higher
)
41 for (; node
!= 0;node
= node
->sibling
) {
43 const unsigned int *class_code
;
46 /* For PCI<->PCI bridges or CardBus bridges, we go down */
47 class_code
= get_property(node
, "class-code", NULL
);
48 if (!class_code
|| ((*class_code
>> 8) != PCI_CLASS_BRIDGE_PCI
&&
49 (*class_code
>> 8) != PCI_CLASS_BRIDGE_CARDBUS
))
51 bus_range
= get_property(node
, "bus-range", &len
);
52 if (bus_range
!= NULL
&& len
> 2 * sizeof(int)) {
53 if (bus_range
[1] > higher
)
54 higher
= bus_range
[1];
56 higher
= fixup_one_level_bus_range(node
->child
, higher
);
61 /* This routine fixes the "bus-range" property of all bridges in the
62 * system since they tend to have their "last" member wrong on macs
64 * Note that the bus numbers manipulated here are OF bus numbers, they
65 * are not Linux bus numbers.
67 static void __init
fixup_bus_range(struct device_node
*bridge
)
70 struct property
*prop
;
73 /* Lookup the "bus-range" property for the hose */
74 prop
= of_find_property(bridge
, "bus-range", &len
);
75 if (prop
== NULL
|| prop
->value
== NULL
|| len
< 2 * sizeof(int)) {
76 printk(KERN_WARNING
"Can't get bus-range for %s\n",
80 bus_range
= (int *)prop
->value
;
81 bus_range
[1] = fixup_one_level_bus_range(bridge
->child
, bus_range
[1]);
85 static unsigned long u3_agp_cfa0(u8 devfn
, u8 off
)
87 return (1 << (unsigned long)PCI_SLOT(devfn
)) |
88 ((unsigned long)PCI_FUNC(devfn
) << 8) |
89 ((unsigned long)off
& 0xFCUL
);
92 static unsigned long u3_agp_cfa1(u8 bus
, u8 devfn
, u8 off
)
94 return ((unsigned long)bus
<< 16) |
95 ((unsigned long)devfn
<< 8) |
96 ((unsigned long)off
& 0xFCUL
) |
100 static volatile void __iomem
*u3_agp_cfg_access(struct pci_controller
* hose
,
101 u8 bus
, u8 dev_fn
, u8 offset
)
105 if (bus
== hose
->first_busno
) {
106 if (dev_fn
< (11 << 3))
108 caddr
= u3_agp_cfa0(dev_fn
, offset
);
110 caddr
= u3_agp_cfa1(bus
, dev_fn
, offset
);
112 /* Uninorth will return garbage if we don't read back the value ! */
114 out_le32(hose
->cfg_addr
, caddr
);
115 } while (in_le32(hose
->cfg_addr
) != caddr
);
118 return hose
->cfg_data
+ offset
;
121 static int u3_agp_read_config(struct pci_bus
*bus
, unsigned int devfn
,
122 int offset
, int len
, u32
*val
)
124 struct pci_controller
*hose
;
125 volatile void __iomem
*addr
;
127 hose
= pci_bus_to_host(bus
);
129 return PCIBIOS_DEVICE_NOT_FOUND
;
131 addr
= u3_agp_cfg_access(hose
, bus
->number
, devfn
, offset
);
133 return PCIBIOS_DEVICE_NOT_FOUND
;
135 * Note: the caller has already checked that offset is
136 * suitably aligned and that len is 1, 2 or 4.
143 *val
= in_le16(addr
);
146 *val
= in_le32(addr
);
149 return PCIBIOS_SUCCESSFUL
;
152 static int u3_agp_write_config(struct pci_bus
*bus
, unsigned int devfn
,
153 int offset
, int len
, u32 val
)
155 struct pci_controller
*hose
;
156 volatile void __iomem
*addr
;
158 hose
= pci_bus_to_host(bus
);
160 return PCIBIOS_DEVICE_NOT_FOUND
;
162 addr
= u3_agp_cfg_access(hose
, bus
->number
, devfn
, offset
);
164 return PCIBIOS_DEVICE_NOT_FOUND
;
166 * Note: the caller has already checked that offset is
167 * suitably aligned and that len is 1, 2 or 4.
176 (void) in_le16(addr
);
180 (void) in_le32(addr
);
183 return PCIBIOS_SUCCESSFUL
;
186 static struct pci_ops u3_agp_pci_ops
=
192 static unsigned long u3_ht_cfa0(u8 devfn
, u8 off
)
194 return (devfn
<< 8) | off
;
197 static unsigned long u3_ht_cfa1(u8 bus
, u8 devfn
, u8 off
)
199 return u3_ht_cfa0(devfn
, off
) + (bus
<< 16) + 0x01000000UL
;
202 static volatile void __iomem
*u3_ht_cfg_access(struct pci_controller
* hose
,
203 u8 bus
, u8 devfn
, u8 offset
)
205 if (bus
== hose
->first_busno
) {
206 if (PCI_SLOT(devfn
) == 0)
208 return hose
->cfg_data
+ u3_ht_cfa0(devfn
, offset
);
210 return hose
->cfg_data
+ u3_ht_cfa1(bus
, devfn
, offset
);
213 static int u3_ht_read_config(struct pci_bus
*bus
, unsigned int devfn
,
214 int offset
, int len
, u32
*val
)
216 struct pci_controller
*hose
;
217 volatile void __iomem
*addr
;
219 hose
= pci_bus_to_host(bus
);
221 return PCIBIOS_DEVICE_NOT_FOUND
;
224 return PCIBIOS_BAD_REGISTER_NUMBER
;
226 addr
= u3_ht_cfg_access(hose
, bus
->number
, devfn
, offset
);
228 return PCIBIOS_DEVICE_NOT_FOUND
;
231 * Note: the caller has already checked that offset is
232 * suitably aligned and that len is 1, 2 or 4.
239 *val
= in_le16(addr
);
242 *val
= in_le32(addr
);
245 return PCIBIOS_SUCCESSFUL
;
248 static int u3_ht_write_config(struct pci_bus
*bus
, unsigned int devfn
,
249 int offset
, int len
, u32 val
)
251 struct pci_controller
*hose
;
252 volatile void __iomem
*addr
;
254 hose
= pci_bus_to_host(bus
);
256 return PCIBIOS_DEVICE_NOT_FOUND
;
259 return PCIBIOS_BAD_REGISTER_NUMBER
;
261 addr
= u3_ht_cfg_access(hose
, bus
->number
, devfn
, offset
);
263 return PCIBIOS_DEVICE_NOT_FOUND
;
265 * Note: the caller has already checked that offset is
266 * suitably aligned and that len is 1, 2 or 4.
275 (void) in_le16(addr
);
279 (void) in_le32(addr
);
282 return PCIBIOS_SUCCESSFUL
;
285 static struct pci_ops u3_ht_pci_ops
=
291 static unsigned int u4_pcie_cfa0(unsigned int devfn
, unsigned int off
)
293 return (1 << PCI_SLOT(devfn
)) |
294 (PCI_FUNC(devfn
) << 8) |
299 static unsigned int u4_pcie_cfa1(unsigned int bus
, unsigned int devfn
,
308 static volatile void __iomem
*u4_pcie_cfg_access(struct pci_controller
* hose
,
309 u8 bus
, u8 dev_fn
, int offset
)
313 if (bus
== hose
->first_busno
)
314 caddr
= u4_pcie_cfa0(dev_fn
, offset
);
316 caddr
= u4_pcie_cfa1(bus
, dev_fn
, offset
);
318 /* Uninorth will return garbage if we don't read back the value ! */
320 out_le32(hose
->cfg_addr
, caddr
);
321 } while (in_le32(hose
->cfg_addr
) != caddr
);
324 return hose
->cfg_data
+ offset
;
327 static int u4_pcie_read_config(struct pci_bus
*bus
, unsigned int devfn
,
328 int offset
, int len
, u32
*val
)
330 struct pci_controller
*hose
;
331 volatile void __iomem
*addr
;
333 hose
= pci_bus_to_host(bus
);
335 return PCIBIOS_DEVICE_NOT_FOUND
;
336 if (offset
>= 0x1000)
337 return PCIBIOS_BAD_REGISTER_NUMBER
;
338 addr
= u4_pcie_cfg_access(hose
, bus
->number
, devfn
, offset
);
340 return PCIBIOS_DEVICE_NOT_FOUND
;
342 * Note: the caller has already checked that offset is
343 * suitably aligned and that len is 1, 2 or 4.
350 *val
= in_le16(addr
);
353 *val
= in_le32(addr
);
356 return PCIBIOS_SUCCESSFUL
;
358 static int u4_pcie_write_config(struct pci_bus
*bus
, unsigned int devfn
,
359 int offset
, int len
, u32 val
)
361 struct pci_controller
*hose
;
362 volatile void __iomem
*addr
;
364 hose
= pci_bus_to_host(bus
);
366 return PCIBIOS_DEVICE_NOT_FOUND
;
367 if (offset
>= 0x1000)
368 return PCIBIOS_BAD_REGISTER_NUMBER
;
369 addr
= u4_pcie_cfg_access(hose
, bus
->number
, devfn
, offset
);
371 return PCIBIOS_DEVICE_NOT_FOUND
;
373 * Note: the caller has already checked that offset is
374 * suitably aligned and that len is 1, 2 or 4.
383 (void) in_le16(addr
);
387 (void) in_le32(addr
);
390 return PCIBIOS_SUCCESSFUL
;
393 static struct pci_ops u4_pcie_pci_ops
=
399 static void __init
setup_u3_agp(struct pci_controller
* hose
)
401 /* On G5, we move AGP up to high bus number so we don't need
402 * to reassign bus numbers for HT. If we ever have P2P bridges
403 * on AGP, we'll have to move pci_assign_all_buses to the
404 * pci_controller structure so we enable it for AGP and not for
406 * We hard code the address because of the different size of
407 * the reg address cell, we shall fix that by killing struct
408 * reg_property and using some accessor functions instead
410 hose
->first_busno
= 0xf0;
411 hose
->last_busno
= 0xff;
412 hose
->ops
= &u3_agp_pci_ops
;
413 hose
->cfg_addr
= ioremap(0xf0000000 + 0x800000, 0x1000);
414 hose
->cfg_data
= ioremap(0xf0000000 + 0xc00000, 0x1000);
419 static void __init
setup_u4_pcie(struct pci_controller
* hose
)
421 /* We currently only implement the "non-atomic" config space, to
422 * be optimised later.
424 hose
->ops
= &u4_pcie_pci_ops
;
425 hose
->cfg_addr
= ioremap(0xf0000000 + 0x800000, 0x1000);
426 hose
->cfg_data
= ioremap(0xf0000000 + 0xc00000, 0x1000);
428 /* The bus contains a bridge from root -> device, we need to
429 * make it visible on bus 0 so that we pick the right type
430 * of config cycles. If we didn't, we would have to force all
431 * config cycles to be type 1. So we override the "bus-range"
434 hose
->first_busno
= 0x00;
435 hose
->last_busno
= 0xff;
439 static void __init
setup_u3_ht(struct pci_controller
* hose
)
441 hose
->ops
= &u3_ht_pci_ops
;
443 /* We hard code the address because of the different size of
444 * the reg address cell, we shall fix that by killing struct
445 * reg_property and using some accessor functions instead
447 hose
->cfg_data
= ioremap(0xf2000000, 0x02000000);
449 hose
->first_busno
= 0;
450 hose
->last_busno
= 0xef;
455 static int __init
add_bridge(struct device_node
*dev
)
458 struct pci_controller
*hose
;
460 const int *bus_range
;
463 DBG("Adding PCI host bridge %s\n", dev
->full_name
);
465 bus_range
= get_property(dev
, "bus-range", &len
);
466 if (bus_range
== NULL
|| len
< 2 * sizeof(int)) {
467 printk(KERN_WARNING
"Can't get bus-range for %s, assume bus 0\n",
471 hose
= pcibios_alloc_controller(dev
);
474 hose
->first_busno
= bus_range
? bus_range
[0] : 0;
475 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
478 if (device_is_compatible(dev
, "u3-agp")) {
480 disp_name
= "U3-AGP";
482 } else if (device_is_compatible(dev
, "u3-ht")) {
486 } else if (device_is_compatible(dev
, "u4-pcie")) {
488 disp_name
= "U4-PCIE";
491 printk(KERN_INFO
"Found %s PCI host bridge. Firmware bus number: %d->%d\n",
492 disp_name
, hose
->first_busno
, hose
->last_busno
);
494 /* Interpret the "ranges" property */
495 /* This also maps the I/O region and sets isa_io/mem_base */
496 pci_process_bridge_OF_ranges(hose
, dev
, primary
);
498 /* Fixup "bus-range" OF property */
499 fixup_bus_range(dev
);
505 void __init
maple_pcibios_fixup(void)
507 struct pci_dev
*dev
= NULL
;
509 DBG(" -> maple_pcibios_fixup\n");
511 for_each_pci_dev(dev
) {
512 /* Fixup IRQ for PCIe host */
513 if (u4_pcie
!= NULL
&& dev
->bus
->number
== 0 &&
514 pci_bus_to_host(dev
->bus
) == u4_pcie
) {
515 printk(KERN_DEBUG
"Fixup U4 PCIe IRQ\n");
516 dev
->irq
= irq_create_mapping(NULL
, 1);
517 if (dev
->irq
!= NO_IRQ
)
518 set_irq_type(dev
->irq
, IRQ_TYPE_LEVEL_LOW
);
522 /* Hide AMD8111 IDE interrupt when in legacy mode so
523 * the driver calls pci_get_legacy_ide_irq()
525 if (dev
->vendor
== PCI_VENDOR_ID_AMD
&&
526 dev
->device
== PCI_DEVICE_ID_AMD_8111_IDE
&&
527 (dev
->class & 5) != 5) {
532 /* For all others, map the interrupt from the device-tree */
533 pci_read_irq_line(dev
);
536 DBG(" <- maple_pcibios_fixup\n");
539 static void __init
maple_fixup_phb_resources(void)
541 struct pci_controller
*hose
, *tmp
;
543 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
544 unsigned long offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
546 hose
->io_resource
.start
+= offset
;
547 hose
->io_resource
.end
+= offset
;
549 printk(KERN_INFO
"PCI Host %d, io start: %llx; io end: %llx\n",
551 (unsigned long long)hose
->io_resource
.start
,
552 (unsigned long long)hose
->io_resource
.end
);
556 void __init
maple_pci_init(void)
558 struct device_node
*np
, *root
;
559 struct device_node
*ht
= NULL
;
561 /* Probe root PCI hosts, that is on U3 the AGP host and the
562 * HyperTransport host. That one is actually "kept" around
563 * and actually added last as it's resource management relies
564 * on the AGP resources to have been setup first
566 root
= of_find_node_by_path("/");
568 printk(KERN_CRIT
"maple_find_bridges: can't find root of device tree\n");
571 for (np
= NULL
; (np
= of_get_next_child(root
, np
)) != NULL
;) {
572 if (np
->name
== NULL
)
574 if (strcmp(np
->name
, "pci") == 0) {
575 if (add_bridge(np
) == 0)
578 if (strcmp(np
->name
, "ht") == 0) {
585 /* Now setup the HyperTransport host if we found any
587 if (ht
&& add_bridge(ht
) != 0)
591 * We need to call pci_setup_phb_io for the HT bridge first
592 * so it gets the I/O port numbers starting at 0, and we
593 * need to call it for the AGP bridge after that so it gets
594 * small positive I/O port numbers.
597 pci_setup_phb_io(u3_ht
, 1);
599 pci_setup_phb_io(u3_agp
, 0);
601 pci_setup_phb_io(u4_pcie
, 0);
603 /* Fixup the IO resources on our host bridges as the common code
604 * does it only for childs of the host bridges
606 maple_fixup_phb_resources();
608 /* Setup the linkage between OF nodes and PHBs */
611 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
612 * assume there is no P2P bridge on the AGP bus, which should be a
613 * safe assumptions hopefully.
616 struct device_node
*np
= u3_agp
->arch_data
;
617 PCI_DN(np
)->busno
= 0xf0;
618 for (np
= np
->child
; np
; np
= np
->sibling
)
619 PCI_DN(np
)->busno
= 0xf0;
622 /* Tell pci.c to not change any resource allocations. */
626 int maple_pci_get_legacy_ide_irq(struct pci_dev
*pdev
, int channel
)
628 struct device_node
*np
;
629 unsigned int defirq
= channel
? 15 : 14;
632 if (pdev
->vendor
!= PCI_VENDOR_ID_AMD
||
633 pdev
->device
!= PCI_DEVICE_ID_AMD_8111_IDE
)
636 np
= pci_device_to_OF_node(pdev
);
638 printk("Failed to locate OF node for IDE %s\n",
642 irq
= irq_of_parse_and_map(np
, channel
& 0x1);
644 printk("Failed to map onboard IDE interrupt for channel %d\n",
651 /* XXX: To remove once all firmwares are ok */
652 static void fixup_maple_ide(struct pci_dev
* dev
)
654 if (!machine_is(maple
))
657 #if 0 /* Enable this to enable IDE port 0 */
661 pci_read_config_byte(dev
, 0x40, &v
);
663 pci_write_config_byte(dev
, 0x40, v
);
666 #if 0 /* fix bus master base */
667 pci_write_config_dword(dev
, 0x20, 0xcc01);
668 printk("old ide resource: %lx -> %lx \n",
669 dev
->resource
[4].start
, dev
->resource
[4].end
);
670 dev
->resource
[4].start
= 0xcc00;
671 dev
->resource
[4].end
= 0xcc10;
673 #if 0 /* Enable this to fixup IDE sense/polarity of irqs in IO-APICs */
675 struct pci_dev
*apicdev
;
678 apicdev
= pci_get_slot (dev
->bus
, PCI_DEVFN(5,0));
680 printk("IDE Fixup IRQ: Can't find IO-APIC !\n");
682 pci_write_config_byte(apicdev
, 0xf2, 0x10 + 2*14);
683 pci_read_config_dword(apicdev
, 0xf4, &v
);
685 pci_write_config_dword(apicdev
, 0xf4, v
);
686 pci_write_config_byte(apicdev
, 0xf2, 0x10 + 2*15);
687 pci_read_config_dword(apicdev
, 0xf4, &v
);
689 pci_write_config_dword(apicdev
, 0xf4, v
);
690 pci_dev_put(apicdev
);
695 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_IDE
,