arch/mips/kernel/traps.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle
   7  * Copyright (C) 1995, 1996 Paul M. Antoine
   8  * Copyright (C) 1998 Ulf Carlsson
   9  * Copyright (C) 1999 Silicon Graphics, Inc.
  10  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  11  * Copyright (C) 2000, 01 MIPS Technologies, Inc.
  12  * Copyright (C) 2002, 2003, 2004, 2005  Maciej W. Rozycki
  13  */
  14 #include <linux/config.h>
  15 #include <linux/init.h>
  16 #include <linux/mm.h>
  17 #include <linux/module.h>
  18 #include <linux/sched.h>
  19 #include <linux/smp.h>
  20 #include <linux/smp_lock.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/kallsyms.h>
  23 #include <linux/bootmem.h>
  24
  25 #include <asm/bootinfo.h>
  26 #include <asm/branch.h>
  27 #include <asm/break.h>
  28 #include <asm/cpu.h>
  29 #include <asm/dsp.h>
  30 #include <asm/fpu.h>
  31 #include <asm/mipsregs.h>
  32 #include <asm/mipsmtregs.h>
  33 #include <asm/module.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/ptrace.h>
  36 #include <asm/sections.h>
  37 #include <asm/system.h>
  38 #include <asm/tlbdebug.h>
  39 #include <asm/traps.h>
  40 #include <asm/uaccess.h>
  41 #include <asm/mmu_context.h>
  42 #include <asm/watch.h>
  43 #include <asm/types.h>
  44
  45 extern asmlinkage void handle_tlbm(void);
  46 extern asmlinkage void handle_tlbl(void);
  47 extern asmlinkage void handle_tlbs(void);
  48 extern asmlinkage void handle_adel(void);
  49 extern asmlinkage void handle_ades(void);
  50 extern asmlinkage void handle_ibe(void);
  51 extern asmlinkage void handle_dbe(void);
  52 extern asmlinkage void handle_sys(void);
  53 extern asmlinkage void handle_bp(void);
  54 extern asmlinkage void handle_ri(void);
  55 extern asmlinkage void handle_cpu(void);
  56 extern asmlinkage void handle_ov(void);
  57 extern asmlinkage void handle_tr(void);
  58 extern asmlinkage void handle_fpe(void);
  59 extern asmlinkage void handle_mdmx(void);
  60 extern asmlinkage void handle_watch(void);
  61 extern asmlinkage void handle_mt(void);
  62 extern asmlinkage void handle_dsp(void);
  63 extern asmlinkage void handle_mcheck(void);
  64 extern asmlinkage void handle_reserved(void);
  65
  66 extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
  67         struct mips_fpu_soft_struct *ctx);
  68
  69 void (*board_be_init)(void);
  70 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
  71 void (*board_nmi_handler_setup)(void);
  72 void (*board_ejtag_handler_setup)(void);
  73 void (*board_bind_eic_interrupt)(int irq, int regset);
  74
  75 /*
  76  * These constant is for searching for possible module text segments.
  77  * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
  78  */
  79 #define MODULE_RANGE (8*1024*1024)
  80
  81 /*
  82  * This routine abuses get_user()/put_user() to reference pointers
  83  * with at least a bit of error checking ...
  84  */
  85 void show_stack(struct task_struct *task, unsigned long *sp)
  86 {
  87         const int field = 2 * sizeof(unsigned long);
  88         long stackdata;
  89         int i;
  90
  91         if (!sp) {
  92                 if (task && task != current)
  93                         sp = (unsigned long *) task->thread.reg29;
  94                 else
  95                         sp = (unsigned long *) &sp;
  96         }
  97
  98         printk("Stack :");
  99         i = 0;
 100         while ((unsigned long) sp & (PAGE_SIZE - 1)) {
 101                 if (i && ((i % (64 / field)) == 0))
 102                         printk("\n       ");
 103                 if (i > 39) {
 104                         printk(" ...");
 105                         break;
 106                 }
 107
 108                 if (__get_user(stackdata, sp++)) {
 109                         printk(" (Bad stack address)");
 110                         break;
 111                 }
 112
 113                 printk(" %0*lx", field, stackdata);
 114                 i++;
 115         }
 116         printk("\n");
 117 }
 118
 119 void show_trace(struct task_struct *task, unsigned long *stack)
 120 {
 121         const int field = 2 * sizeof(unsigned long);
 122         unsigned long addr;
 123
 124         if (!stack) {
 125                 if (task && task != current)
 126                         stack = (unsigned long *) task->thread.reg29;
 127                 else
 128                         stack = (unsigned long *) &stack;
 129         }
 130
 131         printk("Call Trace:");
 132 #ifdef CONFIG_KALLSYMS
 133         printk("\n");
 134 #endif
 135         while (!kstack_end(stack)) {
 136                 addr = *stack++;
 137                 if (__kernel_text_address(addr)) {
 138                         printk(" [<%0*lx>] ", field, addr);
 139                         print_symbol("%s\n", addr);
 140                 }
 141         }
 142         printk("\n");
 143 }
 144
 145 /*
 146  * The architecture-independent dump_stack generator
 147  */
 148 void dump_stack(void)
 149 {
 150         unsigned long stack;
 151
 152         show_trace(current, &stack);
 153 }
 154
 155 EXPORT_SYMBOL(dump_stack);
 156
 157 void show_code(unsigned int *pc)
 158 {
 159         long i;
 160
 161         printk("\nCode:");
 162
 163         for(i = -3 ; i < 6 ; i++) {
 164                 unsigned int insn;
 165                 if (__get_user(insn, pc + i)) {
 166                         printk(" (Bad address in epc)\n");
 167                         break;
 168                 }
 169                 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
 170         }
 171 }
 172
 173 void show_regs(struct pt_regs *regs)
 174 {
 175         const int field = 2 * sizeof(unsigned long);
 176         unsigned int cause = regs->cp0_cause;
 177         int i;
 178
 179         printk("Cpu %d\n", smp_processor_id());
 180
 181         /*
 182          * Saved main processor registers
 183          */
 184         for (i = 0; i < 32; ) {
 185                 if ((i % 4) == 0)
 186                         printk("$%2d   :", i);
 187                 if (i == 0)
 188                         printk(" %0*lx", field, 0UL);
 189                 else if (i == 26 || i == 27)
 190                         printk(" %*s", field, "");
 191                 else
 192                         printk(" %0*lx", field, regs->regs[i]);
 193
 194                 i++;
 195                 if ((i % 4) == 0)
 196                         printk("\n");
 197         }
 198
 199         printk("Hi    : %0*lx\n", field, regs->hi);
 200         printk("Lo    : %0*lx\n", field, regs->lo);
 201
 202         /*
 203          * Saved cp0 registers
 204          */
 205         printk("epc   : %0*lx ", field, regs->cp0_epc);
 206         print_symbol("%s ", regs->cp0_epc);
 207         printk("    %s\n", print_tainted());
 208         printk("ra    : %0*lx ", field, regs->regs[31]);
 209         print_symbol("%s\n", regs->regs[31]);
 210
 211         printk("Status: %08x    ", (uint32_t) regs->cp0_status);
 212
 213         if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
 214                 if (regs->cp0_status & ST0_KUO)
 215                         printk("KUo ");
 216                 if (regs->cp0_status & ST0_IEO)
 217                         printk("IEo ");
 218                 if (regs->cp0_status & ST0_KUP)
 219                         printk("KUp ");
 220                 if (regs->cp0_status & ST0_IEP)
 221                         printk("IEp ");
 222                 if (regs->cp0_status & ST0_KUC)
 223                         printk("KUc ");
 224                 if (regs->cp0_status & ST0_IEC)
 225                         printk("IEc ");
 226         } else {
 227                 if (regs->cp0_status & ST0_KX)
 228                         printk("KX ");
 229                 if (regs->cp0_status & ST0_SX)
 230                         printk("SX ");
 231                 if (regs->cp0_status & ST0_UX)
 232                         printk("UX ");
 233                 switch (regs->cp0_status & ST0_KSU) {
 234                 case KSU_USER:
 235                         printk("USER ");
 236                         break;
 237                 case KSU_SUPERVISOR:
 238                         printk("SUPERVISOR ");
 239                         break;
 240                 case KSU_KERNEL:
 241                         printk("KERNEL ");
 242                         break;
 243                 default:
 244                         printk("BAD_MODE ");
 245                         break;
 246                 }
 247                 if (regs->cp0_status & ST0_ERL)
 248                         printk("ERL ");
 249                 if (regs->cp0_status & ST0_EXL)
 250                         printk("EXL ");
 251                 if (regs->cp0_status & ST0_IE)
 252                         printk("IE ");
 253         }
 254         printk("\n");
 255
 256         printk("Cause : %08x\n", cause);
 257
 258         cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
 259         if (1 <= cause && cause <= 5)
 260                 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
 261
 262         printk("PrId  : %08x\n", read_c0_prid());
 263 }
 264
 265 void show_registers(struct pt_regs *regs)
 266 {
 267         show_regs(regs);
 268         print_modules();
 269         printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
 270                 current->comm, current->pid, current_thread_info(), current);
 271         show_stack(current, (long *) regs->regs[29]);
 272         show_trace(current, (long *) regs->regs[29]);
 273         show_code((unsigned int *) regs->cp0_epc);
 274         printk("\n");
 275 }
 276
 277 static DEFINE_SPINLOCK(die_lock);
 278
 279 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
 280 {
 281         static int die_counter;
 282
 283         console_verbose();
 284         spin_lock_irq(&die_lock);
 285         printk("%s[#%d]:\n", str, ++die_counter);
 286         show_registers(regs);
 287         spin_unlock_irq(&die_lock);
 288         do_exit(SIGSEGV);
 289 }
 290
 291 extern const struct exception_table_entry __start___dbe_table[];
 292 extern const struct exception_table_entry __stop___dbe_table[];
 293
 294 void __declare_dbe_table(void)
 295 {
 296         __asm__ __volatile__(
 297         ".section\t__dbe_table,\"a\"\n\t"
 298         ".previous"
 299         );
 300 }
 301
 302 /* Given an address, look for it in the exception tables. */
 303 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
 304 {
 305         const struct exception_table_entry *e;
 306
 307         e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
 308         if (!e)
 309                 e = search_module_dbetables(addr);
 310         return e;
 311 }
 312
 313 asmlinkage void do_be(struct pt_regs *regs)
 314 {
 315         const int field = 2 * sizeof(unsigned long);
 316         const struct exception_table_entry *fixup = NULL;
 317         int data = regs->cp0_cause & 4;
 318         int action = MIPS_BE_FATAL;
 319
 320         /* XXX For now.  Fixme, this searches the wrong table ...  */
 321         if (data && !user_mode(regs))
 322                 fixup = search_dbe_tables(exception_epc(regs));
 323
 324         if (fixup)
 325                 action = MIPS_BE_FIXUP;
 326
 327         if (board_be_handler)
 328                 action = board_be_handler(regs, fixup != 0);
 329
 330         switch (action) {
 331         case MIPS_BE_DISCARD:
 332                 return;
 333         case MIPS_BE_FIXUP:
 334                 if (fixup) {
 335                         regs->cp0_epc = fixup->nextinsn;
 336                         return;
 337                 }
 338                 break;
 339         default:
 340                 break;
 341         }
 342
 343         /*
 344          * Assume it would be too dangerous to continue ...
 345          */
 346         printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
 347                data ? "Data" : "Instruction",
 348                field, regs->cp0_epc, field, regs->regs[31]);
 349         die_if_kernel("Oops", regs);
 350         force_sig(SIGBUS, current);
 351 }
 352
 353 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
 354 {
 355         unsigned int __user *epc;
 356
 357         epc = (unsigned int __user *) regs->cp0_epc +
 358               ((regs->cp0_cause & CAUSEF_BD) != 0);
 359         if (!get_user(*opcode, epc))
 360                 return 0;
 361
 362         force_sig(SIGSEGV, current);
 363         return 1;
 364 }
 365
 366 /*
 367  * ll/sc emulation
 368  */
 369
 370 #define OPCODE 0xfc000000
 371 #define BASE   0x03e00000
 372 #define RT     0x001f0000
 373 #define OFFSET 0x0000ffff
 374 #define LL     0xc0000000
 375 #define SC     0xe0000000
 376 #define SPEC3  0x7c000000
 377 #define RD     0x0000f800
 378 #define FUNC   0x0000003f
 379 #define RDHWR  0x0000003b
 380
 381 /*
 382  * The ll_bit is cleared by r*_switch.S
 383  */
 384
 385 unsigned long ll_bit;
 386
 387 static struct task_struct *ll_task = NULL;
 388
 389 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
 390 {
 391         unsigned long value, __user *vaddr;
 392         long offset;
 393         int signal = 0;
 394
 395         /*
 396          * analyse the ll instruction that just caused a ri exception
 397          * and put the referenced address to addr.
 398          */
 399
 400         /* sign extend offset */
 401         offset = opcode & OFFSET;
 402         offset <<= 16;
 403         offset >>= 16;
 404
 405         vaddr = (unsigned long __user *)
 406                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 407
 408         if ((unsigned long)vaddr & 3) {
 409                 signal = SIGBUS;
 410                 goto sig;
 411         }
 412         if (get_user(value, vaddr)) {
 413                 signal = SIGSEGV;
 414                 goto sig;
 415         }
 416
 417         preempt_disable();
 418
 419         if (ll_task == NULL || ll_task == current) {
 420                 ll_bit = 1;
 421         } else {
 422                 ll_bit = 0;
 423         }
 424         ll_task = current;
 425
 426         preempt_enable();
 427
 428         compute_return_epc(regs);
 429
 430         regs->regs[(opcode & RT) >> 16] = value;
 431
 432         return;
 433
 434 sig:
 435         force_sig(signal, current);
 436 }
 437
 438 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
 439 {
 440         unsigned long __user *vaddr;
 441         unsigned long reg;
 442         long offset;
 443         int signal = 0;
 444
 445         /*
 446          * analyse the sc instruction that just caused a ri exception
 447          * and put the referenced address to addr.
 448          */
 449
 450         /* sign extend offset */
 451         offset = opcode & OFFSET;
 452         offset <<= 16;
 453         offset >>= 16;
 454
 455         vaddr = (unsigned long __user *)
 456                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 457         reg = (opcode & RT) >> 16;
 458
 459         if ((unsigned long)vaddr & 3) {
 460                 signal = SIGBUS;
 461                 goto sig;
 462         }
 463
 464         preempt_disable();
 465
 466         if (ll_bit == 0 || ll_task != current) {
 467                 compute_return_epc(regs);
 468                 regs->regs[reg] = 0;
 469                 preempt_enable();
 470                 return;
 471         }
 472
 473         preempt_enable();
 474
 475         if (put_user(regs->regs[reg], vaddr)) {
 476                 signal = SIGSEGV;
 477                 goto sig;
 478         }
 479
 480         compute_return_epc(regs);
 481         regs->regs[reg] = 1;
 482
 483         return;
 484
 485 sig:
 486         force_sig(signal, current);
 487 }
 488
 489 /*
 490  * ll uses the opcode of lwc0 and sc uses the opcode of swc0.  That is both
 491  * opcodes are supposed to result in coprocessor unusable exceptions if
 492  * executed on ll/sc-less processors.  That's the theory.  In practice a
 493  * few processors such as NEC's VR4100 throw reserved instruction exceptions
 494  * instead, so we're doing the emulation thing in both exception handlers.
 495  */
 496 static inline int simulate_llsc(struct pt_regs *regs)
 497 {
 498         unsigned int opcode;
 499
 500         if (unlikely(get_insn_opcode(regs, &opcode)))
 501                 return -EFAULT;
 502
 503         if ((opcode & OPCODE) == LL) {
 504                 simulate_ll(regs, opcode);
 505                 return 0;
 506         }
 507         if ((opcode & OPCODE) == SC) {
 508                 simulate_sc(regs, opcode);
 509                 return 0;
 510         }
 511
 512         return -EFAULT;                 /* Strange things going on ... */
 513 }
 514
 515 /*
 516  * Simulate trapping 'rdhwr' instructions to provide user accessible
 517  * registers not implemented in hardware.  The only current use of this
 518  * is the thread area pointer.
 519  */
 520 static inline int simulate_rdhwr(struct pt_regs *regs)
 521 {
 522         struct thread_info *ti = current->thread_info;
 523         unsigned int opcode;
 524
 525         if (unlikely(get_insn_opcode(regs, &opcode)))
 526                 return -EFAULT;
 527
 528         if (unlikely(compute_return_epc(regs)))
 529                 return -EFAULT;
 530
 531         if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
 532                 int rd = (opcode & RD) >> 11;
 533                 int rt = (opcode & RT) >> 16;
 534                 switch (rd) {
 535                         case 29:
 536                                 regs->regs[rt] = ti->tp_value;
 537                                 break;
 538                         default:
 539                                 return -EFAULT;
 540                 }
 541         }
 542
 543         return 0;
 544 }
 545
 546 asmlinkage void do_ov(struct pt_regs *regs)
 547 {
 548         siginfo_t info;
 549
 550         info.si_code = FPE_INTOVF;
 551         info.si_signo = SIGFPE;
 552         info.si_errno = 0;
 553         info.si_addr = (void __user *) regs->cp0_epc;
 554         force_sig_info(SIGFPE, &info, current);
 555 }
 556
 557 /*
 558  * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
 559  */
 560 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
 561 {
 562         if (fcr31 & FPU_CSR_UNI_X) {
 563                 int sig;
 564
 565                 preempt_disable();
 566
 567 #ifdef CONFIG_PREEMPT
 568                 if (!is_fpu_owner()) {
 569                         /* We might lose fpu before disabling preempt... */
 570                         own_fpu();
 571                         BUG_ON(!used_math());
 572                         restore_fp(current);
 573                 }
 574 #endif
 575                 /*
 576                  * Unimplemented operation exception.  If we've got the full
 577                  * software emulator on-board, let's use it...
 578                  *
 579                  * Force FPU to dump state into task/thread context.  We're
 580                  * moving a lot of data here for what is probably a single
 581                  * instruction, but the alternative is to pre-decode the FP
 582                  * register operands before invoking the emulator, which seems
 583                  * a bit extreme for what should be an infrequent event.
 584                  */
 585                 save_fp(current);
 586                 /* Ensure 'resume' not overwrite saved fp context again. */
 587                 lose_fpu();
 588
 589                 preempt_enable();
 590
 591                 /* Run the emulator */
 592                 sig = fpu_emulator_cop1Handler (0, regs,
 593                         &current->thread.fpu.soft);
 594
 595                 preempt_disable();
 596
 597                 own_fpu();      /* Using the FPU again.  */
 598                 /*
 599                  * We can't allow the emulated instruction to leave any of
 600                  * the cause bit set in $fcr31.
 601                  */
 602                 current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
 603
 604                 /* Restore the hardware register state */
 605                 restore_fp(current);
 606
 607                 preempt_enable();
 608
 609                 /* If something went wrong, signal */
 610                 if (sig)
 611                         force_sig(sig, current);
 612
 613                 return;
 614         }
 615
 616         force_sig(SIGFPE, current);
 617 }
 618
 619 asmlinkage void do_bp(struct pt_regs *regs)
 620 {
 621         unsigned int opcode, bcode;
 622         siginfo_t info;
 623
 624         die_if_kernel("Break instruction in kernel code", regs);
 625
 626         if (get_insn_opcode(regs, &opcode))
 627                 return;
 628
 629         /*
 630          * There is the ancient bug in the MIPS assemblers that the break
 631          * code starts left to bit 16 instead to bit 6 in the opcode.
 632          * Gas is bug-compatible, but not always, grrr...
 633          * We handle both cases with a simple heuristics.  --macro
 634          */
 635         bcode = ((opcode >> 6) & ((1 << 20) - 1));
 636         if (bcode < (1 << 10))
 637                 bcode <<= 10;
 638
 639         /*
 640          * (A short test says that IRIX 5.3 sends SIGTRAP for all break
 641          * insns, even for break codes that indicate arithmetic failures.
 642          * Weird ...)
 643          * But should we continue the brokenness???  --macro
 644          */
 645         switch (bcode) {
 646         case BRK_OVERFLOW << 10:
 647         case BRK_DIVZERO << 10:
 648                 if (bcode == (BRK_DIVZERO << 10))
 649                         info.si_code = FPE_INTDIV;
 650                 else
 651                         info.si_code = FPE_INTOVF;
 652                 info.si_signo = SIGFPE;
 653                 info.si_errno = 0;
 654                 info.si_addr = (void __user *) regs->cp0_epc;
 655                 force_sig_info(SIGFPE, &info, current);
 656                 break;
 657         default:
 658                 force_sig(SIGTRAP, current);
 659         }
 660 }
 661
 662 asmlinkage void do_tr(struct pt_regs *regs)
 663 {
 664         unsigned int opcode, tcode = 0;
 665         siginfo_t info;
 666
 667         die_if_kernel("Trap instruction in kernel code", regs);
 668
 669         if (get_insn_opcode(regs, &opcode))
 670                 return;
 671
 672         /* Immediate versions don't provide a code.  */
 673         if (!(opcode & OPCODE))
 674                 tcode = ((opcode >> 6) & ((1 << 10) - 1));
 675
 676         /*
 677          * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
 678          * insns, even for trap codes that indicate arithmetic failures.
 679          * Weird ...)
 680          * But should we continue the brokenness???  --macro
 681          */
 682         switch (tcode) {
 683         case BRK_OVERFLOW:
 684         case BRK_DIVZERO:
 685                 if (tcode == BRK_DIVZERO)
 686                         info.si_code = FPE_INTDIV;
 687                 else
 688                         info.si_code = FPE_INTOVF;
 689                 info.si_signo = SIGFPE;
 690                 info.si_errno = 0;
 691                 info.si_addr = (void __user *) regs->cp0_epc;
 692                 force_sig_info(SIGFPE, &info, current);
 693                 break;
 694         default:
 695                 force_sig(SIGTRAP, current);
 696         }
 697 }
 698
 699 asmlinkage void do_ri(struct pt_regs *regs)
 700 {
 701         die_if_kernel("Reserved instruction in kernel code", regs);
 702
 703         if (!cpu_has_llsc)
 704                 if (!simulate_llsc(regs))
 705                         return;
 706
 707         if (!simulate_rdhwr(regs))
 708                 return;
 709
 710         force_sig(SIGILL, current);
 711 }
 712
 713 asmlinkage void do_cpu(struct pt_regs *regs)
 714 {
 715         unsigned int cpid;
 716
 717         die_if_kernel("do_cpu invoked from kernel context!", regs);
 718
 719         cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
 720
 721         switch (cpid) {
 722         case 0:
 723                 if (!cpu_has_llsc)
 724                         if (!simulate_llsc(regs))
 725                                 return;
 726
 727                 if (!simulate_rdhwr(regs))
 728                         return;
 729
 730                 break;
 731
 732         case 1:
 733                 preempt_disable();
 734
 735                 own_fpu();
 736                 if (used_math()) {      /* Using the FPU again.  */
 737                         restore_fp(current);
 738                 } else {                        /* First time FPU user.  */
 739                         init_fpu();
 740                         set_used_math();
 741                 }
 742
 743                 preempt_enable();
 744
 745                 if (!cpu_has_fpu) {
 746                         int sig = fpu_emulator_cop1Handler(0, regs,
 747                                                 &current->thread.fpu.soft);
 748                         if (sig)
 749                                 force_sig(sig, current);
 750                 }
 751
 752                 return;
 753
 754         case 2:
 755         case 3:
 756                 break;
 757         }
 758
 759         force_sig(SIGILL, current);
 760 }
 761
 762 asmlinkage void do_mdmx(struct pt_regs *regs)
 763 {
 764         force_sig(SIGILL, current);
 765 }
 766
 767 asmlinkage void do_watch(struct pt_regs *regs)
 768 {
 769         /*
 770          * We use the watch exception where available to detect stack
 771          * overflows.
 772          */
 773         dump_tlb_all();
 774         show_regs(regs);
 775         panic("Caught WATCH exception - probably caused by stack overflow.");
 776 }
 777
 778 asmlinkage void do_mcheck(struct pt_regs *regs)
 779 {
 780         show_regs(regs);
 781         dump_tlb_all();
 782         /*
 783          * Some chips may have other causes of machine check (e.g. SB1
 784          * graduation timer)
 785          */
 786         panic("Caught Machine Check exception - %scaused by multiple "
 787               "matching entries in the TLB.",
 788               (regs->cp0_status & ST0_TS) ? "" : "not ");
 789 }
 790
 791 asmlinkage void do_mt(struct pt_regs *regs)
 792 {
 793         die_if_kernel("MIPS MT Thread exception in kernel", regs);
 794
 795         force_sig(SIGILL, current);
 796 }
 797
 798
 799 asmlinkage void do_dsp(struct pt_regs *regs)
 800 {
 801         if (cpu_has_dsp)
 802                 panic("Unexpected DSP exception\n");
 803
 804         force_sig(SIGILL, current);
 805 }
 806
 807 asmlinkage void do_reserved(struct pt_regs *regs)
 808 {
 809         /*
 810          * Game over - no way to handle this if it ever occurs.  Most probably
 811          * caused by a new unknown cpu type or after another deadly
 812          * hard/software error.
 813          */
 814         show_regs(regs);
 815         panic("Caught reserved exception %ld - should not happen.",
 816               (regs->cp0_cause & 0x7f) >> 2);
 817 }
 818
 819 asmlinkage void do_default_vi(struct pt_regs *regs)
 820 {
 821         show_regs(regs);
 822         panic("Caught unexpected vectored interrupt.");
 823 }
 824
 825 /*
 826  * Some MIPS CPUs can enable/disable for cache parity detection, but do
 827  * it different ways.
 828  */
 829 static inline void parity_protection_init(void)
 830 {
 831         switch (current_cpu_data.cputype) {
 832         case CPU_24K:
 833         case CPU_5KC:
 834                 write_c0_ecc(0x80000000);
 835                 back_to_back_c0_hazard();
 836                 /* Set the PE bit (bit 31) in the c0_errctl register. */
 837                 printk(KERN_INFO "Cache parity protection %sabled\n",
 838                        (read_c0_ecc() & 0x80000000) ? "en" : "dis");
 839                 break;
 840         case CPU_20KC:
 841         case CPU_25KF:
 842                 /* Clear the DE bit (bit 16) in the c0_status register. */
 843                 printk(KERN_INFO "Enable cache parity protection for "
 844                        "MIPS 20KC/25KF CPUs.\n");
 845                 clear_c0_status(ST0_DE);
 846                 break;
 847         default:
 848                 break;
 849         }
 850 }
 851
 852 asmlinkage void cache_parity_error(void)
 853 {
 854         const int field = 2 * sizeof(unsigned long);
 855         unsigned int reg_val;
 856
 857         /* For the moment, report the problem and hang. */
 858         printk("Cache error exception:\n");
 859         printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
 860         reg_val = read_c0_cacheerr();
 861         printk("c0_cacheerr == %08x\n", reg_val);
 862
 863         printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
 864                reg_val & (1<<30) ? "secondary" : "primary",
 865                reg_val & (1<<31) ? "data" : "insn");
 866         printk("Error bits: %s%s%s%s%s%s%s\n",
 867                reg_val & (1<<29) ? "ED " : "",
 868                reg_val & (1<<28) ? "ET " : "",
 869                reg_val & (1<<26) ? "EE " : "",
 870                reg_val & (1<<25) ? "EB " : "",
 871                reg_val & (1<<24) ? "EI " : "",
 872                reg_val & (1<<23) ? "E1 " : "",
 873                reg_val & (1<<22) ? "E0 " : "");
 874         printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
 875
 876 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
 877         if (reg_val & (1<<22))
 878                 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
 879
 880         if (reg_val & (1<<23))
 881                 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
 882 #endif
 883
 884         panic("Can't handle the cache error!");
 885 }
 886
 887 /*
 888  * SDBBP EJTAG debug exception handler.
 889  * We skip the instruction and return to the next instruction.
 890  */
 891 void ejtag_exception_handler(struct pt_regs *regs)
 892 {
 893         const int field = 2 * sizeof(unsigned long);
 894         unsigned long depc, old_epc;
 895         unsigned int debug;
 896
 897         printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
 898         depc = read_c0_depc();
 899         debug = read_c0_debug();
 900         printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
 901         if (debug & 0x80000000) {
 902                 /*
 903                  * In branch delay slot.
 904                  * We cheat a little bit here and use EPC to calculate the
 905                  * debug return address (DEPC). EPC is restored after the
 906                  * calculation.
 907                  */
 908                 old_epc = regs->cp0_epc;
 909                 regs->cp0_epc = depc;
 910                 __compute_return_epc(regs);
 911                 depc = regs->cp0_epc;
 912                 regs->cp0_epc = old_epc;
 913         } else
 914                 depc += 4;
 915         write_c0_depc(depc);
 916
 917 #if 0
 918         printk("\n\n----- Enable EJTAG single stepping ----\n\n");
 919         write_c0_debug(debug | 0x100);
 920 #endif
 921 }
 922
 923 /*
 924  * NMI exception handler.
 925  */
 926 void nmi_exception_handler(struct pt_regs *regs)
 927 {
 928         printk("NMI taken!!!!\n");
 929         die("NMI", regs);
 930         while(1) ;
 931 }
 932
 933 #define VECTORSPACING 0x100     /* for EI/VI mode */
 934
 935 unsigned long ebase;
 936 unsigned long exception_handlers[32];
 937 unsigned long vi_handlers[64];
 938
 939 /*
 940  * As a side effect of the way this is implemented we're limited
 941  * to interrupt handlers in the address range from
 942  * KSEG0 <= x < KSEG0 + 256mb on the Nevada.  Oh well ...
 943  */
 944 void *set_except_vector(int n, void *addr)
 945 {
 946         unsigned long handler = (unsigned long) addr;
 947         unsigned long old_handler = exception_handlers[n];
 948
 949         exception_handlers[n] = handler;
 950         if (n == 0 && cpu_has_divec) {
 951                 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
 952                                                  (0x03ffffff & (handler >> 2));
 953                 flush_icache_range(ebase + 0x200, ebase + 0x204);
 954         }
 955         return (void *)old_handler;
 956 }
 957
 958 #ifdef CONFIG_CPU_MIPSR2
 959 /*
 960  * Shadow register allocation
 961  * FIXME: SMP...
 962  */
 963
 964 /* MIPSR2 shadow register sets */
 965 struct shadow_registers {
 966         spinlock_t sr_lock;     /*  */
 967         int sr_supported;       /* Number of shadow register sets supported */
 968         int sr_allocated;       /* Bitmap of allocated shadow registers */
 969 } shadow_registers;
 970
 971 void mips_srs_init(void)
 972 {
 973 #ifdef CONFIG_CPU_MIPSR2_SRS
 974         shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
 975         printk ("%d MIPSR2 register sets available\n", shadow_registers.sr_supported);
 976 #else
 977         shadow_registers.sr_supported = 1;
 978 #endif
 979         shadow_registers.sr_allocated = 1;      /* Set 0 used by kernel */
 980         spin_lock_init(&shadow_registers.sr_lock);
 981 }
 982
 983 int mips_srs_max(void)
 984 {
 985         return shadow_registers.sr_supported;
 986 }
 987
 988 int mips_srs_alloc (void)
 989 {
 990         struct shadow_registers *sr = &shadow_registers;
 991         unsigned long flags;
 992         int set;
 993
 994         spin_lock_irqsave(&sr->sr_lock, flags);
 995
 996         for (set = 0; set < sr->sr_supported; set++) {
 997                 if ((sr->sr_allocated & (1 << set)) == 0) {
 998                         sr->sr_allocated |= 1 << set;
 999                         spin_unlock_irqrestore(&sr->sr_lock, flags);
1000                         return set;
1001                 }
1002         }
1003
1004         /* None available */
1005         spin_unlock_irqrestore(&sr->sr_lock, flags);
1006         return -1;
1007 }
1008
1009 void mips_srs_free (int set)
1010 {
1011         struct shadow_registers *sr = &shadow_registers;
1012         unsigned long flags;
1013
1014         spin_lock_irqsave(&sr->sr_lock, flags);
1015         sr->sr_allocated &= ~(1 << set);
1016         spin_unlock_irqrestore(&sr->sr_lock, flags);
1017 }
1018
1019 void *set_vi_srs_handler (int n, void *addr, int srs)
1020 {
1021         unsigned long handler;
1022         unsigned long old_handler = vi_handlers[n];
1023         u32 *w;
1024         unsigned char *b;
1025
1026         if (!cpu_has_veic && !cpu_has_vint)
1027                 BUG();
1028
1029         if (addr == NULL) {
1030                 handler = (unsigned long) do_default_vi;
1031                 srs = 0;
1032         }
1033         else
1034                 handler = (unsigned long) addr;
1035         vi_handlers[n] = (unsigned long) addr;
1036
1037         b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1038
1039         if (srs >= mips_srs_max())
1040                 panic("Shadow register set %d not supported", srs);
1041
1042         if (cpu_has_veic) {
1043                 if (board_bind_eic_interrupt)
1044                         board_bind_eic_interrupt (n, srs);
1045         }
1046         else if (cpu_has_vint) {
1047                 /* SRSMap is only defined if shadow sets are implemented */
1048                 if (mips_srs_max() > 1)
1049                         change_c0_srsmap (0xf << n*4, srs << n*4);
1050         }
1051
1052         if (srs == 0) {
1053                 /*
1054                  * If no shadow set is selected then use the default handler
1055                  * that does normal register saving and a standard interrupt exit
1056                  */
1057
1058                 extern char except_vec_vi, except_vec_vi_lui;
1059                 extern char except_vec_vi_ori, except_vec_vi_end;
1060                 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1061                 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1062                 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1063
1064                 if (handler_len > VECTORSPACING) {
1065                         /*
1066                          * Sigh... panicing won't help as the console
1067                          * is probably not configured :(
1068                          */
1069                         panic ("VECTORSPACING too small");
1070                 }
1071
1072                 memcpy (b, &except_vec_vi, handler_len);
1073                 w = (u32 *)(b + lui_offset);
1074                 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1075                 w = (u32 *)(b + ori_offset);
1076                 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1077                 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1078         }
1079         else {
1080                 /*
1081                  * In other cases jump directly to the interrupt handler
1082                  *
1083                  * It is the handlers responsibility to save registers if required
1084                  * (eg hi/lo) and return from the exception using "eret"
1085                  */
1086                 w = (u32 *)b;
1087                 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1088                 *w = 0;
1089                 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1090         }
1091
1092         return (void *)old_handler;
1093 }
1094
1095 void *set_vi_handler (int n, void *addr)
1096 {
1097         return set_vi_srs_handler (n, addr, 0);
1098 }
1099 #endif
1100
1101 /*
1102  * This is used by native signal handling
1103  */
1104 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1105 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1106
1107 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1108 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1109
1110 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1111 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1112
1113 static inline void signal_init(void)
1114 {
1115         if (cpu_has_fpu) {
1116                 save_fp_context = _save_fp_context;
1117                 restore_fp_context = _restore_fp_context;
1118         } else {
1119                 save_fp_context = fpu_emulator_save_context;
1120                 restore_fp_context = fpu_emulator_restore_context;
1121         }
1122 }
1123
1124 #ifdef CONFIG_MIPS32_COMPAT
1125
1126 /*
1127  * This is used by 32-bit signal stuff on the 64-bit kernel
1128  */
1129 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1130 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1131
1132 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1133 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1134
1135 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1136 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1137
1138 static inline void signal32_init(void)
1139 {
1140         if (cpu_has_fpu) {
1141                 save_fp_context32 = _save_fp_context32;
1142                 restore_fp_context32 = _restore_fp_context32;
1143         } else {
1144                 save_fp_context32 = fpu_emulator_save_context32;
1145                 restore_fp_context32 = fpu_emulator_restore_context32;
1146         }
1147 }
1148 #endif
1149
1150 extern void cpu_cache_init(void);
1151 extern void tlb_init(void);
1152 extern void flush_tlb_handlers(void);
1153
1154 void __init per_cpu_trap_init(void)
1155 {
1156         unsigned int cpu = smp_processor_id();
1157         unsigned int status_set = ST0_CU0;
1158
1159         /*
1160          * Disable coprocessors and select 32-bit or 64-bit addressing
1161          * and the 16/32 or 32/32 FPR register model.  Reset the BEV
1162          * flag that some firmware may have left set and the TS bit (for
1163          * IP27).  Set XX for ISA IV code to work.
1164          */
1165 #ifdef CONFIG_64BIT
1166         status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1167 #endif
1168         if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1169                 status_set |= ST0_XX;
1170         change_c0_status(ST0_CU|ST0_MX|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1171                          status_set);
1172
1173         if (cpu_has_dsp)
1174                 set_c0_status(ST0_MX);
1175
1176 #ifdef CONFIG_CPU_MIPSR2
1177         write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1178 #endif
1179
1180         /*
1181          * Interrupt handling.
1182          */
1183         if (cpu_has_veic || cpu_has_vint) {
1184                 write_c0_ebase (ebase);
1185                 /* Setting vector spacing enables EI/VI mode  */
1186                 change_c0_intctl (0x3e0, VECTORSPACING);
1187         }
1188         if (cpu_has_divec) {
1189                 if (cpu_has_mipsmt) {
1190                         unsigned int vpflags = dvpe();
1191                         set_c0_cause(CAUSEF_IV);
1192                         evpe(vpflags);
1193                 } else
1194                         set_c0_cause(CAUSEF_IV);
1195         }
1196
1197         cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1198         TLBMISS_HANDLER_SETUP();
1199
1200         atomic_inc(&init_mm.mm_count);
1201         current->active_mm = &init_mm;
1202         BUG_ON(current->mm);
1203         enter_lazy_tlb(&init_mm, current);
1204
1205         cpu_cache_init();
1206         tlb_init();
1207 }
1208
1209 /* Install CPU exception handler */
1210 void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1211 {
1212         memcpy((void *)(ebase + offset), addr, size);
1213         flush_icache_range(ebase + offset, ebase + offset + size);
1214 }
1215
1216 /* Install uncached CPU exception handler */
1217 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1218 {
1219 #ifdef CONFIG_32BIT
1220         unsigned long uncached_ebase = KSEG1ADDR(ebase);
1221 #endif
1222 #ifdef CONFIG_64BIT
1223         unsigned long uncached_ebase = TO_UNCAC(ebase);
1224 #endif
1225
1226         memcpy((void *)(uncached_ebase + offset), addr, size);
1227 }
1228
1229 void __init trap_init(void)
1230 {
1231         extern char except_vec3_generic, except_vec3_r4000;
1232         extern char except_vec4;
1233         unsigned long i;
1234
1235         if (cpu_has_veic || cpu_has_vint)
1236                 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1237         else
1238                 ebase = CAC_BASE;
1239
1240 #ifdef CONFIG_CPU_MIPSR2
1241         mips_srs_init();
1242 #endif
1243
1244         per_cpu_trap_init();
1245
1246         /*
1247          * Copy the generic exception handlers to their final destination.
1248          * This will be overriden later as suitable for a particular
1249          * configuration.
1250          */
1251         set_handler(0x180, &except_vec3_generic, 0x80);
1252
1253         /*
1254          * Setup default vectors
1255          */
1256         for (i = 0; i <= 31; i++)
1257                 set_except_vector(i, handle_reserved);
1258
1259         /*
1260          * Copy the EJTAG debug exception vector handler code to it's final
1261          * destination.
1262          */
1263         if (cpu_has_ejtag && board_ejtag_handler_setup)
1264                 board_ejtag_handler_setup ();
1265
1266         /*
1267          * Only some CPUs have the watch exceptions.
1268          */
1269         if (cpu_has_watch)
1270                 set_except_vector(23, handle_watch);
1271
1272         /*
1273          * Initialise interrupt handlers
1274          */
1275         if (cpu_has_veic || cpu_has_vint) {
1276                 int nvec = cpu_has_veic ? 64 : 8;
1277                 for (i = 0; i < nvec; i++)
1278                         set_vi_handler (i, NULL);
1279         }
1280         else if (cpu_has_divec)
1281                 set_handler(0x200, &except_vec4, 0x8);
1282
1283         /*
1284          * Some CPUs can enable/disable for cache parity detection, but does
1285          * it different ways.
1286          */
1287         parity_protection_init();
1288
1289         /*
1290          * The Data Bus Errors / Instruction Bus Errors are signaled
1291          * by external hardware.  Therefore these two exceptions
1292          * may have board specific handlers.
1293          */
1294         if (board_be_init)
1295                 board_be_init();
1296
1297         set_except_vector(1, handle_tlbm);
1298         set_except_vector(2, handle_tlbl);
1299         set_except_vector(3, handle_tlbs);
1300
1301         set_except_vector(4, handle_adel);
1302         set_except_vector(5, handle_ades);
1303
1304         set_except_vector(6, handle_ibe);
1305         set_except_vector(7, handle_dbe);
1306
1307         set_except_vector(8, handle_sys);
1308         set_except_vector(9, handle_bp);
1309         set_except_vector(10, handle_ri);
1310         set_except_vector(11, handle_cpu);
1311         set_except_vector(12, handle_ov);
1312         set_except_vector(13, handle_tr);
1313
1314         if (current_cpu_data.cputype == CPU_R6000 ||
1315             current_cpu_data.cputype == CPU_R6000A) {
1316                 /*
1317                  * The R6000 is the only R-series CPU that features a machine
1318                  * check exception (similar to the R4000 cache error) and
1319                  * unaligned ldc1/sdc1 exception.  The handlers have not been
1320                  * written yet.  Well, anyway there is no R6000 machine on the
1321                  * current list of targets for Linux/MIPS.
1322                  * (Duh, crap, there is someone with a triple R6k machine)
1323                  */
1324                 //set_except_vector(14, handle_mc);
1325                 //set_except_vector(15, handle_ndc);
1326         }
1327
1328
1329         if (board_nmi_handler_setup)
1330                 board_nmi_handler_setup();
1331
1332         if (cpu_has_fpu && !cpu_has_nofpuex)
1333                 set_except_vector(15, handle_fpe);
1334
1335         set_except_vector(22, handle_mdmx);
1336
1337         if (cpu_has_mcheck)
1338                 set_except_vector(24, handle_mcheck);
1339
1340         if (cpu_has_mipsmt)
1341                 set_except_vector(25, handle_mt);
1342
1343         if (cpu_has_dsp)
1344                 set_except_vector(26, handle_dsp);
1345
1346         if (cpu_has_vce)
1347                 /* Special exception: R4[04]00 uses also the divec space. */
1348                 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1349         else if (cpu_has_4kex)
1350                 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1351         else
1352                 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1353
1354         signal_init();
1355 #ifdef CONFIG_MIPS32_COMPAT
1356         signal32_init();
1357 #endif
1358
1359         flush_icache_range(ebase, ebase + 0x400);
1360         flush_tlb_handlers();
1361 }