| blob | 1e985f2cd70fc4ab0df4dfa07616d9204b6fa87a |
1 /*
2 * linux/arch/arm/kernel/head.S
3 *
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Kernel startup code for all 32-bit CPUs
13 */
14 #include <linux/config.h>
15 #include <linux/linkage.h>
16 #include <linux/init.h>
18 #include <asm/assembler.h>
19 #include <asm/domain.h>
20 #include <asm/procinfo.h>
21 #include <asm/ptrace.h>
22 #include <asm/asm-offsets.h>
23 #include <asm/memory.h>
24 #include <asm/thread_info.h>
25 #include <asm/system.h>
27 #define PROCINFO_MMUFLAGS 8
28 #define PROCINFO_INITFUNC 12
30 #define MACHINFO_TYPE 0
31 #define MACHINFO_PHYSRAM 4
32 #define MACHINFO_PHYSIO 8
33 #define MACHINFO_PGOFFIO 12
34 #define MACHINFO_NAME 16
36 #define KERNEL_RAM_ADDR (PAGE_OFFSET + TEXT_OFFSET)
38 /*
39 * swapper_pg_dir is the virtual address of the initial page table.
40 * We place the page tables 16K below KERNEL_RAM_ADDR. Therefore, we must
41 * make sure that KERNEL_RAM_ADDR is correctly set. Currently, we expect
42 * the least significant 16 bits to be 0x8000, but we could probably
43 * relax this restriction to KERNEL_RAM_ADDR >= PAGE_OFFSET + 0x4000.
44 */
45 #if (KERNEL_RAM_ADDR & 0xffff) != 0x8000
46 #error KERNEL_RAM_ADDR must start at 0xXXXX8000
47 #endif
49 .globl swapper_pg_dir
50 .equ swapper_pg_dir, KERNEL_RAM_ADDR - 0x4000
52 .macro pgtbl, rd
53 ldr \rd, =(__virt_to_phys(KERNEL_RAM_ADDR - 0x4000))
54 .endm
56 #ifdef CONFIG_XIP_KERNEL
57 #define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
58 #else
59 #define TEXTADDR KERNEL_RAM_ADDR
60 #endif
62 /*
63 * Kernel startup entry point.
64 * ---------------------------
65 *
66 * This is normally called from the decompressor code. The requirements
67 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
68 * r1 = machine nr.
69 *
70 * This code is mostly position independent, so if you link the kernel at
71 * 0xc0008000, you call this at __pa(0xc0008000).
72 *
73 * See linux/arch/arm/tools/mach-types for the complete list of machine
74 * numbers for r1.
75 *
76 * We're trying to keep crap to a minimum; DO NOT add any machine specific
77 * crap here - that's what the boot loader (or in extreme, well justified
78 * circumstances, zImage) is for.
79 */
80 __INIT
81 .type stext, %function
82 ENTRY(stext)
83 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
84 @ and irqs disabled
85 bl __lookup_processor_type @ r5=procinfo r9=cpuid
86 movs r10, r5 @ invalid processor (r5=0)?
87 beq __error_p @ yes, error 'p'
88 bl __lookup_machine_type @ r5=machinfo
89 movs r8, r5 @ invalid machine (r5=0)?
90 beq __error_a @ yes, error 'a'
91 bl __create_page_tables
93 /*
94 * The following calls CPU specific code in a position independent
95 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
96 * xxx_proc_info structure selected by __lookup_machine_type
97 * above. On return, the CPU will be ready for the MMU to be
98 * turned on, and r0 will hold the CPU control register value.
99 */
100 ldr r13, __switch_data @ address to jump to after
101 @ mmu has been enabled
102 adr lr, __enable_mmu @ return (PIC) address
103 add pc, r10, #PROCINFO_INITFUNC
105 .type __switch_data, %object
106 __switch_data:
107 .long __mmap_switched
108 .long __data_loc @ r4
109 .long __data_start @ r5
110 .long __bss_start @ r6
111 .long _end @ r7
112 .long processor_id @ r4
113 .long __machine_arch_type @ r5
114 .long cr_alignment @ r6
115 .long init_thread_union + THREAD_START_SP @ sp
117 /*
118 * The following fragment of code is executed with the MMU on, and uses
119 * absolute addresses; this is not position independent.
120 *
121 * r0 = cp#15 control register
122 * r1 = machine ID
123 * r9 = processor ID
124 */
125 .type __mmap_switched, %function
126 __mmap_switched:
127 adr r3, __switch_data + 4
129 ldmia r3!, {r4, r5, r6, r7}
130 cmp r4, r5 @ Copy data segment if needed
131 1: cmpne r5, r6
132 ldrne fp, [r4], #4
133 strne fp, [r5], #4
134 bne 1b
136 mov fp, #0 @ Clear BSS (and zero fp)
137 1: cmp r6, r7
138 strcc fp, [r6],#4
139 bcc 1b
141 ldmia r3, {r4, r5, r6, sp}
142 str r9, [r4] @ Save processor ID
143 str r1, [r5] @ Save machine type
144 bic r4, r0, #CR_A @ Clear 'A' bit
145 stmia r6, {r0, r4} @ Save control register values
146 b start_kernel
148 #if defined(CONFIG_SMP)
149 .type secondary_startup, #function
150 ENTRY(secondary_startup)
151 /*
152 * Common entry point for secondary CPUs.
153 *
154 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
155 * the processor type - there is no need to check the machine type
156 * as it has already been validated by the primary processor.
157 */
158 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
159 bl __lookup_processor_type
160 movs r10, r5 @ invalid processor?
161 moveq r0, #'p' @ yes, error 'p'
162 beq __error
164 /*
165 * Use the page tables supplied from __cpu_up.
166 */
167 adr r4, __secondary_data
168 ldmia r4, {r5, r6, r13} @ address to jump to after
169 sub r4, r4, r5 @ mmu has been enabled
170 ldr r4, [r6, r4] @ get secondary_data.pgdir
171 adr lr, __enable_mmu @ return address
172 add pc, r10, #12 @ initialise processor
173 @ (return control reg)
175 /*
176 * r6 = &secondary_data
177 */
178 ENTRY(__secondary_switched)
179 ldr sp, [r6, #4] @ get secondary_data.stack
180 mov fp, #0
181 b secondary_start_kernel
183 .type __secondary_data, %object
184 __secondary_data:
185 .long .
186 .long secondary_data
187 .long __secondary_switched
188 #endif /* defined(CONFIG_SMP) */
192 /*
193 * Setup common bits before finally enabling the MMU. Essentially
194 * this is just loading the page table pointer and domain access
195 * registers.
196 */
197 .type __enable_mmu, %function
198 __enable_mmu:
199 #ifdef CONFIG_ALIGNMENT_TRAP
200 orr r0, r0, #CR_A
201 #else
202 bic r0, r0, #CR_A
203 #endif
204 #ifdef CONFIG_CPU_DCACHE_DISABLE
205 bic r0, r0, #CR_C
206 #endif
207 #ifdef CONFIG_CPU_BPREDICT_DISABLE
208 bic r0, r0, #CR_Z
209 #endif
210 #ifdef CONFIG_CPU_ICACHE_DISABLE
211 bic r0, r0, #CR_I
212 #endif
213 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
214 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
215 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
216 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
217 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
218 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
219 b __turn_mmu_on
221 /*
222 * Enable the MMU. This completely changes the structure of the visible
223 * memory space. You will not be able to trace execution through this.
224 * If you have an enquiry about this, *please* check the linux-arm-kernel
225 * mailing list archives BEFORE sending another post to the list.
226 *
227 * r0 = cp#15 control register
228 * r13 = *virtual* address to jump to upon completion
229 *
230 * other registers depend on the function called upon completion
231 */
232 .align 5
233 .type __turn_mmu_on, %function
234 __turn_mmu_on:
235 mov r0, r0
236 mcr p15, 0, r0, c1, c0, 0 @ write control reg
237 mrc p15, 0, r3, c0, c0, 0 @ read id reg
238 mov r3, r3
239 mov r3, r3
240 mov pc, r13
244 /*
245 * Setup the initial page tables. We only setup the barest
246 * amount which are required to get the kernel running, which
247 * generally means mapping in the kernel code.
248 *
249 * r8 = machinfo
250 * r9 = cpuid
251 * r10 = procinfo
252 *
253 * Returns:
254 * r0, r3, r5, r6, r7 corrupted
255 * r4 = physical page table address
256 */
257 .type __create_page_tables, %function
258 __create_page_tables:
259 ldr r5, [r8, #MACHINFO_PHYSRAM] @ physram
260 pgtbl r4 @ page table address
262 /*
263 * Clear the 16K level 1 swapper page table
264 */
265 mov r0, r4
266 mov r3, #0
267 add r6, r0, #0x4000
268 1: str r3, [r0], #4
269 str r3, [r0], #4
270 str r3, [r0], #4
271 str r3, [r0], #4
272 teq r0, r6
273 bne 1b
275 ldr r7, [r10, #PROCINFO_MMUFLAGS] @ mmuflags
277 /*
278 * Create identity mapping for first MB of kernel to
279 * cater for the MMU enable. This identity mapping
280 * will be removed by paging_init(). We use our current program
281 * counter to determine corresponding section base address.
282 */
283 mov r6, pc, lsr #20 @ start of kernel section
284 orr r3, r7, r6, lsl #20 @ flags + kernel base
285 str r3, [r4, r6, lsl #2] @ identity mapping
287 /*
288 * Now setup the pagetables for our kernel direct
289 * mapped region. We round TEXTADDR down to the
290 * nearest megabyte boundary. It is assumed that
291 * the kernel fits within 4 contigous 1MB sections.
292 */
293 add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel
294 str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]!
295 add r3, r3, #1 << 20
296 str r3, [r0, #4]! @ KERNEL + 1MB
297 add r3, r3, #1 << 20
298 str r3, [r0, #4]! @ KERNEL + 2MB
299 add r3, r3, #1 << 20
300 str r3, [r0, #4] @ KERNEL + 3MB
302 /*
303 * Then map first 1MB of ram in case it contains our boot params.
304 */
305 add r0, r4, #PAGE_OFFSET >> 18
306 orr r6, r5, r7
307 str r6, [r0]
309 #ifdef CONFIG_XIP_KERNEL
310 /*
311 * Map some ram to cover our .data and .bss areas.
312 * Mapping 3MB should be plenty.
313 */
314 sub r3, r4, r5
315 mov r3, r3, lsr #20
316 add r0, r0, r3, lsl #2
317 add r6, r6, r3, lsl #20
318 str r6, [r0], #4
319 add r6, r6, #(1 << 20)
320 str r6, [r0], #4
321 add r6, r6, #(1 << 20)
322 str r6, [r0]
323 #endif
325 #ifdef CONFIG_DEBUG_LL
326 bic r7, r7, #0x0c @ turn off cacheable
327 @ and bufferable bits
328 /*
329 * Map in IO space for serial debugging.
330 * This allows debug messages to be output
331 * via a serial console before paging_init.
332 */
333 ldr r3, [r8, #MACHINFO_PGOFFIO]
334 add r0, r4, r3
335 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
336 cmp r3, #0x0800 @ limit to 512MB
337 movhi r3, #0x0800
338 add r6, r0, r3
339 ldr r3, [r8, #MACHINFO_PHYSIO]
340 orr r3, r3, r7
341 1: str r3, [r0], #4
342 add r3, r3, #1 << 20
343 teq r0, r6
344 bne 1b
345 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
346 /*
347 * If we're using the NetWinder or CATS, we also need to map
348 * in the 16550-type serial port for the debug messages
349 */
350 add r0, r4, #0xff000000 >> 18
351 orr r3, r7, #0x7c000000
352 str r3, [r0]
353 #endif
354 #ifdef CONFIG_ARCH_RPC
355 /*
356 * Map in screen at 0x02000000 & SCREEN2_BASE
357 * Similar reasons here - for debug. This is
358 * only for Acorn RiscPC architectures.
359 */
360 add r0, r4, #0x02000000 >> 18
361 orr r3, r7, #0x02000000
362 str r3, [r0]
363 add r0, r4, #0xd8000000 >> 18
364 str r3, [r0]
365 #endif
366 #endif
367 mov pc, lr
368 .ltorg
372 /*
373 * Exception handling. Something went wrong and we can't proceed. We
374 * ought to tell the user, but since we don't have any guarantee that
375 * we're even running on the right architecture, we do virtually nothing.
376 *
377 * If CONFIG_DEBUG_LL is set we try to print out something about the error
378 * and hope for the best (useful if bootloader fails to pass a proper
379 * machine ID for example).
380 */
382 .type __error_p, %function
383 __error_p:
384 #ifdef CONFIG_DEBUG_LL
385 adr r0, str_p1
386 bl printascii
387 b __error
388 str_p1: .asciz "\nError: unrecognized/unsupported processor variant.\n"
389 .align
390 #endif
392 .type __error_a, %function
393 __error_a:
394 #ifdef CONFIG_DEBUG_LL
395 mov r4, r1 @ preserve machine ID
396 adr r0, str_a1
397 bl printascii
398 mov r0, r4
399 bl printhex8
400 adr r0, str_a2
401 bl printascii
402 adr r3, 3f
403 ldmia r3, {r4, r5, r6} @ get machine desc list
404 sub r4, r3, r4 @ get offset between virt&phys
405 add r5, r5, r4 @ convert virt addresses to
406 add r6, r6, r4 @ physical address space
407 1: ldr r0, [r5, #MACHINFO_TYPE] @ get machine type
408 bl printhex8
409 mov r0, #'\t'
410 bl printch
411 ldr r0, [r5, #MACHINFO_NAME] @ get machine name
412 add r0, r0, r4
413 bl printascii
414 mov r0, #'\n'
415 bl printch
416 add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc
417 cmp r5, r6
418 blo 1b
419 adr r0, str_a3
420 bl printascii
421 b __error
422 str_a1: .asciz "\nError: unrecognized/unsupported machine ID (r1 = 0x"
423 str_a2: .asciz ").\n\nAvailable machine support:\n\nID (hex)\tNAME\n"
424 str_a3: .asciz "\nPlease check your kernel config and/or bootloader.\n"
425 .align
426 #endif
428 .type __error, %function
429 __error:
430 #ifdef CONFIG_ARCH_RPC
431 /*
432 * Turn the screen red on a error - RiscPC only.
433 */
434 mov r0, #0x02000000
435 mov r3, #0x11
436 orr r3, r3, r3, lsl #8
437 orr r3, r3, r3, lsl #16
438 str r3, [r0], #4
439 str r3, [r0], #4
440 str r3, [r0], #4
441 str r3, [r0], #4
442 #endif
443 1: mov r0, r0
444 b 1b
447 /*
448 * Read processor ID register (CP#15, CR0), and look up in the linker-built
449 * supported processor list. Note that we can't use the absolute addresses
450 * for the __proc_info lists since we aren't running with the MMU on
451 * (and therefore, we are not in the correct address space). We have to
452 * calculate the offset.
453 *
454 * Returns:
455 * r3, r4, r6 corrupted
456 * r5 = proc_info pointer in physical address space
457 * r9 = cpuid
458 */
459 .type __lookup_processor_type, %function
460 __lookup_processor_type:
461 adr r3, 3f
462 ldmda r3, {r5, r6, r9}
463 sub r3, r3, r9 @ get offset between virt&phys
464 add r5, r5, r3 @ convert virt addresses to
465 add r6, r6, r3 @ physical address space
466 mrc p15, 0, r9, c0, c0 @ get processor id
467 1: ldmia r5, {r3, r4} @ value, mask
468 and r4, r4, r9 @ mask wanted bits
469 teq r3, r4
470 beq 2f
471 add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list)
472 cmp r5, r6
473 blo 1b
474 mov r5, #0 @ unknown processor
475 2: mov pc, lr
477 /*
478 * This provides a C-API version of the above function.
479 */
480 ENTRY(lookup_processor_type)
481 stmfd sp!, {r4 - r6, r9, lr}
482 bl __lookup_processor_type
483 mov r0, r5
484 ldmfd sp!, {r4 - r6, r9, pc}
486 /*
487 * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for
488 * more information about the __proc_info and __arch_info structures.
489 */
490 .long __proc_info_begin
491 .long __proc_info_end
492 3: .long .
493 .long __arch_info_begin
494 .long __arch_info_end
496 /*
497 * Lookup machine architecture in the linker-build list of architectures.
498 * Note that we can't use the absolute addresses for the __arch_info
499 * lists since we aren't running with the MMU on (and therefore, we are
500 * not in the correct address space). We have to calculate the offset.
501 *
502 * r1 = machine architecture number
503 * Returns:
504 * r3, r4, r6 corrupted
505 * r5 = mach_info pointer in physical address space
506 */
507 .type __lookup_machine_type, %function
508 __lookup_machine_type:
509 adr r3, 3b
510 ldmia r3, {r4, r5, r6}
511 sub r3, r3, r4 @ get offset between virt&phys
512 add r5, r5, r3 @ convert virt addresses to
513 add r6, r6, r3 @ physical address space
514 1: ldr r3, [r5, #MACHINFO_TYPE] @ get machine type
515 teq r3, r1 @ matches loader number?
516 beq 2f @ found
517 add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc
518 cmp r5, r6
519 blo 1b
520 mov r5, #0 @ unknown machine
521 2: mov pc, lr
523 /*
524 * This provides a C-API version of the above function.
525 */
526 ENTRY(lookup_machine_type)
527 stmfd sp!, {r4 - r6, lr}
528 mov r1, r0
529 bl __lookup_machine_type
530 mov r0, r5
531 ldmfd sp!, {r4 - r6, pc}