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[PATCH] percpu counter data type changes to suppport more than 2**31 ext3 free blocks...
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / scsi / sata_promise.c
blob7eb67a6bdc64ca4a08f3fb3739e63b0b4c6d706d
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include <asm/io.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.04"
50
51
52 enum {
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_TBG_MODE = 0x41, /* TBG mode */
56 PDC_FLASH_CTL = 0x44, /* Flash control register */
57 PDC_PCI_CTL = 0x48, /* PCI control and status register */
58 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
59 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
61 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
62 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
63
64 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
65 (1<<8) | (1<<9) | (1<<10),
66
67 board_2037x = 0, /* FastTrak S150 TX2plus */
68 board_20319 = 1, /* FastTrak S150 TX4 */
69 board_20619 = 2, /* FastTrak TX4000 */
70 board_20771 = 3, /* FastTrak TX2300 */
71 board_2057x = 4, /* SATAII150 Tx2plus */
72 board_40518 = 5, /* SATAII150 Tx4 */
73
74 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
75
76 PDC_RESET = (1 << 11), /* HDMA reset */
77
78 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
79 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI,
80 };
81
82
83 struct pdc_port_priv {
84 u8 *pkt;
85 dma_addr_t pkt_dma;
86 };
87
88 struct pdc_host_priv {
89 int hotplug_offset;
90 };
91
92 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
93 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
94 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
95 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
96 static void pdc_eng_timeout(struct ata_port *ap);
97 static int pdc_port_start(struct ata_port *ap);
98 static void pdc_port_stop(struct ata_port *ap);
99 static void pdc_pata_phy_reset(struct ata_port *ap);
100 static void pdc_sata_phy_reset(struct ata_port *ap);
101 static void pdc_qc_prep(struct ata_queued_cmd *qc);
102 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
103 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
104 static void pdc_irq_clear(struct ata_port *ap);
105 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
106 static void pdc_host_stop(struct ata_host_set *host_set);
107
108
109 static struct scsi_host_template pdc_ata_sht = {
110 .module = THIS_MODULE,
111 .name = DRV_NAME,
112 .ioctl = ata_scsi_ioctl,
113 .queuecommand = ata_scsi_queuecmd,
114 .can_queue = ATA_DEF_QUEUE,
115 .this_id = ATA_SHT_THIS_ID,
116 .sg_tablesize = LIBATA_MAX_PRD,
117 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
118 .emulated = ATA_SHT_EMULATED,
119 .use_clustering = ATA_SHT_USE_CLUSTERING,
120 .proc_name = DRV_NAME,
121 .dma_boundary = ATA_DMA_BOUNDARY,
122 .slave_configure = ata_scsi_slave_config,
123 .bios_param = ata_std_bios_param,
124 };
125
126 static const struct ata_port_operations pdc_sata_ops = {
127 .port_disable = ata_port_disable,
128 .tf_load = pdc_tf_load_mmio,
129 .tf_read = ata_tf_read,
130 .check_status = ata_check_status,
131 .exec_command = pdc_exec_command_mmio,
132 .dev_select = ata_std_dev_select,
133
134 .phy_reset = pdc_sata_phy_reset,
135
136 .qc_prep = pdc_qc_prep,
137 .qc_issue = pdc_qc_issue_prot,
138 .eng_timeout = pdc_eng_timeout,
139 .irq_handler = pdc_interrupt,
140 .irq_clear = pdc_irq_clear,
141
142 .scr_read = pdc_sata_scr_read,
143 .scr_write = pdc_sata_scr_write,
144 .port_start = pdc_port_start,
145 .port_stop = pdc_port_stop,
146 .host_stop = pdc_host_stop,
147 };
148
149 static const struct ata_port_operations pdc_pata_ops = {
150 .port_disable = ata_port_disable,
151 .tf_load = pdc_tf_load_mmio,
152 .tf_read = ata_tf_read,
153 .check_status = ata_check_status,
154 .exec_command = pdc_exec_command_mmio,
155 .dev_select = ata_std_dev_select,
156
157 .phy_reset = pdc_pata_phy_reset,
158
159 .qc_prep = pdc_qc_prep,
160 .qc_issue = pdc_qc_issue_prot,
161 .eng_timeout = pdc_eng_timeout,
162 .irq_handler = pdc_interrupt,
163 .irq_clear = pdc_irq_clear,
164
165 .port_start = pdc_port_start,
166 .port_stop = pdc_port_stop,
167 .host_stop = pdc_host_stop,
168 };
169
170 static const struct ata_port_info pdc_port_info[] = {
171 /* board_2037x */
172 {
173 .sht = &pdc_ata_sht,
174 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
175 .pio_mask = 0x1f, /* pio0-4 */
176 .mwdma_mask = 0x07, /* mwdma0-2 */
177 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
178 .port_ops = &pdc_sata_ops,
179 },
180
181 /* board_20319 */
182 {
183 .sht = &pdc_ata_sht,
184 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
185 .pio_mask = 0x1f, /* pio0-4 */
186 .mwdma_mask = 0x07, /* mwdma0-2 */
187 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
188 .port_ops = &pdc_sata_ops,
189 },
190
191 /* board_20619 */
192 {
193 .sht = &pdc_ata_sht,
194 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
195 .pio_mask = 0x1f, /* pio0-4 */
196 .mwdma_mask = 0x07, /* mwdma0-2 */
197 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
198 .port_ops = &pdc_pata_ops,
199 },
200
201 /* board_20771 */
202 {
203 .sht = &pdc_ata_sht,
204 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
205 .pio_mask = 0x1f, /* pio0-4 */
206 .mwdma_mask = 0x07, /* mwdma0-2 */
207 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
208 .port_ops = &pdc_sata_ops,
209 },
210
211 /* board_2057x */
212 {
213 .sht = &pdc_ata_sht,
214 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
215 .pio_mask = 0x1f, /* pio0-4 */
216 .mwdma_mask = 0x07, /* mwdma0-2 */
217 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
218 .port_ops = &pdc_sata_ops,
219 },
220
221 /* board_40518 */
222 {
223 .sht = &pdc_ata_sht,
224 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
225 .pio_mask = 0x1f, /* pio0-4 */
226 .mwdma_mask = 0x07, /* mwdma0-2 */
227 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
228 .port_ops = &pdc_sata_ops,
229 },
230 };
231
232 static const struct pci_device_id pdc_ata_pci_tbl[] = {
233 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
234 board_2037x },
235 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
236 board_2037x },
237 { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
238 board_2037x },
239 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
240 board_2037x },
241 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
242 board_2037x },
243 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
244 board_2037x },
245 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
246 board_2057x },
247 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
248 board_2057x },
249 { PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
250 board_2037x },
251
252 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
253 board_20319 },
254 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
255 board_20319 },
256 { PCI_VENDOR_ID_PROMISE, 0x3515, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
257 board_20319 },
258 { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
259 board_20319 },
260 { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 board_20319 },
262 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_40518 },
264
265 { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
266 board_20619 },
267
268 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 board_20771 },
270 { } /* terminate list */
271 };
272
273
274 static struct pci_driver pdc_ata_pci_driver = {
275 .name = DRV_NAME,
276 .id_table = pdc_ata_pci_tbl,
277 .probe = pdc_ata_init_one,
278 .remove = ata_pci_remove_one,
279 };
280
281
282 static int pdc_port_start(struct ata_port *ap)
283 {
284 struct device *dev = ap->host_set->dev;
285 struct pdc_port_priv *pp;
286 int rc;
287
288 rc = ata_port_start(ap);
289 if (rc)
290 return rc;
291
292 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
293 if (!pp) {
294 rc = -ENOMEM;
295 goto err_out;
296 }
297
298 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
299 if (!pp->pkt) {
300 rc = -ENOMEM;
301 goto err_out_kfree;
302 }
303
304 ap->private_data = pp;
305
306 return 0;
307
308 err_out_kfree:
309 kfree(pp);
310 err_out:
311 ata_port_stop(ap);
312 return rc;
313 }
314
315
316 static void pdc_port_stop(struct ata_port *ap)
317 {
318 struct device *dev = ap->host_set->dev;
319 struct pdc_port_priv *pp = ap->private_data;
320
321 ap->private_data = NULL;
322 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
323 kfree(pp);
324 ata_port_stop(ap);
325 }
326
327
328 static void pdc_host_stop(struct ata_host_set *host_set)
329 {
330 struct pdc_host_priv *hp = host_set->private_data;
331
332 ata_pci_host_stop(host_set);
333
334 kfree(hp);
335 }
336
337
338 static void pdc_reset_port(struct ata_port *ap)
339 {
340 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
341 unsigned int i;
342 u32 tmp;
343
344 for (i = 11; i > 0; i--) {
345 tmp = readl(mmio);
346 if (tmp & PDC_RESET)
347 break;
348
349 udelay(100);
350
351 tmp |= PDC_RESET;
352 writel(tmp, mmio);
353 }
354
355 tmp &= ~PDC_RESET;
356 writel(tmp, mmio);
357 readl(mmio); /* flush */
358 }
359
360 static void pdc_sata_phy_reset(struct ata_port *ap)
361 {
362 pdc_reset_port(ap);
363 sata_phy_reset(ap);
364 }
365
366 static void pdc_pata_phy_reset(struct ata_port *ap)
367 {
368 /* FIXME: add cable detect. Don't assume 40-pin cable */
369 ap->cbl = ATA_CBL_PATA40;
370 ap->udma_mask &= ATA_UDMA_MASK_40C;
371
372 pdc_reset_port(ap);
373 ata_port_probe(ap);
374 ata_bus_reset(ap);
375 }
376
377 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
378 {
379 if (sc_reg > SCR_CONTROL)
380 return 0xffffffffU;
381 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
382 }
383
384
385 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
386 u32 val)
387 {
388 if (sc_reg > SCR_CONTROL)
389 return;
390 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
391 }
392
393 static void pdc_qc_prep(struct ata_queued_cmd *qc)
394 {
395 struct pdc_port_priv *pp = qc->ap->private_data;
396 unsigned int i;
397
398 VPRINTK("ENTER\n");
399
400 switch (qc->tf.protocol) {
401 case ATA_PROT_DMA:
402 ata_qc_prep(qc);
403 /* fall through */
404
405 case ATA_PROT_NODATA:
406 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
407 qc->dev->devno, pp->pkt);
408
409 if (qc->tf.flags & ATA_TFLAG_LBA48)
410 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
411 else
412 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
413
414 pdc_pkt_footer(&qc->tf, pp->pkt, i);
415 break;
416
417 default:
418 break;
419 }
420 }
421
422 static void pdc_eng_timeout(struct ata_port *ap)
423 {
424 struct ata_host_set *host_set = ap->host_set;
425 u8 drv_stat;
426 struct ata_queued_cmd *qc;
427 unsigned long flags;
428
429 DPRINTK("ENTER\n");
430
431 spin_lock_irqsave(&host_set->lock, flags);
432
433 qc = ata_qc_from_tag(ap, ap->active_tag);
434
435 switch (qc->tf.protocol) {
436 case ATA_PROT_DMA:
437 case ATA_PROT_NODATA:
438 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
439 drv_stat = ata_wait_idle(ap);
440 qc->err_mask |= __ac_err_mask(drv_stat);
441 break;
442
443 default:
444 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
445
446 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
447 ap->id, qc->tf.command, drv_stat);
448
449 qc->err_mask |= ac_err_mask(drv_stat);
450 break;
451 }
452
453 spin_unlock_irqrestore(&host_set->lock, flags);
454 ata_eh_qc_complete(qc);
455 DPRINTK("EXIT\n");
456 }
457
458 static inline unsigned int pdc_host_intr( struct ata_port *ap,
459 struct ata_queued_cmd *qc)
460 {
461 unsigned int handled = 0;
462 u32 tmp;
463 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
464
465 tmp = readl(mmio);
466 if (tmp & PDC_ERR_MASK) {
467 qc->err_mask |= AC_ERR_DEV;
468 pdc_reset_port(ap);
469 }
470
471 switch (qc->tf.protocol) {
472 case ATA_PROT_DMA:
473 case ATA_PROT_NODATA:
474 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
475 ata_qc_complete(qc);
476 handled = 1;
477 break;
478
479 default:
480 ap->stats.idle_irq++;
481 break;
482 }
483
484 return handled;
485 }
486
487 static void pdc_irq_clear(struct ata_port *ap)
488 {
489 struct ata_host_set *host_set = ap->host_set;
490 void __iomem *mmio = host_set->mmio_base;
491
492 readl(mmio + PDC_INT_SEQMASK);
493 }
494
495 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
496 {
497 struct ata_host_set *host_set = dev_instance;
498 struct ata_port *ap;
499 u32 mask = 0;
500 unsigned int i, tmp;
501 unsigned int handled = 0;
502 void __iomem *mmio_base;
503
504 VPRINTK("ENTER\n");
505
506 if (!host_set || !host_set->mmio_base) {
507 VPRINTK("QUICK EXIT\n");
508 return IRQ_NONE;
509 }
510
511 mmio_base = host_set->mmio_base;
512
513 /* reading should also clear interrupts */
514 mask = readl(mmio_base + PDC_INT_SEQMASK);
515
516 if (mask == 0xffffffff) {
517 VPRINTK("QUICK EXIT 2\n");
518 return IRQ_NONE;
519 }
520
521 spin_lock(&host_set->lock);
522
523 mask &= 0xffff; /* only 16 tags possible */
524 if (!mask) {
525 VPRINTK("QUICK EXIT 3\n");
526 goto done_irq;
527 }
528
529 writel(mask, mmio_base + PDC_INT_SEQMASK);
530
531 for (i = 0; i < host_set->n_ports; i++) {
532 VPRINTK("port %u\n", i);
533 ap = host_set->ports[i];
534 tmp = mask & (1 << (i + 1));
535 if (tmp && ap &&
536 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
537 struct ata_queued_cmd *qc;
538
539 qc = ata_qc_from_tag(ap, ap->active_tag);
540 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
541 handled += pdc_host_intr(ap, qc);
542 }
543 }
544
545 VPRINTK("EXIT\n");
546
547 done_irq:
548 spin_unlock(&host_set->lock);
549 return IRQ_RETVAL(handled);
550 }
551
552 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
553 {
554 struct ata_port *ap = qc->ap;
555 struct pdc_port_priv *pp = ap->private_data;
556 unsigned int port_no = ap->port_no;
557 u8 seq = (u8) (port_no + 1);
558
559 VPRINTK("ENTER, ap %p\n", ap);
560
561 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
562 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
563
564 pp->pkt[2] = seq;
565 wmb(); /* flush PRD, pkt writes */
566 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
567 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
568 }
569
570 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
571 {
572 switch (qc->tf.protocol) {
573 case ATA_PROT_DMA:
574 case ATA_PROT_NODATA:
575 pdc_packet_start(qc);
576 return 0;
577
578 case ATA_PROT_ATAPI_DMA:
579 BUG();
580 break;
581
582 default:
583 break;
584 }
585
586 return ata_qc_issue_prot(qc);
587 }
588
589 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
590 {
591 WARN_ON (tf->protocol == ATA_PROT_DMA ||
592 tf->protocol == ATA_PROT_NODATA);
593 ata_tf_load(ap, tf);
594 }
595
596
597 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
598 {
599 WARN_ON (tf->protocol == ATA_PROT_DMA ||
600 tf->protocol == ATA_PROT_NODATA);
601 ata_exec_command(ap, tf);
602 }
603
604
605 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
606 {
607 port->cmd_addr = base;
608 port->data_addr = base;
609 port->feature_addr =
610 port->error_addr = base + 0x4;
611 port->nsect_addr = base + 0x8;
612 port->lbal_addr = base + 0xc;
613 port->lbam_addr = base + 0x10;
614 port->lbah_addr = base + 0x14;
615 port->device_addr = base + 0x18;
616 port->command_addr =
617 port->status_addr = base + 0x1c;
618 port->altstatus_addr =
619 port->ctl_addr = base + 0x38;
620 }
621
622
623 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
624 {
625 void __iomem *mmio = pe->mmio_base;
626 struct pdc_host_priv *hp = pe->private_data;
627 int hotplug_offset = hp->hotplug_offset;
628 u32 tmp;
629
630 /*
631 * Except for the hotplug stuff, this is voodoo from the
632 * Promise driver. Label this entire section
633 * "TODO: figure out why we do this"
634 */
635
636 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
637 tmp = readl(mmio + PDC_FLASH_CTL);
638 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
639 writel(tmp, mmio + PDC_FLASH_CTL);
640
641 /* clear plug/unplug flags for all ports */
642 tmp = readl(mmio + hotplug_offset);
643 writel(tmp | 0xff, mmio + hotplug_offset);
644
645 /* mask plug/unplug ints */
646 tmp = readl(mmio + hotplug_offset);
647 writel(tmp | 0xff0000, mmio + hotplug_offset);
648
649 /* reduce TBG clock to 133 Mhz. */
650 tmp = readl(mmio + PDC_TBG_MODE);
651 tmp &= ~0x30000; /* clear bit 17, 16*/
652 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
653 writel(tmp, mmio + PDC_TBG_MODE);
654
655 readl(mmio + PDC_TBG_MODE); /* flush */
656 msleep(10);
657
658 /* adjust slew rate control register. */
659 tmp = readl(mmio + PDC_SLEW_CTL);
660 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
661 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
662 writel(tmp, mmio + PDC_SLEW_CTL);
663 }
664
665 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
666 {
667 static int printed_version;
668 struct ata_probe_ent *probe_ent = NULL;
669 struct pdc_host_priv *hp;
670 unsigned long base;
671 void __iomem *mmio_base;
672 unsigned int board_idx = (unsigned int) ent->driver_data;
673 int pci_dev_busy = 0;
674 int rc;
675
676 if (!printed_version++)
677 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
678
679 /*
680 * If this driver happens to only be useful on Apple's K2, then
681 * we should check that here as it has a normal Serverworks ID
682 */
683 rc = pci_enable_device(pdev);
684 if (rc)
685 return rc;
686
687 rc = pci_request_regions(pdev, DRV_NAME);
688 if (rc) {
689 pci_dev_busy = 1;
690 goto err_out;
691 }
692
693 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
694 if (rc)
695 goto err_out_regions;
696 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
697 if (rc)
698 goto err_out_regions;
699
700 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
701 if (probe_ent == NULL) {
702 rc = -ENOMEM;
703 goto err_out_regions;
704 }
705
706 probe_ent->dev = pci_dev_to_dev(pdev);
707 INIT_LIST_HEAD(&probe_ent->node);
708
709 mmio_base = pci_iomap(pdev, 3, 0);
710 if (mmio_base == NULL) {
711 rc = -ENOMEM;
712 goto err_out_free_ent;
713 }
714 base = (unsigned long) mmio_base;
715
716 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
717 if (hp == NULL) {
718 rc = -ENOMEM;
719 goto err_out_free_ent;
720 }
721
722 /* Set default hotplug offset */
723 hp->hotplug_offset = PDC_SATA_PLUG_CSR;
724 probe_ent->private_data = hp;
725
726 probe_ent->sht = pdc_port_info[board_idx].sht;
727 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
728 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
729 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
730 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
731 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
732
733 probe_ent->irq = pdev->irq;
734 probe_ent->irq_flags = SA_SHIRQ;
735 probe_ent->mmio_base = mmio_base;
736
737 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
738 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
739
740 probe_ent->port[0].scr_addr = base + 0x400;
741 probe_ent->port[1].scr_addr = base + 0x500;
742
743 /* notice 4-port boards */
744 switch (board_idx) {
745 case board_40518:
746 /* Override hotplug offset for SATAII150 */
747 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
748 /* Fall through */
749 case board_20319:
750 probe_ent->n_ports = 4;
751
752 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
753 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
754
755 probe_ent->port[2].scr_addr = base + 0x600;
756 probe_ent->port[3].scr_addr = base + 0x700;
757 break;
758 case board_2057x:
759 /* Override hotplug offset for SATAII150 */
760 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
761 /* Fall through */
762 case board_2037x:
763 probe_ent->n_ports = 2;
764 break;
765 case board_20771:
766 probe_ent->n_ports = 2;
767 break;
768 case board_20619:
769 probe_ent->n_ports = 4;
770
771 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
772 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
773
774 probe_ent->port[2].scr_addr = base + 0x600;
775 probe_ent->port[3].scr_addr = base + 0x700;
776 break;
777 default:
778 BUG();
779 break;
780 }
781
782 pci_set_master(pdev);
783
784 /* initialize adapter */
785 pdc_host_init(board_idx, probe_ent);
786
787 /* FIXME: Need any other frees than hp? */
788 if (!ata_device_add(probe_ent))
789 kfree(hp);
790
791 kfree(probe_ent);
792
793 return 0;
794
795 err_out_free_ent:
796 kfree(probe_ent);
797 err_out_regions:
798 pci_release_regions(pdev);
799 err_out:
800 if (!pci_dev_busy)
801 pci_disable_device(pdev);
802 return rc;
803 }
804
805
806 static int __init pdc_ata_init(void)
807 {
808 return pci_module_init(&pdc_ata_pci_driver);
809 }
810
811
812 static void __exit pdc_ata_exit(void)
813 {
814 pci_unregister_driver(&pdc_ata_pci_driver);
815 }
816
817
818 MODULE_AUTHOR("Jeff Garzik");
819 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
820 MODULE_LICENSE("GPL");
821 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
822 MODULE_VERSION(DRV_VERSION);
823
824 module_init(pdc_ata_init);
825 module_exit(pdc_ata_exit);
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