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USB: SisUSB2VGA: Whitespace Cleanups
[linux-2.6/openmoko-kernel.git] / drivers / ata / pata_sis.c
blobcce2834b2b60990140071be8ad10ec3fbcee2b84
1 /*
2 * pata_sis.c - SiS ATA driver
3 *
4 * (C) 2005 Red Hat <alan@redhat.com>
5 * (C) 2007 Bartlomiej Zolnierkiewicz
6 *
7 * Based upon linux/drivers/ide/pci/sis5513.c
8 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
9 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
10 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
11 * SiS Taiwan : for direct support and hardware.
12 * Daniela Engert : for initial ATA100 advices and numerous others.
13 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
14 * for checking code correctness, providing patches.
15 * Original tests and design on the SiS620 chipset.
16 * ATA100 tests and design on the SiS735 chipset.
17 * ATA16/33 support from specs
18 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
19 *
20 *
21 * TODO
22 * Check MWDMA on drives that don't support MWDMA speed pio cycles ?
23 * More Testing
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/blkdev.h>
31 #include <linux/delay.h>
32 #include <linux/device.h>
33 #include <scsi/scsi_host.h>
34 #include <linux/libata.h>
35 #include <linux/ata.h>
36 #include "sis.h"
37
38 #define DRV_NAME "pata_sis"
39 #define DRV_VERSION "0.5.2"
40
41 struct sis_chipset {
42 u16 device; /* PCI host ID */
43 const struct ata_port_info *info; /* Info block */
44 /* Probably add family, cable detect type etc here to clean
45 up code later */
46 };
47
48 struct sis_laptop {
49 u16 device;
50 u16 subvendor;
51 u16 subdevice;
52 };
53
54 static const struct sis_laptop sis_laptop[] = {
55 /* devid, subvendor, subdev */
56 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
57 { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */
58 /* end marker */
59 { 0, }
60 };
61
62 static int sis_short_ata40(struct pci_dev *dev)
63 {
64 const struct sis_laptop *lap = &sis_laptop[0];
65
66 while (lap->device) {
67 if (lap->device == dev->device &&
68 lap->subvendor == dev->subsystem_vendor &&
69 lap->subdevice == dev->subsystem_device)
70 return 1;
71 lap++;
72 }
73
74 return 0;
75 }
76
77 /**
78 * sis_old_port_base - return PCI configuration base for dev
79 * @adev: device
80 *
81 * Returns the base of the PCI configuration registers for this port
82 * number.
83 */
84
85 static int sis_old_port_base(struct ata_device *adev)
86 {
87 return 0x40 + (4 * adev->ap->port_no) + (2 * adev->devno);
88 }
89
90 /**
91 * sis_133_cable_detect - check for 40/80 pin
92 * @ap: Port
93 * @deadline: deadline jiffies for the operation
94 *
95 * Perform cable detection for the later UDMA133 capable
96 * SiS chipset.
97 */
98
99 static int sis_133_cable_detect(struct ata_port *ap)
100 {
101 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
102 u16 tmp;
103
104 /* The top bit of this register is the cable detect bit */
105 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
106 if ((tmp & 0x8000) && !sis_short_ata40(pdev))
107 return ATA_CBL_PATA40;
108 return ATA_CBL_PATA80;
109 }
110
111 /**
112 * sis_66_cable_detect - check for 40/80 pin
113 * @ap: Port
114 * @deadline: deadline jiffies for the operation
115 *
116 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133
117 * SiS IDE controllers.
118 */
119
120 static int sis_66_cable_detect(struct ata_port *ap)
121 {
122 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
123 u8 tmp;
124
125 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */
126 pci_read_config_byte(pdev, 0x48, &tmp);
127 tmp >>= ap->port_no;
128 if ((tmp & 0x10) && !sis_short_ata40(pdev))
129 return ATA_CBL_PATA40;
130 return ATA_CBL_PATA80;
131 }
132
133
134 /**
135 * sis_pre_reset - probe begin
136 * @ap: ATA port
137 * @deadline: deadline jiffies for the operation
138 *
139 * Set up cable type and use generic probe init
140 */
141
142 static int sis_pre_reset(struct ata_port *ap, unsigned long deadline)
143 {
144 static const struct pci_bits sis_enable_bits[] = {
145 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
146 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
147 };
148
149 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
150
151 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
152 return -ENOENT;
153
154 /* Clear the FIFO settings. We can't enable the FIFO until
155 we know we are poking at a disk */
156 pci_write_config_byte(pdev, 0x4B, 0);
157 return ata_std_prereset(ap, deadline);
158 }
159
160
161 /**
162 * sis_error_handler - Probe specified port on PATA host controller
163 * @ap: Port to probe
164 *
165 * LOCKING:
166 * None (inherited from caller).
167 */
168
169 static void sis_error_handler(struct ata_port *ap)
170 {
171 ata_bmdma_drive_eh(ap, sis_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
172 }
173
174 /**
175 * sis_set_fifo - Set RWP fifo bits for this device
176 * @ap: Port
177 * @adev: Device
178 *
179 * SIS chipsets implement prefetch/postwrite bits for each device
180 * on both channels. This functionality is not ATAPI compatible and
181 * must be configured according to the class of device present
182 */
183
184 static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
185 {
186 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
187 u8 fifoctrl;
188 u8 mask = 0x11;
189
190 mask <<= (2 * ap->port_no);
191 mask <<= adev->devno;
192
193 /* This holds various bits including the FIFO control */
194 pci_read_config_byte(pdev, 0x4B, &fifoctrl);
195 fifoctrl &= ~mask;
196
197 /* Enable for ATA (disk) only */
198 if (adev->class == ATA_DEV_ATA)
199 fifoctrl |= mask;
200 pci_write_config_byte(pdev, 0x4B, fifoctrl);
201 }
202
203 /**
204 * sis_old_set_piomode - Initialize host controller PATA PIO timings
205 * @ap: Port whose timings we are configuring
206 * @adev: Device we are configuring for.
207 *
208 * Set PIO mode for device, in host controller PCI config space. This
209 * function handles PIO set up for all chips that are pre ATA100 and
210 * also early ATA100 devices.
211 *
212 * LOCKING:
213 * None (inherited from caller).
214 */
215
216 static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
217 {
218 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
219 int port = sis_old_port_base(adev);
220 u8 t1, t2;
221 int speed = adev->pio_mode - XFER_PIO_0;
222
223 const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
224 const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
225
226 sis_set_fifo(ap, adev);
227
228 pci_read_config_byte(pdev, port, &t1);
229 pci_read_config_byte(pdev, port + 1, &t2);
230
231 t1 &= ~0x0F; /* Clear active/recovery timings */
232 t2 &= ~0x07;
233
234 t1 |= active[speed];
235 t2 |= recovery[speed];
236
237 pci_write_config_byte(pdev, port, t1);
238 pci_write_config_byte(pdev, port + 1, t2);
239 }
240
241 /**
242 * sis_100_set_piomode - Initialize host controller PATA PIO timings
243 * @ap: Port whose timings we are configuring
244 * @adev: Device we are configuring for.
245 *
246 * Set PIO mode for device, in host controller PCI config space. This
247 * function handles PIO set up for ATA100 devices and early ATA133.
248 *
249 * LOCKING:
250 * None (inherited from caller).
251 */
252
253 static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
254 {
255 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
256 int port = sis_old_port_base(adev);
257 int speed = adev->pio_mode - XFER_PIO_0;
258
259 const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
260
261 sis_set_fifo(ap, adev);
262
263 pci_write_config_byte(pdev, port, actrec[speed]);
264 }
265
266 /**
267 * sis_133_set_piomode - Initialize host controller PATA PIO timings
268 * @ap: Port whose timings we are configuring
269 * @adev: Device we are configuring for.
270 *
271 * Set PIO mode for device, in host controller PCI config space. This
272 * function handles PIO set up for the later ATA133 devices.
273 *
274 * LOCKING:
275 * None (inherited from caller).
276 */
277
278 static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
279 {
280 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
281 int port = 0x40;
282 u32 t1;
283 u32 reg54;
284 int speed = adev->pio_mode - XFER_PIO_0;
285
286 const u32 timing133[] = {
287 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
288 0x0C266000,
289 0x04263000,
290 0x0C0A3000,
291 0x05093000
292 };
293 const u32 timing100[] = {
294 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
295 0x091C4000,
296 0x031C2000,
297 0x09072000,
298 0x04062000
299 };
300
301 sis_set_fifo(ap, adev);
302
303 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
304 pci_read_config_dword(pdev, 0x54, &reg54);
305 if (reg54 & 0x40000000)
306 port = 0x70;
307 port += 8 * ap->port_no + 4 * adev->devno;
308
309 pci_read_config_dword(pdev, port, &t1);
310 t1 &= 0xC0C00FFF; /* Mask out timing */
311
312 if (t1 & 0x08) /* 100 or 133 ? */
313 t1 |= timing133[speed];
314 else
315 t1 |= timing100[speed];
316 pci_write_config_byte(pdev, port, t1);
317 }
318
319 /**
320 * sis_old_set_dmamode - Initialize host controller PATA DMA timings
321 * @ap: Port whose timings we are configuring
322 * @adev: Device to program
323 *
324 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
325 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
326 * the old ide/pci driver.
327 *
328 * LOCKING:
329 * None (inherited from caller).
330 */
331
332 static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
333 {
334 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
335 int speed = adev->dma_mode - XFER_MW_DMA_0;
336 int drive_pci = sis_old_port_base(adev);
337 u16 timing;
338
339 const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
340 const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
341
342 pci_read_config_word(pdev, drive_pci, &timing);
343
344 if (adev->dma_mode < XFER_UDMA_0) {
345 /* bits 3-0 hold recovery timing bits 8-10 active timing and
346 the higer bits are dependant on the device */
347 timing &= ~0x870F;
348 timing |= mwdma_bits[speed];
349 } else {
350 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
351 speed = adev->dma_mode - XFER_UDMA_0;
352 timing &= ~0x6000;
353 timing |= udma_bits[speed];
354 }
355 pci_write_config_word(pdev, drive_pci, timing);
356 }
357
358 /**
359 * sis_66_set_dmamode - Initialize host controller PATA DMA timings
360 * @ap: Port whose timings we are configuring
361 * @adev: Device to program
362 *
363 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
364 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
365 * the old ide/pci driver.
366 *
367 * LOCKING:
368 * None (inherited from caller).
369 */
370
371 static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
372 {
373 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
374 int speed = adev->dma_mode - XFER_MW_DMA_0;
375 int drive_pci = sis_old_port_base(adev);
376 u16 timing;
377
378 /* MWDMA 0-2 and UDMA 0-5 */
379 const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
380 const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 };
381
382 pci_read_config_word(pdev, drive_pci, &timing);
383
384 if (adev->dma_mode < XFER_UDMA_0) {
385 /* bits 3-0 hold recovery timing bits 8-10 active timing and
386 the higer bits are dependant on the device, bit 15 udma */
387 timing &= ~0x870F;
388 timing |= mwdma_bits[speed];
389 } else {
390 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
391 speed = adev->dma_mode - XFER_UDMA_0;
392 timing &= ~0xF000;
393 timing |= udma_bits[speed];
394 }
395 pci_write_config_word(pdev, drive_pci, timing);
396 }
397
398 /**
399 * sis_100_set_dmamode - Initialize host controller PATA DMA timings
400 * @ap: Port whose timings we are configuring
401 * @adev: Device to program
402 *
403 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
404 * Handles UDMA66 and early UDMA100 devices.
405 *
406 * LOCKING:
407 * None (inherited from caller).
408 */
409
410 static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
411 {
412 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
413 int speed = adev->dma_mode - XFER_MW_DMA_0;
414 int drive_pci = sis_old_port_base(adev);
415 u8 timing;
416
417 const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81};
418
419 pci_read_config_byte(pdev, drive_pci + 1, &timing);
420
421 if (adev->dma_mode < XFER_UDMA_0) {
422 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
423 } else {
424 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
425 speed = adev->dma_mode - XFER_UDMA_0;
426 timing &= ~0x8F;
427 timing |= udma_bits[speed];
428 }
429 pci_write_config_byte(pdev, drive_pci + 1, timing);
430 }
431
432 /**
433 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
434 * @ap: Port whose timings we are configuring
435 * @adev: Device to program
436 *
437 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
438 * Handles early SiS 961 bridges.
439 *
440 * LOCKING:
441 * None (inherited from caller).
442 */
443
444 static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
445 {
446 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
447 int speed = adev->dma_mode - XFER_MW_DMA_0;
448 int drive_pci = sis_old_port_base(adev);
449 u8 timing;
450 /* Low 4 bits are timing */
451 static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81};
452
453 pci_read_config_byte(pdev, drive_pci + 1, &timing);
454
455 if (adev->dma_mode < XFER_UDMA_0) {
456 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
457 } else {
458 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
459 speed = adev->dma_mode - XFER_UDMA_0;
460 timing &= ~0x8F;
461 timing |= udma_bits[speed];
462 }
463 pci_write_config_byte(pdev, drive_pci + 1, timing);
464 }
465
466 /**
467 * sis_133_set_dmamode - Initialize host controller PATA DMA timings
468 * @ap: Port whose timings we are configuring
469 * @adev: Device to program
470 *
471 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
472 *
473 * LOCKING:
474 * None (inherited from caller).
475 */
476
477 static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
478 {
479 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
480 int speed = adev->dma_mode - XFER_MW_DMA_0;
481 int port = 0x40;
482 u32 t1;
483 u32 reg54;
484
485 /* bits 4- cycle time 8 - cvs time */
486 static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
487 static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
488
489 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
490 pci_read_config_dword(pdev, 0x54, &reg54);
491 if (reg54 & 0x40000000)
492 port = 0x70;
493 port += (8 * ap->port_no) + (4 * adev->devno);
494
495 pci_read_config_dword(pdev, port, &t1);
496
497 if (adev->dma_mode < XFER_UDMA_0) {
498 t1 &= ~0x00000004;
499 /* FIXME: need data sheet to add MWDMA here. Also lacking on
500 ide/pci driver */
501 } else {
502 speed = adev->dma_mode - XFER_UDMA_0;
503 /* if & 8 no UDMA133 - need info for ... */
504 t1 &= ~0x00000FF0;
505 t1 |= 0x00000004;
506 if (t1 & 0x08)
507 t1 |= timing_u133[speed];
508 else
509 t1 |= timing_u100[speed];
510 }
511 pci_write_config_dword(pdev, port, t1);
512 }
513
514 static struct scsi_host_template sis_sht = {
515 .module = THIS_MODULE,
516 .name = DRV_NAME,
517 .ioctl = ata_scsi_ioctl,
518 .queuecommand = ata_scsi_queuecmd,
519 .can_queue = ATA_DEF_QUEUE,
520 .this_id = ATA_SHT_THIS_ID,
521 .sg_tablesize = LIBATA_MAX_PRD,
522 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
523 .emulated = ATA_SHT_EMULATED,
524 .use_clustering = ATA_SHT_USE_CLUSTERING,
525 .proc_name = DRV_NAME,
526 .dma_boundary = ATA_DMA_BOUNDARY,
527 .slave_configure = ata_scsi_slave_config,
528 .slave_destroy = ata_scsi_slave_destroy,
529 .bios_param = ata_std_bios_param,
530 };
531
532 static const struct ata_port_operations sis_133_ops = {
533 .port_disable = ata_port_disable,
534 .set_piomode = sis_133_set_piomode,
535 .set_dmamode = sis_133_set_dmamode,
536 .mode_filter = ata_pci_default_filter,
537
538 .tf_load = ata_tf_load,
539 .tf_read = ata_tf_read,
540 .check_status = ata_check_status,
541 .exec_command = ata_exec_command,
542 .dev_select = ata_std_dev_select,
543
544 .freeze = ata_bmdma_freeze,
545 .thaw = ata_bmdma_thaw,
546 .error_handler = sis_error_handler,
547 .post_internal_cmd = ata_bmdma_post_internal_cmd,
548 .cable_detect = sis_133_cable_detect,
549
550 .bmdma_setup = ata_bmdma_setup,
551 .bmdma_start = ata_bmdma_start,
552 .bmdma_stop = ata_bmdma_stop,
553 .bmdma_status = ata_bmdma_status,
554 .qc_prep = ata_qc_prep,
555 .qc_issue = ata_qc_issue_prot,
556 .data_xfer = ata_data_xfer,
557
558 .irq_handler = ata_interrupt,
559 .irq_clear = ata_bmdma_irq_clear,
560 .irq_on = ata_irq_on,
561 .irq_ack = ata_irq_ack,
562
563 .port_start = ata_port_start,
564 };
565
566 static const struct ata_port_operations sis_133_for_sata_ops = {
567 .port_disable = ata_port_disable,
568 .set_piomode = sis_133_set_piomode,
569 .set_dmamode = sis_133_set_dmamode,
570 .mode_filter = ata_pci_default_filter,
571
572 .tf_load = ata_tf_load,
573 .tf_read = ata_tf_read,
574 .check_status = ata_check_status,
575 .exec_command = ata_exec_command,
576 .dev_select = ata_std_dev_select,
577
578 .freeze = ata_bmdma_freeze,
579 .thaw = ata_bmdma_thaw,
580 .error_handler = ata_bmdma_error_handler,
581 .post_internal_cmd = ata_bmdma_post_internal_cmd,
582 .cable_detect = sis_133_cable_detect,
583
584 .bmdma_setup = ata_bmdma_setup,
585 .bmdma_start = ata_bmdma_start,
586 .bmdma_stop = ata_bmdma_stop,
587 .bmdma_status = ata_bmdma_status,
588 .qc_prep = ata_qc_prep,
589 .qc_issue = ata_qc_issue_prot,
590 .data_xfer = ata_data_xfer,
591
592 .irq_handler = ata_interrupt,
593 .irq_clear = ata_bmdma_irq_clear,
594 .irq_on = ata_irq_on,
595 .irq_ack = ata_irq_ack,
596
597 .port_start = ata_port_start,
598 };
599
600 static const struct ata_port_operations sis_133_early_ops = {
601 .port_disable = ata_port_disable,
602 .set_piomode = sis_100_set_piomode,
603 .set_dmamode = sis_133_early_set_dmamode,
604 .mode_filter = ata_pci_default_filter,
605
606 .tf_load = ata_tf_load,
607 .tf_read = ata_tf_read,
608 .check_status = ata_check_status,
609 .exec_command = ata_exec_command,
610 .dev_select = ata_std_dev_select,
611
612 .freeze = ata_bmdma_freeze,
613 .thaw = ata_bmdma_thaw,
614 .error_handler = sis_error_handler,
615 .post_internal_cmd = ata_bmdma_post_internal_cmd,
616 .cable_detect = sis_66_cable_detect,
617
618 .bmdma_setup = ata_bmdma_setup,
619 .bmdma_start = ata_bmdma_start,
620 .bmdma_stop = ata_bmdma_stop,
621 .bmdma_status = ata_bmdma_status,
622 .qc_prep = ata_qc_prep,
623 .qc_issue = ata_qc_issue_prot,
624 .data_xfer = ata_data_xfer,
625
626 .irq_handler = ata_interrupt,
627 .irq_clear = ata_bmdma_irq_clear,
628 .irq_on = ata_irq_on,
629 .irq_ack = ata_irq_ack,
630
631 .port_start = ata_port_start,
632 };
633
634 static const struct ata_port_operations sis_100_ops = {
635 .port_disable = ata_port_disable,
636 .set_piomode = sis_100_set_piomode,
637 .set_dmamode = sis_100_set_dmamode,
638 .mode_filter = ata_pci_default_filter,
639
640 .tf_load = ata_tf_load,
641 .tf_read = ata_tf_read,
642 .check_status = ata_check_status,
643 .exec_command = ata_exec_command,
644 .dev_select = ata_std_dev_select,
645
646 .freeze = ata_bmdma_freeze,
647 .thaw = ata_bmdma_thaw,
648 .error_handler = sis_error_handler,
649 .post_internal_cmd = ata_bmdma_post_internal_cmd,
650 .cable_detect = sis_66_cable_detect,
651
652 .bmdma_setup = ata_bmdma_setup,
653 .bmdma_start = ata_bmdma_start,
654 .bmdma_stop = ata_bmdma_stop,
655 .bmdma_status = ata_bmdma_status,
656 .qc_prep = ata_qc_prep,
657 .qc_issue = ata_qc_issue_prot,
658 .data_xfer = ata_data_xfer,
659
660 .irq_handler = ata_interrupt,
661 .irq_clear = ata_bmdma_irq_clear,
662 .irq_on = ata_irq_on,
663 .irq_ack = ata_irq_ack,
664
665 .port_start = ata_port_start,
666 };
667
668 static const struct ata_port_operations sis_66_ops = {
669 .port_disable = ata_port_disable,
670 .set_piomode = sis_old_set_piomode,
671 .set_dmamode = sis_66_set_dmamode,
672 .mode_filter = ata_pci_default_filter,
673
674 .tf_load = ata_tf_load,
675 .tf_read = ata_tf_read,
676 .check_status = ata_check_status,
677 .exec_command = ata_exec_command,
678 .dev_select = ata_std_dev_select,
679 .cable_detect = sis_66_cable_detect,
680
681 .freeze = ata_bmdma_freeze,
682 .thaw = ata_bmdma_thaw,
683 .error_handler = sis_error_handler,
684 .post_internal_cmd = ata_bmdma_post_internal_cmd,
685
686 .bmdma_setup = ata_bmdma_setup,
687 .bmdma_start = ata_bmdma_start,
688 .bmdma_stop = ata_bmdma_stop,
689 .bmdma_status = ata_bmdma_status,
690 .qc_prep = ata_qc_prep,
691 .qc_issue = ata_qc_issue_prot,
692 .data_xfer = ata_data_xfer,
693
694 .irq_handler = ata_interrupt,
695 .irq_clear = ata_bmdma_irq_clear,
696 .irq_on = ata_irq_on,
697 .irq_ack = ata_irq_ack,
698
699 .port_start = ata_port_start,
700 };
701
702 static const struct ata_port_operations sis_old_ops = {
703 .port_disable = ata_port_disable,
704 .set_piomode = sis_old_set_piomode,
705 .set_dmamode = sis_old_set_dmamode,
706 .mode_filter = ata_pci_default_filter,
707
708 .tf_load = ata_tf_load,
709 .tf_read = ata_tf_read,
710 .check_status = ata_check_status,
711 .exec_command = ata_exec_command,
712 .dev_select = ata_std_dev_select,
713
714 .freeze = ata_bmdma_freeze,
715 .thaw = ata_bmdma_thaw,
716 .error_handler = sis_error_handler,
717 .post_internal_cmd = ata_bmdma_post_internal_cmd,
718 .cable_detect = ata_cable_40wire,
719
720 .bmdma_setup = ata_bmdma_setup,
721 .bmdma_start = ata_bmdma_start,
722 .bmdma_stop = ata_bmdma_stop,
723 .bmdma_status = ata_bmdma_status,
724 .qc_prep = ata_qc_prep,
725 .qc_issue = ata_qc_issue_prot,
726 .data_xfer = ata_data_xfer,
727
728 .irq_handler = ata_interrupt,
729 .irq_clear = ata_bmdma_irq_clear,
730 .irq_on = ata_irq_on,
731 .irq_ack = ata_irq_ack,
732
733 .port_start = ata_port_start,
734 };
735
736 static const struct ata_port_info sis_info = {
737 .sht = &sis_sht,
738 .flags = ATA_FLAG_SLAVE_POSS,
739 .pio_mask = 0x1f, /* pio0-4 */
740 .mwdma_mask = 0x07,
741 .udma_mask = 0,
742 .port_ops = &sis_old_ops,
743 };
744 static const struct ata_port_info sis_info33 = {
745 .sht = &sis_sht,
746 .flags = ATA_FLAG_SLAVE_POSS,
747 .pio_mask = 0x1f, /* pio0-4 */
748 .mwdma_mask = 0x07,
749 .udma_mask = ATA_UDMA2, /* UDMA 33 */
750 .port_ops = &sis_old_ops,
751 };
752 static const struct ata_port_info sis_info66 = {
753 .sht = &sis_sht,
754 .flags = ATA_FLAG_SLAVE_POSS,
755 .pio_mask = 0x1f, /* pio0-4 */
756 .udma_mask = ATA_UDMA4, /* UDMA 66 */
757 .port_ops = &sis_66_ops,
758 };
759 static const struct ata_port_info sis_info100 = {
760 .sht = &sis_sht,
761 .flags = ATA_FLAG_SLAVE_POSS,
762 .pio_mask = 0x1f, /* pio0-4 */
763 .udma_mask = ATA_UDMA5,
764 .port_ops = &sis_100_ops,
765 };
766 static const struct ata_port_info sis_info100_early = {
767 .sht = &sis_sht,
768 .flags = ATA_FLAG_SLAVE_POSS,
769 .udma_mask = ATA_UDMA5,
770 .pio_mask = 0x1f, /* pio0-4 */
771 .port_ops = &sis_66_ops,
772 };
773 static const struct ata_port_info sis_info133 = {
774 .sht = &sis_sht,
775 .flags = ATA_FLAG_SLAVE_POSS,
776 .pio_mask = 0x1f, /* pio0-4 */
777 .udma_mask = ATA_UDMA6,
778 .port_ops = &sis_133_ops,
779 };
780 const struct ata_port_info sis_info133_for_sata = {
781 .sht = &sis_sht,
782 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
783 .pio_mask = 0x1f, /* pio0-4 */
784 .udma_mask = ATA_UDMA6,
785 .port_ops = &sis_133_for_sata_ops,
786 };
787 static const struct ata_port_info sis_info133_early = {
788 .sht = &sis_sht,
789 .flags = ATA_FLAG_SLAVE_POSS,
790 .pio_mask = 0x1f, /* pio0-4 */
791 .udma_mask = ATA_UDMA6,
792 .port_ops = &sis_133_early_ops,
793 };
794
795 /* Privately shared with the SiS180 SATA driver, not for use elsewhere */
796 EXPORT_SYMBOL_GPL(sis_info133_for_sata);
797
798 static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
799 {
800 u16 regw;
801 u8 reg;
802
803 if (sis->info == &sis_info133) {
804 pci_read_config_word(pdev, 0x50, &regw);
805 if (regw & 0x08)
806 pci_write_config_word(pdev, 0x50, regw & ~0x08);
807 pci_read_config_word(pdev, 0x52, &regw);
808 if (regw & 0x08)
809 pci_write_config_word(pdev, 0x52, regw & ~0x08);
810 return;
811 }
812
813 if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
814 /* Fix up latency */
815 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
816 /* Set compatibility bit */
817 pci_read_config_byte(pdev, 0x49, &reg);
818 if (!(reg & 0x01))
819 pci_write_config_byte(pdev, 0x49, reg | 0x01);
820 return;
821 }
822
823 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
824 /* Fix up latency */
825 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
826 /* Set compatibility bit */
827 pci_read_config_byte(pdev, 0x52, &reg);
828 if (!(reg & 0x04))
829 pci_write_config_byte(pdev, 0x52, reg | 0x04);
830 return;
831 }
832
833 if (sis->info == &sis_info33) {
834 pci_read_config_byte(pdev, PCI_CLASS_PROG, &reg);
835 if (( reg & 0x0F ) != 0x00)
836 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
837 /* Fall through to ATA16 fixup below */
838 }
839
840 if (sis->info == &sis_info || sis->info == &sis_info33) {
841 /* force per drive recovery and active timings
842 needed on ATA_33 and below chips */
843 pci_read_config_byte(pdev, 0x52, &reg);
844 if (!(reg & 0x08))
845 pci_write_config_byte(pdev, 0x52, reg|0x08);
846 return;
847 }
848
849 BUG();
850 }
851
852 /**
853 * sis_init_one - Register SiS ATA PCI device with kernel services
854 * @pdev: PCI device to register
855 * @ent: Entry in sis_pci_tbl matching with @pdev
856 *
857 * Called from kernel PCI layer. We probe for combined mode (sigh),
858 * and then hand over control to libata, for it to do the rest.
859 *
860 * LOCKING:
861 * Inherited from PCI layer (may sleep).
862 *
863 * RETURNS:
864 * Zero on success, or -ERRNO value.
865 */
866
867 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
868 {
869 static int printed_version;
870 struct ata_port_info port;
871 const struct ata_port_info *ppi[] = { &port, NULL };
872 struct pci_dev *host = NULL;
873 struct sis_chipset *chipset = NULL;
874 struct sis_chipset *sets;
875
876 static struct sis_chipset sis_chipsets[] = {
877
878 { 0x0968, &sis_info133 },
879 { 0x0966, &sis_info133 },
880 { 0x0965, &sis_info133 },
881 { 0x0745, &sis_info100 },
882 { 0x0735, &sis_info100 },
883 { 0x0733, &sis_info100 },
884 { 0x0635, &sis_info100 },
885 { 0x0633, &sis_info100 },
886
887 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
888 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
889
890 { 0x0640, &sis_info66 },
891 { 0x0630, &sis_info66 },
892 { 0x0620, &sis_info66 },
893 { 0x0540, &sis_info66 },
894 { 0x0530, &sis_info66 },
895
896 { 0x5600, &sis_info33 },
897 { 0x5598, &sis_info33 },
898 { 0x5597, &sis_info33 },
899 { 0x5591, &sis_info33 },
900 { 0x5582, &sis_info33 },
901 { 0x5581, &sis_info33 },
902
903 { 0x5596, &sis_info },
904 { 0x5571, &sis_info },
905 { 0x5517, &sis_info },
906 { 0x5511, &sis_info },
907
908 {0}
909 };
910 static struct sis_chipset sis133_early = {
911 0x0, &sis_info133_early
912 };
913 static struct sis_chipset sis133 = {
914 0x0, &sis_info133
915 };
916 static struct sis_chipset sis100_early = {
917 0x0, &sis_info100_early
918 };
919 static struct sis_chipset sis100 = {
920 0x0, &sis_info100
921 };
922
923 if (!printed_version++)
924 dev_printk(KERN_DEBUG, &pdev->dev,
925 "version " DRV_VERSION "\n");
926
927 /* We have to find the bridge first */
928
929 for (sets = &sis_chipsets[0]; sets->device; sets++) {
930 host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL);
931 if (host != NULL) {
932 chipset = sets; /* Match found */
933 if (sets->device == 0x630) { /* SIS630 */
934 if (host->revision >= 0x30) /* 630 ET */
935 chipset = &sis100_early;
936 }
937 break;
938 }
939 }
940
941 /* Look for concealed bridges */
942 if (chipset == NULL) {
943 /* Second check */
944 u32 idemisc;
945 u16 trueid;
946
947 /* Disable ID masking and register remapping then
948 see what the real ID is */
949
950 pci_read_config_dword(pdev, 0x54, &idemisc);
951 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
952 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
953 pci_write_config_dword(pdev, 0x54, idemisc);
954
955 switch(trueid) {
956 case 0x5518: /* SIS 962/963 */
957 chipset = &sis133;
958 if ((idemisc & 0x40000000) == 0) {
959 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
960 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
961 }
962 break;
963 case 0x0180: /* SIS 965/965L */
964 chipset = &sis133;
965 break;
966 case 0x1180: /* SIS 966/966L */
967 chipset = &sis133;
968 break;
969 }
970 }
971
972 /* Further check */
973 if (chipset == NULL) {
974 struct pci_dev *lpc_bridge;
975 u16 trueid;
976 u8 prefctl;
977 u8 idecfg;
978
979 /* Try the second unmasking technique */
980 pci_read_config_byte(pdev, 0x4a, &idecfg);
981 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
982 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
983 pci_write_config_byte(pdev, 0x4a, idecfg);
984
985 switch(trueid) {
986 case 0x5517:
987 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
988 if (lpc_bridge == NULL)
989 break;
990 pci_read_config_byte(pdev, 0x49, &prefctl);
991 pci_dev_put(lpc_bridge);
992
993 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
994 chipset = &sis133_early;
995 break;
996 }
997 chipset = &sis100;
998 break;
999 }
1000 }
1001 pci_dev_put(host);
1002
1003 /* No chipset info, no support */
1004 if (chipset == NULL)
1005 return -ENODEV;
1006
1007 port = *chipset->info;
1008 port.private_data = chipset;
1009
1010 sis_fixup(pdev, chipset);
1011
1012 return ata_pci_init_one(pdev, ppi);
1013 }
1014
1015 static const struct pci_device_id sis_pci_tbl[] = {
1016 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
1017 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
1018 { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */
1019
1020 { }
1021 };
1022
1023 static struct pci_driver sis_pci_driver = {
1024 .name = DRV_NAME,
1025 .id_table = sis_pci_tbl,
1026 .probe = sis_init_one,
1027 .remove = ata_pci_remove_one,
1028 #ifdef CONFIG_PM
1029 .suspend = ata_pci_device_suspend,
1030 .resume = ata_pci_device_resume,
1031 #endif
1032 };
1033
1034 static int __init sis_init(void)
1035 {
1036 return pci_register_driver(&sis_pci_driver);
1037 }
1038
1039 static void __exit sis_exit(void)
1040 {
1041 pci_unregister_driver(&sis_pci_driver);
1042 }
1043
1044 module_init(sis_init);
1045 module_exit(sis_exit);
1046
1047 MODULE_AUTHOR("Alan Cox");
1048 MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
1049 MODULE_LICENSE("GPL");
1050 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
1051 MODULE_VERSION(DRV_VERSION);
1052
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