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misc drivers/net endianness noise
[linux-2.6/openmoko-kernel.git] / drivers / serial / amba-pl011.c
blob08adc1de4a7953072d42209d47338a04b7de38cc
1 /*
2 * linux/drivers/char/amba.c
3 *
4 * Driver for AMBA serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
26 *
27 * This is a generic driver for ARM AMBA-type serial ports. They
28 * have a lot of 16550-like features, but are not register compatible.
29 * Note that although they do have CTS, DCD and DSR inputs, they do
30 * not have an RI input, nor do they have DTR or RTS outputs. If
31 * required, these have to be supplied via some other means (eg, GPIO)
32 * and hooked into this driver.
33 */
34
35 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
36 #define SUPPORT_SYSRQ
37 #endif
38
39 #include <linux/module.h>
40 #include <linux/ioport.h>
41 #include <linux/init.h>
42 #include <linux/console.h>
43 #include <linux/sysrq.h>
44 #include <linux/device.h>
45 #include <linux/tty.h>
46 #include <linux/tty_flip.h>
47 #include <linux/serial_core.h>
48 #include <linux/serial.h>
49 #include <linux/amba/bus.h>
50 #include <linux/amba/serial.h>
51 #include <linux/clk.h>
52
53 #include <asm/io.h>
54 #include <asm/sizes.h>
55
56 #define UART_NR 14
57
58 #define SERIAL_AMBA_MAJOR 204
59 #define SERIAL_AMBA_MINOR 64
60 #define SERIAL_AMBA_NR UART_NR
61
62 #define AMBA_ISR_PASS_LIMIT 256
63
64 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
65 #define UART_DUMMY_DR_RX (1 << 16)
66
67 /*
68 * We wrap our port structure around the generic uart_port.
69 */
70 struct uart_amba_port {
71 struct uart_port port;
72 struct clk *clk;
73 unsigned int im; /* interrupt mask */
74 unsigned int old_status;
75 };
76
77 static void pl011_stop_tx(struct uart_port *port)
78 {
79 struct uart_amba_port *uap = (struct uart_amba_port *)port;
80
81 uap->im &= ~UART011_TXIM;
82 writew(uap->im, uap->port.membase + UART011_IMSC);
83 }
84
85 static void pl011_start_tx(struct uart_port *port)
86 {
87 struct uart_amba_port *uap = (struct uart_amba_port *)port;
88
89 uap->im |= UART011_TXIM;
90 writew(uap->im, uap->port.membase + UART011_IMSC);
91 }
92
93 static void pl011_stop_rx(struct uart_port *port)
94 {
95 struct uart_amba_port *uap = (struct uart_amba_port *)port;
96
97 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
98 UART011_PEIM|UART011_BEIM|UART011_OEIM);
99 writew(uap->im, uap->port.membase + UART011_IMSC);
100 }
101
102 static void pl011_enable_ms(struct uart_port *port)
103 {
104 struct uart_amba_port *uap = (struct uart_amba_port *)port;
105
106 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
107 writew(uap->im, uap->port.membase + UART011_IMSC);
108 }
109
110 static void pl011_rx_chars(struct uart_amba_port *uap)
111 {
112 struct tty_struct *tty = uap->port.info->tty;
113 unsigned int status, ch, flag, max_count = 256;
114
115 status = readw(uap->port.membase + UART01x_FR);
116 while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
117 ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
118 flag = TTY_NORMAL;
119 uap->port.icount.rx++;
120
121 /*
122 * Note that the error handling code is
123 * out of the main execution path
124 */
125 if (unlikely(ch & UART_DR_ERROR)) {
126 if (ch & UART011_DR_BE) {
127 ch &= ~(UART011_DR_FE | UART011_DR_PE);
128 uap->port.icount.brk++;
129 if (uart_handle_break(&uap->port))
130 goto ignore_char;
131 } else if (ch & UART011_DR_PE)
132 uap->port.icount.parity++;
133 else if (ch & UART011_DR_FE)
134 uap->port.icount.frame++;
135 if (ch & UART011_DR_OE)
136 uap->port.icount.overrun++;
137
138 ch &= uap->port.read_status_mask;
139
140 if (ch & UART011_DR_BE)
141 flag = TTY_BREAK;
142 else if (ch & UART011_DR_PE)
143 flag = TTY_PARITY;
144 else if (ch & UART011_DR_FE)
145 flag = TTY_FRAME;
146 }
147
148 if (uart_handle_sysrq_char(&uap->port, ch & 255))
149 goto ignore_char;
150
151 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
152
153 ignore_char:
154 status = readw(uap->port.membase + UART01x_FR);
155 }
156 spin_unlock(&uap->port.lock);
157 tty_flip_buffer_push(tty);
158 spin_lock(&uap->port.lock);
159 }
160
161 static void pl011_tx_chars(struct uart_amba_port *uap)
162 {
163 struct circ_buf *xmit = &uap->port.info->xmit;
164 int count;
165
166 if (uap->port.x_char) {
167 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
168 uap->port.icount.tx++;
169 uap->port.x_char = 0;
170 return;
171 }
172 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
173 pl011_stop_tx(&uap->port);
174 return;
175 }
176
177 count = uap->port.fifosize >> 1;
178 do {
179 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
180 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
181 uap->port.icount.tx++;
182 if (uart_circ_empty(xmit))
183 break;
184 } while (--count > 0);
185
186 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
187 uart_write_wakeup(&uap->port);
188
189 if (uart_circ_empty(xmit))
190 pl011_stop_tx(&uap->port);
191 }
192
193 static void pl011_modem_status(struct uart_amba_port *uap)
194 {
195 unsigned int status, delta;
196
197 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
198
199 delta = status ^ uap->old_status;
200 uap->old_status = status;
201
202 if (!delta)
203 return;
204
205 if (delta & UART01x_FR_DCD)
206 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
207
208 if (delta & UART01x_FR_DSR)
209 uap->port.icount.dsr++;
210
211 if (delta & UART01x_FR_CTS)
212 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
213
214 wake_up_interruptible(&uap->port.info->delta_msr_wait);
215 }
216
217 static irqreturn_t pl011_int(int irq, void *dev_id)
218 {
219 struct uart_amba_port *uap = dev_id;
220 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
221 int handled = 0;
222
223 spin_lock(&uap->port.lock);
224
225 status = readw(uap->port.membase + UART011_MIS);
226 if (status) {
227 do {
228 writew(status & ~(UART011_TXIS|UART011_RTIS|
229 UART011_RXIS),
230 uap->port.membase + UART011_ICR);
231
232 if (status & (UART011_RTIS|UART011_RXIS))
233 pl011_rx_chars(uap);
234 if (status & (UART011_DSRMIS|UART011_DCDMIS|
235 UART011_CTSMIS|UART011_RIMIS))
236 pl011_modem_status(uap);
237 if (status & UART011_TXIS)
238 pl011_tx_chars(uap);
239
240 if (pass_counter-- == 0)
241 break;
242
243 status = readw(uap->port.membase + UART011_MIS);
244 } while (status != 0);
245 handled = 1;
246 }
247
248 spin_unlock(&uap->port.lock);
249
250 return IRQ_RETVAL(handled);
251 }
252
253 static unsigned int pl01x_tx_empty(struct uart_port *port)
254 {
255 struct uart_amba_port *uap = (struct uart_amba_port *)port;
256 unsigned int status = readw(uap->port.membase + UART01x_FR);
257 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
258 }
259
260 static unsigned int pl01x_get_mctrl(struct uart_port *port)
261 {
262 struct uart_amba_port *uap = (struct uart_amba_port *)port;
263 unsigned int result = 0;
264 unsigned int status = readw(uap->port.membase + UART01x_FR);
265
266 #define TIOCMBIT(uartbit, tiocmbit) \
267 if (status & uartbit) \
268 result |= tiocmbit
269
270 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
271 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
272 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
273 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
274 #undef TIOCMBIT
275 return result;
276 }
277
278 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
279 {
280 struct uart_amba_port *uap = (struct uart_amba_port *)port;
281 unsigned int cr;
282
283 cr = readw(uap->port.membase + UART011_CR);
284
285 #define TIOCMBIT(tiocmbit, uartbit) \
286 if (mctrl & tiocmbit) \
287 cr |= uartbit; \
288 else \
289 cr &= ~uartbit
290
291 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
292 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
293 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
294 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
295 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
296 #undef TIOCMBIT
297
298 writew(cr, uap->port.membase + UART011_CR);
299 }
300
301 static void pl011_break_ctl(struct uart_port *port, int break_state)
302 {
303 struct uart_amba_port *uap = (struct uart_amba_port *)port;
304 unsigned long flags;
305 unsigned int lcr_h;
306
307 spin_lock_irqsave(&uap->port.lock, flags);
308 lcr_h = readw(uap->port.membase + UART011_LCRH);
309 if (break_state == -1)
310 lcr_h |= UART01x_LCRH_BRK;
311 else
312 lcr_h &= ~UART01x_LCRH_BRK;
313 writew(lcr_h, uap->port.membase + UART011_LCRH);
314 spin_unlock_irqrestore(&uap->port.lock, flags);
315 }
316
317 #ifdef CONFIG_CONSOLE_POLL
318 static int pl010_get_poll_char(struct uart_port *port)
319 {
320 struct uart_amba_port *uap = (struct uart_amba_port *)port;
321 unsigned int status;
322
323 do {
324 status = readw(uap->port.membase + UART01x_FR);
325 } while (status & UART01x_FR_RXFE);
326
327 return readw(uap->port.membase + UART01x_DR);
328 }
329
330 static void pl010_put_poll_char(struct uart_port *port,
331 unsigned char ch)
332 {
333 struct uart_amba_port *uap = (struct uart_amba_port *)port;
334
335 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
336 barrier();
337
338 writew(ch, uap->port.membase + UART01x_DR);
339 }
340
341 #endif /* CONFIG_CONSOLE_POLL */
342
343 static int pl011_startup(struct uart_port *port)
344 {
345 struct uart_amba_port *uap = (struct uart_amba_port *)port;
346 unsigned int cr;
347 int retval;
348
349 /*
350 * Try to enable the clock producer.
351 */
352 retval = clk_enable(uap->clk);
353 if (retval)
354 goto out;
355
356 uap->port.uartclk = clk_get_rate(uap->clk);
357
358 /*
359 * Allocate the IRQ
360 */
361 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
362 if (retval)
363 goto clk_dis;
364
365 writew(UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
366 uap->port.membase + UART011_IFLS);
367
368 /*
369 * Provoke TX FIFO interrupt into asserting.
370 */
371 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
372 writew(cr, uap->port.membase + UART011_CR);
373 writew(0, uap->port.membase + UART011_FBRD);
374 writew(1, uap->port.membase + UART011_IBRD);
375 writew(0, uap->port.membase + UART011_LCRH);
376 writew(0, uap->port.membase + UART01x_DR);
377 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
378 barrier();
379
380 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
381 writew(cr, uap->port.membase + UART011_CR);
382
383 /*
384 * initialise the old status of the modem signals
385 */
386 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
387
388 /*
389 * Finally, enable interrupts
390 */
391 spin_lock_irq(&uap->port.lock);
392 uap->im = UART011_RXIM | UART011_RTIM;
393 writew(uap->im, uap->port.membase + UART011_IMSC);
394 spin_unlock_irq(&uap->port.lock);
395
396 return 0;
397
398 clk_dis:
399 clk_disable(uap->clk);
400 out:
401 return retval;
402 }
403
404 static void pl011_shutdown(struct uart_port *port)
405 {
406 struct uart_amba_port *uap = (struct uart_amba_port *)port;
407 unsigned long val;
408
409 /*
410 * disable all interrupts
411 */
412 spin_lock_irq(&uap->port.lock);
413 uap->im = 0;
414 writew(uap->im, uap->port.membase + UART011_IMSC);
415 writew(0xffff, uap->port.membase + UART011_ICR);
416 spin_unlock_irq(&uap->port.lock);
417
418 /*
419 * Free the interrupt
420 */
421 free_irq(uap->port.irq, uap);
422
423 /*
424 * disable the port
425 */
426 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
427
428 /*
429 * disable break condition and fifos
430 */
431 val = readw(uap->port.membase + UART011_LCRH);
432 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
433 writew(val, uap->port.membase + UART011_LCRH);
434
435 /*
436 * Shut down the clock producer
437 */
438 clk_disable(uap->clk);
439 }
440
441 static void
442 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
443 struct ktermios *old)
444 {
445 unsigned int lcr_h, old_cr;
446 unsigned long flags;
447 unsigned int baud, quot;
448
449 /*
450 * Ask the core to calculate the divisor for us.
451 */
452 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
453 quot = port->uartclk * 4 / baud;
454
455 switch (termios->c_cflag & CSIZE) {
456 case CS5:
457 lcr_h = UART01x_LCRH_WLEN_5;
458 break;
459 case CS6:
460 lcr_h = UART01x_LCRH_WLEN_6;
461 break;
462 case CS7:
463 lcr_h = UART01x_LCRH_WLEN_7;
464 break;
465 default: // CS8
466 lcr_h = UART01x_LCRH_WLEN_8;
467 break;
468 }
469 if (termios->c_cflag & CSTOPB)
470 lcr_h |= UART01x_LCRH_STP2;
471 if (termios->c_cflag & PARENB) {
472 lcr_h |= UART01x_LCRH_PEN;
473 if (!(termios->c_cflag & PARODD))
474 lcr_h |= UART01x_LCRH_EPS;
475 }
476 if (port->fifosize > 1)
477 lcr_h |= UART01x_LCRH_FEN;
478
479 spin_lock_irqsave(&port->lock, flags);
480
481 /*
482 * Update the per-port timeout.
483 */
484 uart_update_timeout(port, termios->c_cflag, baud);
485
486 port->read_status_mask = UART011_DR_OE | 255;
487 if (termios->c_iflag & INPCK)
488 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
489 if (termios->c_iflag & (BRKINT | PARMRK))
490 port->read_status_mask |= UART011_DR_BE;
491
492 /*
493 * Characters to ignore
494 */
495 port->ignore_status_mask = 0;
496 if (termios->c_iflag & IGNPAR)
497 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
498 if (termios->c_iflag & IGNBRK) {
499 port->ignore_status_mask |= UART011_DR_BE;
500 /*
501 * If we're ignoring parity and break indicators,
502 * ignore overruns too (for real raw support).
503 */
504 if (termios->c_iflag & IGNPAR)
505 port->ignore_status_mask |= UART011_DR_OE;
506 }
507
508 /*
509 * Ignore all characters if CREAD is not set.
510 */
511 if ((termios->c_cflag & CREAD) == 0)
512 port->ignore_status_mask |= UART_DUMMY_DR_RX;
513
514 if (UART_ENABLE_MS(port, termios->c_cflag))
515 pl011_enable_ms(port);
516
517 /* first, disable everything */
518 old_cr = readw(port->membase + UART011_CR);
519 writew(0, port->membase + UART011_CR);
520
521 /* Set baud rate */
522 writew(quot & 0x3f, port->membase + UART011_FBRD);
523 writew(quot >> 6, port->membase + UART011_IBRD);
524
525 /*
526 * ----------v----------v----------v----------v-----
527 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
528 * ----------^----------^----------^----------^-----
529 */
530 writew(lcr_h, port->membase + UART011_LCRH);
531 writew(old_cr, port->membase + UART011_CR);
532
533 spin_unlock_irqrestore(&port->lock, flags);
534 }
535
536 static const char *pl011_type(struct uart_port *port)
537 {
538 return port->type == PORT_AMBA ? "AMBA/PL011" : NULL;
539 }
540
541 /*
542 * Release the memory region(s) being used by 'port'
543 */
544 static void pl010_release_port(struct uart_port *port)
545 {
546 release_mem_region(port->mapbase, SZ_4K);
547 }
548
549 /*
550 * Request the memory region(s) being used by 'port'
551 */
552 static int pl010_request_port(struct uart_port *port)
553 {
554 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
555 != NULL ? 0 : -EBUSY;
556 }
557
558 /*
559 * Configure/autoconfigure the port.
560 */
561 static void pl010_config_port(struct uart_port *port, int flags)
562 {
563 if (flags & UART_CONFIG_TYPE) {
564 port->type = PORT_AMBA;
565 pl010_request_port(port);
566 }
567 }
568
569 /*
570 * verify the new serial_struct (for TIOCSSERIAL).
571 */
572 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
573 {
574 int ret = 0;
575 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
576 ret = -EINVAL;
577 if (ser->irq < 0 || ser->irq >= NR_IRQS)
578 ret = -EINVAL;
579 if (ser->baud_base < 9600)
580 ret = -EINVAL;
581 return ret;
582 }
583
584 static struct uart_ops amba_pl011_pops = {
585 .tx_empty = pl01x_tx_empty,
586 .set_mctrl = pl011_set_mctrl,
587 .get_mctrl = pl01x_get_mctrl,
588 .stop_tx = pl011_stop_tx,
589 .start_tx = pl011_start_tx,
590 .stop_rx = pl011_stop_rx,
591 .enable_ms = pl011_enable_ms,
592 .break_ctl = pl011_break_ctl,
593 .startup = pl011_startup,
594 .shutdown = pl011_shutdown,
595 .set_termios = pl011_set_termios,
596 .type = pl011_type,
597 .release_port = pl010_release_port,
598 .request_port = pl010_request_port,
599 .config_port = pl010_config_port,
600 .verify_port = pl010_verify_port,
601 #ifdef CONFIG_CONSOLE_POLL
602 .poll_get_char = pl010_get_poll_char,
603 .poll_put_char = pl010_put_poll_char,
604 #endif
605 };
606
607 static struct uart_amba_port *amba_ports[UART_NR];
608
609 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
610
611 static void pl011_console_putchar(struct uart_port *port, int ch)
612 {
613 struct uart_amba_port *uap = (struct uart_amba_port *)port;
614
615 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
616 barrier();
617 writew(ch, uap->port.membase + UART01x_DR);
618 }
619
620 static void
621 pl011_console_write(struct console *co, const char *s, unsigned int count)
622 {
623 struct uart_amba_port *uap = amba_ports[co->index];
624 unsigned int status, old_cr, new_cr;
625
626 clk_enable(uap->clk);
627
628 /*
629 * First save the CR then disable the interrupts
630 */
631 old_cr = readw(uap->port.membase + UART011_CR);
632 new_cr = old_cr & ~UART011_CR_CTSEN;
633 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
634 writew(new_cr, uap->port.membase + UART011_CR);
635
636 uart_console_write(&uap->port, s, count, pl011_console_putchar);
637
638 /*
639 * Finally, wait for transmitter to become empty
640 * and restore the TCR
641 */
642 do {
643 status = readw(uap->port.membase + UART01x_FR);
644 } while (status & UART01x_FR_BUSY);
645 writew(old_cr, uap->port.membase + UART011_CR);
646
647 clk_disable(uap->clk);
648 }
649
650 static void __init
651 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
652 int *parity, int *bits)
653 {
654 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
655 unsigned int lcr_h, ibrd, fbrd;
656
657 lcr_h = readw(uap->port.membase + UART011_LCRH);
658
659 *parity = 'n';
660 if (lcr_h & UART01x_LCRH_PEN) {
661 if (lcr_h & UART01x_LCRH_EPS)
662 *parity = 'e';
663 else
664 *parity = 'o';
665 }
666
667 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
668 *bits = 7;
669 else
670 *bits = 8;
671
672 ibrd = readw(uap->port.membase + UART011_IBRD);
673 fbrd = readw(uap->port.membase + UART011_FBRD);
674
675 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
676 }
677 }
678
679 static int __init pl011_console_setup(struct console *co, char *options)
680 {
681 struct uart_amba_port *uap;
682 int baud = 38400;
683 int bits = 8;
684 int parity = 'n';
685 int flow = 'n';
686
687 /*
688 * Check whether an invalid uart number has been specified, and
689 * if so, search for the first available port that does have
690 * console support.
691 */
692 if (co->index >= UART_NR)
693 co->index = 0;
694 uap = amba_ports[co->index];
695 if (!uap)
696 return -ENODEV;
697
698 uap->port.uartclk = clk_get_rate(uap->clk);
699
700 if (options)
701 uart_parse_options(options, &baud, &parity, &bits, &flow);
702 else
703 pl011_console_get_options(uap, &baud, &parity, &bits);
704
705 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
706 }
707
708 static struct uart_driver amba_reg;
709 static struct console amba_console = {
710 .name = "ttyAMA",
711 .write = pl011_console_write,
712 .device = uart_console_device,
713 .setup = pl011_console_setup,
714 .flags = CON_PRINTBUFFER,
715 .index = -1,
716 .data = &amba_reg,
717 };
718
719 #define AMBA_CONSOLE (&amba_console)
720 #else
721 #define AMBA_CONSOLE NULL
722 #endif
723
724 static struct uart_driver amba_reg = {
725 .owner = THIS_MODULE,
726 .driver_name = "ttyAMA",
727 .dev_name = "ttyAMA",
728 .major = SERIAL_AMBA_MAJOR,
729 .minor = SERIAL_AMBA_MINOR,
730 .nr = UART_NR,
731 .cons = AMBA_CONSOLE,
732 };
733
734 static int pl011_probe(struct amba_device *dev, void *id)
735 {
736 struct uart_amba_port *uap;
737 void __iomem *base;
738 int i, ret;
739
740 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
741 if (amba_ports[i] == NULL)
742 break;
743
744 if (i == ARRAY_SIZE(amba_ports)) {
745 ret = -EBUSY;
746 goto out;
747 }
748
749 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
750 if (uap == NULL) {
751 ret = -ENOMEM;
752 goto out;
753 }
754
755 base = ioremap(dev->res.start, PAGE_SIZE);
756 if (!base) {
757 ret = -ENOMEM;
758 goto free;
759 }
760
761 uap->clk = clk_get(&dev->dev, "UARTCLK");
762 if (IS_ERR(uap->clk)) {
763 ret = PTR_ERR(uap->clk);
764 goto unmap;
765 }
766
767 uap->port.dev = &dev->dev;
768 uap->port.mapbase = dev->res.start;
769 uap->port.membase = base;
770 uap->port.iotype = UPIO_MEM;
771 uap->port.irq = dev->irq[0];
772 uap->port.fifosize = 16;
773 uap->port.ops = &amba_pl011_pops;
774 uap->port.flags = UPF_BOOT_AUTOCONF;
775 uap->port.line = i;
776
777 amba_ports[i] = uap;
778
779 amba_set_drvdata(dev, uap);
780 ret = uart_add_one_port(&amba_reg, &uap->port);
781 if (ret) {
782 amba_set_drvdata(dev, NULL);
783 amba_ports[i] = NULL;
784 clk_put(uap->clk);
785 unmap:
786 iounmap(base);
787 free:
788 kfree(uap);
789 }
790 out:
791 return ret;
792 }
793
794 static int pl011_remove(struct amba_device *dev)
795 {
796 struct uart_amba_port *uap = amba_get_drvdata(dev);
797 int i;
798
799 amba_set_drvdata(dev, NULL);
800
801 uart_remove_one_port(&amba_reg, &uap->port);
802
803 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
804 if (amba_ports[i] == uap)
805 amba_ports[i] = NULL;
806
807 iounmap(uap->port.membase);
808 clk_put(uap->clk);
809 kfree(uap);
810 return 0;
811 }
812
813 static struct amba_id pl011_ids[] __initdata = {
814 {
815 .id = 0x00041011,
816 .mask = 0x000fffff,
817 },
818 { 0, 0 },
819 };
820
821 static struct amba_driver pl011_driver = {
822 .drv = {
823 .name = "uart-pl011",
824 },
825 .id_table = pl011_ids,
826 .probe = pl011_probe,
827 .remove = pl011_remove,
828 };
829
830 static int __init pl011_init(void)
831 {
832 int ret;
833 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
834
835 ret = uart_register_driver(&amba_reg);
836 if (ret == 0) {
837 ret = amba_driver_register(&pl011_driver);
838 if (ret)
839 uart_unregister_driver(&amba_reg);
840 }
841 return ret;
842 }
843
844 static void __exit pl011_exit(void)
845 {
846 amba_driver_unregister(&pl011_driver);
847 uart_unregister_driver(&amba_reg);
848 }
849
850 module_init(pl011_init);
851 module_exit(pl011_exit);
852
853 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
854 MODULE_DESCRIPTION("ARM AMBA serial port driver");
855 MODULE_LICENSE("GPL");
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