arch/arm/plat-s3c64xx/include/plat/irqs.h

   1 /* linux/arch/arm/plat-s3c64xx/include/mach/irqs.h
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * S3C64XX - Common IRQ support
   9  */
  10
  11 #ifndef __ASM_PLAT_S3C64XX_IRQS_H
  12 #define __ASM_PLAT_S3C64XX_IRQS_H __FILE__
  13
  14 /* we keep the first set of CPU IRQs out of the range of
  15  * the ISA space, so that the PC104 has them to itself
  16  * and we don't end up having to do horrible things to the
  17  * standard ISA drivers....
  18  *
  19  * note, since we're using the VICs, our start must be a
  20  * mulitple of 32 to allow the common code to work
  21  */
  22
  23 #define S3C_IRQ_OFFSET  (32)
  24
  25 #define S3C_IRQ(x)      ((x) + S3C_IRQ_OFFSET)
  26
  27 /* UART interrupts, each UART has 4 intterupts per channel so
  28  * use the space between the ISA and S3C main interrupts. Note, these
  29  * are not in the same order as the S3C24XX series! */
  30
  31 #define IRQ_S3CUART_BASE0       (16)
  32 #define IRQ_S3CUART_BASE1       (20)
  33 #define IRQ_S3CUART_BASE2       (24)
  34 #define IRQ_S3CUART_BASE3       (28)
  35
  36 #define UART_IRQ_RXD            (0)
  37 #define UART_IRQ_ERR            (1)
  38 #define UART_IRQ_TXD            (2)
  39 #define UART_IRQ_MODEM          (3)
  40
  41 #define IRQ_S3CUART_RX0         (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
  42 #define IRQ_S3CUART_TX0         (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
  43 #define IRQ_S3CUART_ERR0        (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
  44
  45 #define IRQ_S3CUART_RX1         (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
  46 #define IRQ_S3CUART_TX1         (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
  47 #define IRQ_S3CUART_ERR1        (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
  48
  49 #define IRQ_S3CUART_RX2         (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
  50 #define IRQ_S3CUART_TX2         (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
  51 #define IRQ_S3CUART_ERR2        (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
  52
  53 #define IRQ_S3CUART_RX3         (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
  54 #define IRQ_S3CUART_TX3         (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
  55 #define IRQ_S3CUART_ERR3        (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
  56
  57 /* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
  58  * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
  59  * which we place after the pair of VICs. */
  60
  61 #define S3C_IRQ_EINT_BASE       S3C_IRQ(64)
  62
  63 #define S3C_EINT(x)     ((x) + S3C_IRQ_EINT_BASE)
  64
  65 /* Define NR_IRQs here, machine specific can always re-define.
  66  * Currently the IRQ_EINT27 is the last one we can have. */
  67
  68 #define NR_IRQS (S3C_EINT(27) + 1)
  69
  70 #endif /* __ASM_PLAT_S3C64XX_IRQS_H */
  71