arch/arm/plat-s3c64xx/s3c6400-clock.c

   1 /* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * S3C6400 based common clock support
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/list.h>
  19 #include <linux/errno.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/sysdev.h>
  23 #include <linux/io.h>
  24
  25 #include <mach/hardware.h>
  26 #include <mach/map.h>
  27
  28 #include <plat/cpu-freq.h>
  29
  30 #include <plat/regs-clock.h>
  31 #include <plat/clock.h>
  32 #include <plat/cpu.h>
  33 #include <plat/pll.h>
  34
  35 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
  36  * ext_xtal_mux for want of an actual name from the manual.
  37 */
  38
  39 struct clk clk_ext_xtal_mux = {
  40         .name           = "ext_xtal",
  41         .id             = -1,
  42 };
  43
  44 #define clk_fin_apll clk_ext_xtal_mux
  45 #define clk_fin_mpll clk_ext_xtal_mux
  46 #define clk_fin_epll clk_ext_xtal_mux
  47
  48 #define clk_fout_mpll   clk_mpll
  49
  50 struct clk_sources {
  51         unsigned int    nr_sources;
  52         struct clk      **sources;
  53 };
  54
  55 struct clksrc_clk {
  56         struct clk              clk;
  57         unsigned int            mask;
  58         unsigned int            shift;
  59
  60         struct clk_sources      *sources;
  61
  62         unsigned int            divider_shift;
  63         void __iomem            *reg_divider;
  64 };
  65
  66 struct clk clk_fout_apll = {
  67         .name           = "fout_apll",
  68         .id             = -1,
  69 };
  70
  71 static struct clk *clk_src_apll_list[] = {
  72         [0] = &clk_fin_apll,
  73         [1] = &clk_fout_apll,
  74 };
  75
  76 static struct clk_sources clk_src_apll = {
  77         .sources        = clk_src_apll_list,
  78         .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
  79 };
  80
  81 struct clksrc_clk clk_mout_apll = {
  82         .clk    = {
  83                 .name           = "mout_apll",
  84                 .id             = -1,
  85         },
  86         .shift          = S3C6400_CLKSRC_APLL_MOUT_SHIFT,
  87         .mask           = S3C6400_CLKSRC_APLL_MOUT,
  88         .sources        = &clk_src_apll,
  89 };
  90
  91 struct clk clk_fout_epll = {
  92         .name           = "fout_epll",
  93         .id             = -1,
  94 };
  95
  96 static struct clk *clk_src_epll_list[] = {
  97         [0] = &clk_fin_epll,
  98         [1] = &clk_fout_epll,
  99 };
 100
 101 static struct clk_sources clk_src_epll = {
 102         .sources        = clk_src_epll_list,
 103         .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
 104 };
 105
 106 struct clksrc_clk clk_mout_epll = {
 107         .clk    = {
 108                 .name           = "mout_epll",
 109                 .id             = -1,
 110         },
 111         .shift          = S3C6400_CLKSRC_EPLL_MOUT_SHIFT,
 112         .mask           = S3C6400_CLKSRC_EPLL_MOUT,
 113         .sources        = &clk_src_epll,
 114 };
 115
 116 static struct clk *clk_src_mpll_list[] = {
 117         [0] = &clk_fin_mpll,
 118         [1] = &clk_fout_mpll,
 119 };
 120
 121 static struct clk_sources clk_src_mpll = {
 122         .sources        = clk_src_mpll_list,
 123         .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
 124 };
 125
 126 struct clksrc_clk clk_mout_mpll = {
 127         .clk = {
 128                 .name           = "mout_mpll",
 129                 .id             = -1,
 130         },
 131         .shift          = S3C6400_CLKSRC_MPLL_MOUT_SHIFT,
 132         .mask           = S3C6400_CLKSRC_MPLL_MOUT,
 133         .sources        = &clk_src_mpll,
 134 };
 135
 136 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
 137 {
 138         unsigned long rate = clk_get_rate(clk->parent);
 139
 140         printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
 141
 142         if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
 143                 rate /= 2;
 144
 145         return rate;
 146 }
 147
 148 struct clk clk_dout_mpll = {
 149         .name           = "dout_mpll",
 150         .id             = -1,
 151         .parent         = &clk_mout_mpll.clk,
 152         .get_rate       = s3c64xx_clk_doutmpll_get_rate,
 153 };
 154
 155 static struct clk *clkset_spi_mmc_list[] = {
 156         &clk_mout_epll.clk,
 157         &clk_dout_mpll,
 158         &clk_fin_epll,
 159         &clk_27m,
 160 };
 161
 162 static struct clk_sources clkset_spi_mmc = {
 163         .sources        = clkset_spi_mmc_list,
 164         .nr_sources     = ARRAY_SIZE(clkset_spi_mmc_list),
 165 };
 166
 167 static struct clk *clkset_irda_list[] = {
 168         &clk_mout_epll.clk,
 169         &clk_dout_mpll,
 170         NULL,
 171         &clk_27m,
 172 };
 173
 174 static struct clk_sources clkset_irda = {
 175         .sources        = clkset_irda_list,
 176         .nr_sources     = ARRAY_SIZE(clkset_irda_list),
 177 };
 178
 179 static struct clk *clkset_uart_list[] = {
 180         &clk_mout_epll.clk,
 181         &clk_dout_mpll,
 182         NULL,
 183         NULL
 184 };
 185
 186 static struct clk_sources clkset_uart = {
 187         .sources        = clkset_uart_list,
 188         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 189 };
 190
 191 static struct clk *clkset_uhost_list[] = {
 192         &clk_mout_epll.clk,
 193         &clk_dout_mpll,
 194         &clk_fin_epll,
 195         &clk_48m,
 196 };
 197
 198 static struct clk_sources clkset_uhost = {
 199         .sources        = clkset_uhost_list,
 200         .nr_sources     = ARRAY_SIZE(clkset_uhost_list),
 201 };
 202
 203
 204 /* The peripheral clocks are all controlled via clocksource followed
 205  * by an optional divider and gate stage. We currently roll this into
 206  * one clock which hides the intermediate clock from the mux.
 207  *
 208  * Note, the JPEG clock can only be an even divider...
 209  *
 210  * The scaler and LCD clocks depend on the S3C64XX version, and also
 211  * have a common parent divisor so are not included here.
 212  */
 213
 214 static inline struct clksrc_clk *to_clksrc(struct clk *clk)
 215 {
 216         return container_of(clk, struct clksrc_clk, clk);
 217 }
 218
 219 static unsigned long s3c64xx_getrate_clksrc(struct clk *clk)
 220 {
 221         struct clksrc_clk *sclk = to_clksrc(clk);
 222         unsigned long rate = clk_get_rate(clk->parent);
 223         u32 clkdiv = __raw_readl(sclk->reg_divider);
 224
 225         clkdiv >>= sclk->divider_shift;
 226         clkdiv &= 0xf;
 227         clkdiv++;
 228
 229         rate /= clkdiv;
 230         return rate;
 231 }
 232
 233 static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
 234 {
 235         struct clksrc_clk *sclk = to_clksrc(clk);
 236         void __iomem *reg = sclk->reg_divider;
 237         unsigned int div;
 238         u32 val;
 239
 240         rate = clk_round_rate(clk, rate);
 241         div = clk_get_rate(clk->parent) / rate;
 242
 243         val = __raw_readl(reg);
 244         val &= ~sclk->mask;
 245         val |= (rate - 1) << sclk->shift;
 246         __raw_writel(val, reg);
 247
 248         return 0;
 249 }
 250
 251 static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent)
 252 {
 253         struct clksrc_clk *sclk = to_clksrc(clk);
 254         struct clk_sources *srcs = sclk->sources;
 255         u32 clksrc = __raw_readl(S3C_CLK_SRC);
 256         int src_nr = -1;
 257         int ptr;
 258
 259         for (ptr = 0; ptr < srcs->nr_sources; ptr++)
 260                 if (srcs->sources[ptr] == parent) {
 261                         src_nr = ptr;
 262                         break;
 263                 }
 264
 265         if (src_nr >= 0) {
 266                 clksrc &= ~sclk->mask;
 267                 clksrc |= src_nr << sclk->shift;
 268
 269                 __raw_writel(clksrc, S3C_CLK_SRC);
 270                 return 0;
 271         }
 272
 273         return -EINVAL;
 274 }
 275
 276 static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
 277                                               unsigned long rate)
 278 {
 279         unsigned long parent_rate = clk_get_rate(clk->parent);
 280         int div;
 281
 282         if (rate > parent_rate)
 283                 rate = parent_rate;
 284         else {
 285                 div = rate / parent_rate;
 286
 287                 if (div == 0)
 288                         div = 1;
 289                 if (div > 16)
 290                         div = 16;
 291
 292                 rate = parent_rate / div;
 293         }
 294
 295         return rate;
 296 }
 297
 298 static struct clksrc_clk clk_mmc0 = {
 299         .clk    = {
 300                 .name           = "mmc_bus",
 301                 .id             = 0,
 302                 .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
 303                 .enable         = s3c64xx_sclk_ctrl,
 304                 .set_parent     = s3c64xx_setparent_clksrc,
 305                 .get_rate       = s3c64xx_getrate_clksrc,
 306                 .set_rate       = s3c64xx_setrate_clksrc,
 307                 .round_rate     = s3c64xx_roundrate_clksrc,
 308         },
 309         .shift          = S3C6400_CLKSRC_MMC0_SHIFT,
 310         .mask           = S3C6400_CLKSRC_MMC0_MASK,
 311         .sources        = &clkset_spi_mmc,
 312         .divider_shift  = S3C6400_CLKDIV1_MMC0_SHIFT,
 313         .reg_divider    = S3C_CLK_DIV1,
 314 };
 315
 316 static struct clksrc_clk clk_mmc1 = {
 317         .clk    = {
 318                 .name           = "mmc_bus",
 319                 .id             = 1,
 320                 .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
 321                 .enable         = s3c64xx_sclk_ctrl,
 322                 .get_rate       = s3c64xx_getrate_clksrc,
 323                 .set_rate       = s3c64xx_setrate_clksrc,
 324                 .set_parent     = s3c64xx_setparent_clksrc,
 325                 .round_rate     = s3c64xx_roundrate_clksrc,
 326         },
 327         .shift          = S3C6400_CLKSRC_MMC1_SHIFT,
 328         .mask           = S3C6400_CLKSRC_MMC1_MASK,
 329         .sources        = &clkset_spi_mmc,
 330         .divider_shift  = S3C6400_CLKDIV1_MMC1_SHIFT,
 331         .reg_divider    = S3C_CLK_DIV1,
 332 };
 333
 334 static struct clksrc_clk clk_mmc2 = {
 335         .clk    = {
 336                 .name           = "mmc_bus",
 337                 .id             = 2,
 338                 .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
 339                 .enable         = s3c64xx_sclk_ctrl,
 340                 .get_rate       = s3c64xx_getrate_clksrc,
 341                 .set_rate       = s3c64xx_setrate_clksrc,
 342                 .set_parent     = s3c64xx_setparent_clksrc,
 343                 .round_rate     = s3c64xx_roundrate_clksrc,
 344         },
 345         .shift          = S3C6400_CLKSRC_MMC2_SHIFT,
 346         .mask           = S3C6400_CLKSRC_MMC2_MASK,
 347         .sources        = &clkset_spi_mmc,
 348         .divider_shift  = S3C6400_CLKDIV1_MMC2_SHIFT,
 349         .reg_divider    = S3C_CLK_DIV1,
 350 };
 351
 352 static struct clksrc_clk clk_usbhost = {
 353         .clk    = {
 354                 .name           = "usb-host-bus",
 355                 .id             = -1,
 356                 .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
 357                 .enable         = s3c64xx_sclk_ctrl,
 358                 .set_parent     = s3c64xx_setparent_clksrc,
 359                 .get_rate       = s3c64xx_getrate_clksrc,
 360                 .set_rate       = s3c64xx_setrate_clksrc,
 361                 .round_rate     = s3c64xx_roundrate_clksrc,
 362         },
 363         .shift          = S3C6400_CLKSRC_UHOST_SHIFT,
 364         .mask           = S3C6400_CLKSRC_UHOST_MASK,
 365         .sources        = &clkset_uhost,
 366         .divider_shift  = S3C6400_CLKDIV1_UHOST_SHIFT,
 367         .reg_divider    = S3C_CLK_DIV1,
 368 };
 369
 370 static struct clksrc_clk clk_uart_uclk1 = {
 371         .clk    = {
 372                 .name           = "uclk1",
 373                 .id             = -1,
 374                 .ctrlbit        = S3C_CLKCON_SCLK_UART,
 375                 .enable         = s3c64xx_sclk_ctrl,
 376                 .set_parent     = s3c64xx_setparent_clksrc,
 377                 .get_rate       = s3c64xx_getrate_clksrc,
 378                 .set_rate       = s3c64xx_setrate_clksrc,
 379                 .round_rate     = s3c64xx_roundrate_clksrc,
 380         },
 381         .shift          = S3C6400_CLKSRC_UART_SHIFT,
 382         .mask           = S3C6400_CLKSRC_UART_MASK,
 383         .sources        = &clkset_uart,
 384         .divider_shift  = S3C6400_CLKDIV2_UART_SHIFT,
 385         .reg_divider    = S3C_CLK_DIV2,
 386 };
 387
 388 /* Where does UCLK0 come from? */
 389
 390 static struct clksrc_clk clk_spi0 = {
 391         .clk    = {
 392                 .name           = "spi-bus",
 393                 .id             = 0,
 394                 .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
 395                 .enable         = s3c64xx_sclk_ctrl,
 396                 .set_parent     = s3c64xx_setparent_clksrc,
 397                 .get_rate       = s3c64xx_getrate_clksrc,
 398                 .set_rate       = s3c64xx_setrate_clksrc,
 399                 .round_rate     = s3c64xx_roundrate_clksrc,
 400         },
 401         .shift          = S3C6400_CLKSRC_SPI0_SHIFT,
 402         .mask           = S3C6400_CLKSRC_SPI0_MASK,
 403         .sources        = &clkset_spi_mmc,
 404         .divider_shift  = S3C6400_CLKDIV2_SPI0_SHIFT,
 405         .reg_divider    = S3C_CLK_DIV2,
 406 };
 407
 408 static struct clksrc_clk clk_spi1 = {
 409         .clk    = {
 410                 .name           = "spi-bus",
 411                 .id             = 1,
 412                 .ctrlbit        = S3C_CLKCON_SCLK_SPI1,
 413                 .enable         = s3c64xx_sclk_ctrl,
 414                 .set_parent     = s3c64xx_setparent_clksrc,
 415                 .get_rate       = s3c64xx_getrate_clksrc,
 416                 .set_rate       = s3c64xx_setrate_clksrc,
 417                 .round_rate     = s3c64xx_roundrate_clksrc,
 418         },
 419         .shift          = S3C6400_CLKSRC_SPI1_SHIFT,
 420         .mask           = S3C6400_CLKSRC_SPI1_MASK,
 421         .sources        = &clkset_spi_mmc,
 422         .divider_shift  = S3C6400_CLKDIV2_SPI1_SHIFT,
 423         .reg_divider    = S3C_CLK_DIV2,
 424 };
 425
 426 static struct clk clk_iis_cd0 = {
 427         .name           = "iis_cdclk0",
 428         .id             = -1,
 429 };
 430
 431 static struct clk clk_iis_cd1 = {
 432         .name           = "iis_cdclk1",
 433         .id             = -1,
 434 };
 435
 436 static struct clk clk_pcm_cd = {
 437         .name           = "pcm_cdclk",
 438         .id             = -1,
 439 };
 440
 441 static struct clk *clkset_audio0_list[] = {
 442         [0] = &clk_mout_epll.clk,
 443         [1] = &clk_dout_mpll,
 444         [2] = &clk_fin_epll,
 445         [3] = &clk_iis_cd0,
 446         [4] = &clk_pcm_cd,
 447 };
 448
 449 static struct clk_sources clkset_audio0 = {
 450         .sources        = clkset_audio0_list,
 451         .nr_sources     = ARRAY_SIZE(clkset_audio0_list),
 452 };
 453
 454 static struct clksrc_clk clk_audio0 = {
 455         .clk    = {
 456                 .name           = "audio-bus",
 457                 .id             = 0,
 458                 .ctrlbit        = S3C_CLKCON_SCLK_AUDIO0,
 459                 .enable         = s3c64xx_sclk_ctrl,
 460                 .set_parent     = s3c64xx_setparent_clksrc,
 461                 .get_rate       = s3c64xx_getrate_clksrc,
 462                 .set_rate       = s3c64xx_setrate_clksrc,
 463                 .round_rate     = s3c64xx_roundrate_clksrc,
 464         },
 465         .shift          = S3C6400_CLKSRC_AUDIO0_SHIFT,
 466         .mask           = S3C6400_CLKSRC_AUDIO0_MASK,
 467         .sources        = &clkset_audio0,
 468         .divider_shift  = S3C6400_CLKDIV2_AUDIO0_SHIFT,
 469         .reg_divider    = S3C_CLK_DIV2,
 470 };
 471
 472 static struct clk *clkset_audio1_list[] = {
 473         [0] = &clk_mout_epll.clk,
 474         [1] = &clk_dout_mpll,
 475         [2] = &clk_fin_epll,
 476         [3] = &clk_iis_cd1,
 477         [4] = &clk_pcm_cd,
 478 };
 479
 480 static struct clk_sources clkset_audio1 = {
 481         .sources        = clkset_audio1_list,
 482         .nr_sources     = ARRAY_SIZE(clkset_audio1_list),
 483 };
 484
 485 static struct clksrc_clk clk_audio1 = {
 486         .clk    = {
 487                 .name           = "audio-bus",
 488                 .id             = 1,
 489                 .ctrlbit        = S3C_CLKCON_SCLK_AUDIO1,
 490                 .enable         = s3c64xx_sclk_ctrl,
 491                 .set_parent     = s3c64xx_setparent_clksrc,
 492                 .get_rate       = s3c64xx_getrate_clksrc,
 493                 .set_rate       = s3c64xx_setrate_clksrc,
 494                 .round_rate     = s3c64xx_roundrate_clksrc,
 495         },
 496         .shift          = S3C6400_CLKSRC_AUDIO1_SHIFT,
 497         .mask           = S3C6400_CLKSRC_AUDIO1_MASK,
 498         .sources        = &clkset_audio1,
 499         .divider_shift  = S3C6400_CLKDIV2_AUDIO1_SHIFT,
 500         .reg_divider    = S3C_CLK_DIV2,
 501 };
 502
 503 static struct clksrc_clk clk_irda = {
 504         .clk    = {
 505                 .name           = "irda-bus",
 506                 .id             = 0,
 507                 .ctrlbit        = S3C_CLKCON_SCLK_IRDA,
 508                 .enable         = s3c64xx_sclk_ctrl,
 509                 .set_parent     = s3c64xx_setparent_clksrc,
 510                 .get_rate       = s3c64xx_getrate_clksrc,
 511                 .set_rate       = s3c64xx_setrate_clksrc,
 512                 .round_rate     = s3c64xx_roundrate_clksrc,
 513         },
 514         .shift          = S3C6400_CLKSRC_IRDA_SHIFT,
 515         .mask           = S3C6400_CLKSRC_IRDA_MASK,
 516         .sources        = &clkset_irda,
 517         .divider_shift  = S3C6400_CLKDIV2_IRDA_SHIFT,
 518         .reg_divider    = S3C_CLK_DIV2,
 519 };
 520
 521 /* Clock initialisation code */
 522
 523 static struct clksrc_clk *init_parents[] = {
 524         &clk_mout_apll,
 525         &clk_mout_epll,
 526         &clk_mout_mpll,
 527         &clk_mmc0,
 528         &clk_mmc1,
 529         &clk_mmc2,
 530         &clk_usbhost,
 531         &clk_uart_uclk1,
 532         &clk_spi0,
 533         &clk_spi1,
 534         &clk_audio0,
 535         &clk_audio1,
 536         &clk_irda,
 537 };
 538
 539 static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
 540 {
 541         struct clk_sources *srcs = clk->sources;
 542         u32 clksrc = __raw_readl(S3C_CLK_SRC);
 543
 544         clksrc &= clk->mask;
 545         clksrc >>= clk->shift;
 546
 547         if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
 548                 printk(KERN_ERR "%s: bad source %d\n",
 549                        clk->clk.name, clksrc);
 550                 return;
 551         }
 552
 553         clk->clk.parent = srcs->sources[clksrc];
 554
 555         printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
 556                clk->clk.name, clk->clk.parent->name, clksrc,
 557                clk_get_rate(&clk->clk));
 558 }
 559
 560 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
 561
 562 void __init_or_cpufreq s3c6400_setup_clocks(void)
 563 {
 564         struct clk *xtal_clk;
 565         unsigned long xtal;
 566         unsigned long fclk;
 567         unsigned long hclk;
 568         unsigned long hclk2;
 569         unsigned long pclk;
 570         unsigned long epll;
 571         unsigned long apll;
 572         unsigned long mpll;
 573         unsigned int ptr;
 574         u32 clkdiv0;
 575
 576         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
 577
 578         clkdiv0 = __raw_readl(S3C_CLK_DIV0);
 579         printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
 580
 581         xtal_clk = clk_get(NULL, "xtal");
 582         BUG_ON(IS_ERR(xtal_clk));
 583
 584         xtal = clk_get_rate(xtal_clk);
 585         clk_put(xtal_clk);
 586
 587         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 588
 589         epll = s3c6400_get_epll(xtal);
 590         mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
 591         apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
 592
 593         fclk = mpll;
 594
 595         printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
 596                apll, mpll, epll);
 597
 598         hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
 599         hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
 600         pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
 601
 602         printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
 603                hclk2, hclk, pclk);
 604
 605         clk_fout_mpll.rate = mpll;
 606         clk_fout_epll.rate = epll;
 607         clk_fout_apll.rate = apll;
 608
 609         clk_h.rate = hclk;
 610         clk_p.rate = pclk;
 611         clk_f.rate = fclk;
 612
 613         for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
 614                 s3c6400_set_clksrc(init_parents[ptr]);
 615 }
 616
 617 static struct clk *clks[] __initdata = {
 618         &clk_ext_xtal_mux,
 619         &clk_iis_cd0,
 620         &clk_iis_cd1,
 621         &clk_pcm_cd,
 622         &clk_mout_epll.clk,
 623         &clk_fout_epll,
 624         &clk_mout_mpll.clk,
 625         &clk_dout_mpll,
 626         &clk_mmc0.clk,
 627         &clk_mmc1.clk,
 628         &clk_mmc2.clk,
 629         &clk_usbhost.clk,
 630         &clk_uart_uclk1.clk,
 631         &clk_spi0.clk,
 632         &clk_spi1.clk,
 633         &clk_audio0.clk,
 634         &clk_audio1.clk,
 635         &clk_irda.clk,
 636 };
 637
 638 void __init s3c6400_register_clocks(void)
 639 {
 640         struct clk *clkp;
 641         int ret;
 642         int ptr;
 643
 644         for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
 645                 clkp = clks[ptr];
 646                 ret = s3c24xx_register_clock(clkp);
 647                 if (ret < 0) {
 648                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 649                                clkp->name, ret);
 650                 }
 651         }
 652
 653         clk_mpll.parent = &clk_mout_mpll.clk;
 654         clk_epll.parent = &clk_mout_epll.clk;
 655 }