1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
53 #include <linux/netdevice.h>
54 #include <linux/ethtool.h>
55 #include <linux/delay.h>
56 #include <linux/pci.h>
60 #define ICH_FLASH_GFPREG 0x0000
61 #define ICH_FLASH_HSFSTS 0x0004
62 #define ICH_FLASH_HSFCTL 0x0006
63 #define ICH_FLASH_FADDR 0x0008
64 #define ICH_FLASH_FDATA0 0x0010
65 #define ICH_FLASH_PR0 0x0074
67 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
68 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
69 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
70 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
71 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
73 #define ICH_CYCLE_READ 0
74 #define ICH_CYCLE_WRITE 2
75 #define ICH_CYCLE_ERASE 3
77 #define FLASH_GFPREG_BASE_MASK 0x1FFF
78 #define FLASH_SECTOR_ADDR_SHIFT 12
80 #define ICH_FLASH_SEG_SIZE_256 256
81 #define ICH_FLASH_SEG_SIZE_4K 4096
82 #define ICH_FLASH_SEG_SIZE_8K 8192
83 #define ICH_FLASH_SEG_SIZE_64K 65536
86 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
88 #define E1000_ICH_MNG_IAMT_MODE 0x2
90 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
91 (ID_LED_DEF1_OFF2 << 8) | \
92 (ID_LED_DEF1_ON2 << 4) | \
95 #define E1000_ICH_NVM_SIG_WORD 0x13
96 #define E1000_ICH_NVM_SIG_MASK 0xC000
97 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
98 #define E1000_ICH_NVM_SIG_VALUE 0x80
100 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
102 #define E1000_FEXTNVM_SW_CONFIG 1
103 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
105 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
107 #define E1000_ICH_RAR_ENTRIES 7
109 #define PHY_PAGE_SHIFT 5
110 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
111 ((reg) & MAX_PHY_REG_ADDRESS))
112 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
113 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
115 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
116 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
117 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
119 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
120 /* Offset 04h HSFSTS */
121 union ich8_hws_flash_status
{
123 u16 flcdone
:1; /* bit 0 Flash Cycle Done */
124 u16 flcerr
:1; /* bit 1 Flash Cycle Error */
125 u16 dael
:1; /* bit 2 Direct Access error Log */
126 u16 berasesz
:2; /* bit 4:3 Sector Erase Size */
127 u16 flcinprog
:1; /* bit 5 flash cycle in Progress */
128 u16 reserved1
:2; /* bit 13:6 Reserved */
129 u16 reserved2
:6; /* bit 13:6 Reserved */
130 u16 fldesvalid
:1; /* bit 14 Flash Descriptor Valid */
131 u16 flockdn
:1; /* bit 15 Flash Config Lock-Down */
136 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
137 /* Offset 06h FLCTL */
138 union ich8_hws_flash_ctrl
{
139 struct ich8_hsflctl
{
140 u16 flcgo
:1; /* 0 Flash Cycle Go */
141 u16 flcycle
:2; /* 2:1 Flash Cycle */
142 u16 reserved
:5; /* 7:3 Reserved */
143 u16 fldbcount
:2; /* 9:8 Flash Data Byte Count */
144 u16 flockdn
:6; /* 15:10 Reserved */
149 /* ICH Flash Region Access Permissions */
150 union ich8_hws_flash_regacc
{
152 u32 grra
:8; /* 0:7 GbE region Read Access */
153 u32 grwa
:8; /* 8:15 GbE region Write Access */
154 u32 gmrag
:8; /* 23:16 GbE Master Read Access Grant */
155 u32 gmwag
:8; /* 31:24 GbE Master Write Access Grant */
160 /* ICH Flash Protected Region */
161 union ich8_flash_protected_range
{
163 u32 base
:13; /* 0:12 Protected Range Base */
164 u32 reserved1
:2; /* 13:14 Reserved */
165 u32 rpe
:1; /* 15 Read Protection Enable */
166 u32 limit
:13; /* 16:28 Protected Range Limit */
167 u32 reserved2
:2; /* 29:30 Reserved */
168 u32 wpe
:1; /* 31 Write Protection Enable */
173 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
);
174 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
);
175 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
);
176 static s32
e1000_check_polarity_ife_ich8lan(struct e1000_hw
*hw
);
177 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
);
178 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
179 u32 offset
, u8 byte
);
180 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
182 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
184 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
186 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
);
187 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
);
188 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
);
190 static inline u16
__er16flash(struct e1000_hw
*hw
, unsigned long reg
)
192 return readw(hw
->flash_address
+ reg
);
195 static inline u32
__er32flash(struct e1000_hw
*hw
, unsigned long reg
)
197 return readl(hw
->flash_address
+ reg
);
200 static inline void __ew16flash(struct e1000_hw
*hw
, unsigned long reg
, u16 val
)
202 writew(val
, hw
->flash_address
+ reg
);
205 static inline void __ew32flash(struct e1000_hw
*hw
, unsigned long reg
, u32 val
)
207 writel(val
, hw
->flash_address
+ reg
);
210 #define er16flash(reg) __er16flash(hw, (reg))
211 #define er32flash(reg) __er32flash(hw, (reg))
212 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
213 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
216 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
217 * @hw: pointer to the HW structure
219 * Initialize family-specific PHY parameters and function pointers.
221 static s32
e1000_init_phy_params_ich8lan(struct e1000_hw
*hw
)
223 struct e1000_phy_info
*phy
= &hw
->phy
;
228 phy
->reset_delay_us
= 100;
231 * We may need to do this twice - once for IGP and if that fails,
232 * we'll set BM func pointers and try again
234 ret_val
= e1000e_determine_phy_address(hw
);
236 hw
->phy
.ops
.write_phy_reg
= e1000e_write_phy_reg_bm
;
237 hw
->phy
.ops
.read_phy_reg
= e1000e_read_phy_reg_bm
;
238 ret_val
= e1000e_determine_phy_address(hw
);
244 while ((e1000_phy_unknown
== e1000e_get_phy_type_from_id(phy
->id
)) &&
247 ret_val
= e1000e_get_phy_id(hw
);
254 case IGP03E1000_E_PHY_ID
:
255 phy
->type
= e1000_phy_igp_3
;
256 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
259 case IFE_PLUS_E_PHY_ID
:
261 phy
->type
= e1000_phy_ife
;
262 phy
->autoneg_mask
= E1000_ALL_NOT_GIG
;
264 case BME1000_E_PHY_ID
:
265 phy
->type
= e1000_phy_bm
;
266 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
267 hw
->phy
.ops
.read_phy_reg
= e1000e_read_phy_reg_bm
;
268 hw
->phy
.ops
.write_phy_reg
= e1000e_write_phy_reg_bm
;
269 hw
->phy
.ops
.commit_phy
= e1000e_phy_sw_reset
;
272 return -E1000_ERR_PHY
;
280 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
281 * @hw: pointer to the HW structure
283 * Initialize family-specific NVM parameters and function
286 static s32
e1000_init_nvm_params_ich8lan(struct e1000_hw
*hw
)
288 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
289 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
291 u32 sector_base_addr
;
295 /* Can't read flash registers if the register set isn't mapped. */
296 if (!hw
->flash_address
) {
297 hw_dbg(hw
, "ERROR: Flash registers not mapped\n");
298 return -E1000_ERR_CONFIG
;
301 nvm
->type
= e1000_nvm_flash_sw
;
303 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
306 * sector_X_addr is a "sector"-aligned address (4096 bytes)
307 * Add 1 to sector_end_addr since this sector is included in
310 sector_base_addr
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
311 sector_end_addr
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
) + 1;
313 /* flash_base_addr is byte-aligned */
314 nvm
->flash_base_addr
= sector_base_addr
<< FLASH_SECTOR_ADDR_SHIFT
;
317 * find total size of the NVM, then cut in half since the total
318 * size represents two separate NVM banks.
320 nvm
->flash_bank_size
= (sector_end_addr
- sector_base_addr
)
321 << FLASH_SECTOR_ADDR_SHIFT
;
322 nvm
->flash_bank_size
/= 2;
323 /* Adjust to word count */
324 nvm
->flash_bank_size
/= sizeof(u16
);
326 nvm
->word_size
= E1000_ICH8_SHADOW_RAM_WORDS
;
328 /* Clear shadow ram */
329 for (i
= 0; i
< nvm
->word_size
; i
++) {
330 dev_spec
->shadow_ram
[i
].modified
= 0;
331 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
338 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
339 * @hw: pointer to the HW structure
341 * Initialize family-specific MAC parameters and function
344 static s32
e1000_init_mac_params_ich8lan(struct e1000_adapter
*adapter
)
346 struct e1000_hw
*hw
= &adapter
->hw
;
347 struct e1000_mac_info
*mac
= &hw
->mac
;
349 /* Set media type function pointer */
350 hw
->phy
.media_type
= e1000_media_type_copper
;
352 /* Set mta register count */
353 mac
->mta_reg_count
= 32;
354 /* Set rar entry count */
355 mac
->rar_entry_count
= E1000_ICH_RAR_ENTRIES
;
356 if (mac
->type
== e1000_ich8lan
)
357 mac
->rar_entry_count
--;
358 /* Set if manageability features are enabled. */
359 mac
->arc_subsystem_valid
= 1;
361 /* Enable PCS Lock-loss workaround for ICH8 */
362 if (mac
->type
== e1000_ich8lan
)
363 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw
, 1);
368 static s32
e1000_get_variants_ich8lan(struct e1000_adapter
*adapter
)
370 struct e1000_hw
*hw
= &adapter
->hw
;
373 rc
= e1000_init_mac_params_ich8lan(adapter
);
377 rc
= e1000_init_nvm_params_ich8lan(hw
);
381 rc
= e1000_init_phy_params_ich8lan(hw
);
385 if ((adapter
->hw
.mac
.type
== e1000_ich8lan
) &&
386 (adapter
->hw
.phy
.type
== e1000_phy_igp_3
))
387 adapter
->flags
|= FLAG_LSC_GIG_SPEED_DROP
;
392 static DEFINE_MUTEX(nvm_mutex
);
393 static pid_t nvm_owner_pid
= -1;
394 static char nvm_owner_name
[TASK_COMM_LEN
] = "";
397 * e1000_acquire_swflag_ich8lan - Acquire software control flag
398 * @hw: pointer to the HW structure
400 * Acquires the software control flag for performing NVM and PHY
401 * operations. This is a function pointer entry point only called by
402 * read/write routines for the PHY and NVM parts.
404 static s32
e1000_acquire_swflag_ich8lan(struct e1000_hw
*hw
)
407 u32 timeout
= PHY_CFG_TIMEOUT
;
411 if (!mutex_trylock(&nvm_mutex
)) {
412 WARN(1, KERN_ERR
"e1000e mutex contention. Owned by process "
413 "%s (pid %d), required by process %s (pid %d)\n",
414 nvm_owner_name
, nvm_owner_pid
,
415 current
->comm
, current
->pid
);
417 mutex_lock(&nvm_mutex
);
419 nvm_owner_pid
= current
->pid
;
420 strncpy(nvm_owner_name
, current
->comm
, TASK_COMM_LEN
);
423 extcnf_ctrl
= er32(EXTCNF_CTRL
);
424 extcnf_ctrl
|= E1000_EXTCNF_CTRL_SWFLAG
;
425 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
427 extcnf_ctrl
= er32(EXTCNF_CTRL
);
428 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
)
435 hw_dbg(hw
, "FW or HW has locked the resource for too long.\n");
436 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
437 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
439 strcpy(nvm_owner_name
, "");
440 mutex_unlock(&nvm_mutex
);
441 return -E1000_ERR_CONFIG
;
448 * e1000_release_swflag_ich8lan - Release software control flag
449 * @hw: pointer to the HW structure
451 * Releases the software control flag for performing NVM and PHY operations.
452 * This is a function pointer entry point only called by read/write
453 * routines for the PHY and NVM parts.
455 static void e1000_release_swflag_ich8lan(struct e1000_hw
*hw
)
459 extcnf_ctrl
= er32(EXTCNF_CTRL
);
460 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
461 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
464 strcpy(nvm_owner_name
, "");
465 mutex_unlock(&nvm_mutex
);
469 * e1000_check_mng_mode_ich8lan - Checks management mode
470 * @hw: pointer to the HW structure
472 * This checks if the adapter has manageability enabled.
473 * This is a function pointer entry point only called by read/write
474 * routines for the PHY and NVM parts.
476 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
)
478 u32 fwsm
= er32(FWSM
);
480 return (fwsm
& E1000_FWSM_MODE_MASK
) ==
481 (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
);
485 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
486 * @hw: pointer to the HW structure
488 * Checks if firmware is blocking the reset of the PHY.
489 * This is a function pointer entry point only called by
492 static s32
e1000_check_reset_block_ich8lan(struct e1000_hw
*hw
)
498 return (fwsm
& E1000_ICH_FWSM_RSPCIPHY
) ? 0 : E1000_BLK_PHY_RESET
;
502 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
503 * @hw: pointer to the HW structure
505 * Forces the speed and duplex settings of the PHY.
506 * This is a function pointer entry point only called by
507 * PHY setup routines.
509 static s32
e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw
*hw
)
511 struct e1000_phy_info
*phy
= &hw
->phy
;
516 if (phy
->type
!= e1000_phy_ife
) {
517 ret_val
= e1000e_phy_force_speed_duplex_igp(hw
);
521 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &data
);
525 e1000e_phy_force_speed_duplex_setup(hw
, &data
);
527 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, data
);
531 /* Disable MDI-X support for 10/100 */
532 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
536 data
&= ~IFE_PMC_AUTO_MDIX
;
537 data
&= ~IFE_PMC_FORCE_MDIX
;
539 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, data
);
543 hw_dbg(hw
, "IFE PMC: %X\n", data
);
547 if (phy
->autoneg_wait_to_complete
) {
548 hw_dbg(hw
, "Waiting for forced speed/duplex link on IFE phy.\n");
550 ret_val
= e1000e_phy_has_link_generic(hw
,
558 hw_dbg(hw
, "Link taking longer than expected.\n");
561 ret_val
= e1000e_phy_has_link_generic(hw
,
573 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
574 * @hw: pointer to the HW structure
577 * This is a function pointer entry point called by drivers
578 * or other shared routines.
580 static s32
e1000_phy_hw_reset_ich8lan(struct e1000_hw
*hw
)
582 struct e1000_phy_info
*phy
= &hw
->phy
;
584 u32 data
, cnf_size
, cnf_base_addr
, sw_cfg_mask
;
586 u16 loop
= E1000_ICH8_LAN_INIT_TIMEOUT
;
587 u16 word_addr
, reg_data
, reg_addr
, phy_page
= 0;
589 ret_val
= e1000e_phy_hw_reset_generic(hw
);
594 * Initialize the PHY from the NVM on ICH platforms. This
595 * is needed due to an issue where the NVM configuration is
596 * not properly autoloaded after power transitions.
597 * Therefore, after each PHY reset, we will load the
598 * configuration data out of the NVM manually.
600 if (hw
->mac
.type
== e1000_ich8lan
&& phy
->type
== e1000_phy_igp_3
) {
601 struct e1000_adapter
*adapter
= hw
->adapter
;
603 /* Check if SW needs configure the PHY */
604 if ((adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_M_AMT
) ||
605 (adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_M
))
606 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG_ICH8M
;
608 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG
;
610 data
= er32(FEXTNVM
);
611 if (!(data
& sw_cfg_mask
))
614 /* Wait for basic configuration completes before proceeding*/
617 data
&= E1000_STATUS_LAN_INIT_DONE
;
619 } while ((!data
) && --loop
);
622 * If basic configuration is incomplete before the above loop
623 * count reaches 0, loading the configuration from NVM will
624 * leave the PHY in a bad state possibly resulting in no link.
627 hw_dbg(hw
, "LAN_INIT_DONE not set, increase timeout\n");
630 /* Clear the Init Done bit for the next init event */
632 data
&= ~E1000_STATUS_LAN_INIT_DONE
;
636 * Make sure HW does not configure LCD from PHY
637 * extended configuration before SW configuration
639 data
= er32(EXTCNF_CTRL
);
640 if (data
& E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE
)
643 cnf_size
= er32(EXTCNF_SIZE
);
644 cnf_size
&= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK
;
645 cnf_size
>>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT
;
649 cnf_base_addr
= data
& E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK
;
650 cnf_base_addr
>>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT
;
652 /* Configure LCD from extended configuration region. */
654 /* cnf_base_addr is in DWORD */
655 word_addr
= (u16
)(cnf_base_addr
<< 1);
657 for (i
= 0; i
< cnf_size
; i
++) {
658 ret_val
= e1000_read_nvm(hw
,
665 ret_val
= e1000_read_nvm(hw
,
666 (word_addr
+ i
* 2 + 1),
672 /* Save off the PHY page for future writes. */
673 if (reg_addr
== IGP01E1000_PHY_PAGE_SELECT
) {
678 reg_addr
|= phy_page
;
680 ret_val
= e1e_wphy(hw
, (u32
)reg_addr
, reg_data
);
690 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
691 * @hw: pointer to the HW structure
693 * Populates "phy" structure with various feature states.
694 * This function is only called by other family-specific
697 static s32
e1000_get_phy_info_ife_ich8lan(struct e1000_hw
*hw
)
699 struct e1000_phy_info
*phy
= &hw
->phy
;
704 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
709 hw_dbg(hw
, "Phy info is only valid if link is up\n");
710 return -E1000_ERR_CONFIG
;
713 ret_val
= e1e_rphy(hw
, IFE_PHY_SPECIAL_CONTROL
, &data
);
716 phy
->polarity_correction
= (!(data
& IFE_PSC_AUTO_POLARITY_DISABLE
));
718 if (phy
->polarity_correction
) {
719 ret_val
= e1000_check_polarity_ife_ich8lan(hw
);
723 /* Polarity is forced */
724 phy
->cable_polarity
= (data
& IFE_PSC_FORCE_POLARITY
)
725 ? e1000_rev_polarity_reversed
726 : e1000_rev_polarity_normal
;
729 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
733 phy
->is_mdix
= (data
& IFE_PMC_MDIX_STATUS
);
735 /* The following parameters are undefined for 10/100 operation. */
736 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
737 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
738 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
744 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
745 * @hw: pointer to the HW structure
747 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
748 * This is a function pointer entry point called by drivers
749 * or other shared routines.
751 static s32
e1000_get_phy_info_ich8lan(struct e1000_hw
*hw
)
753 switch (hw
->phy
.type
) {
755 return e1000_get_phy_info_ife_ich8lan(hw
);
757 case e1000_phy_igp_3
:
759 return e1000e_get_phy_info_igp(hw
);
765 return -E1000_ERR_PHY_TYPE
;
769 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
770 * @hw: pointer to the HW structure
772 * Polarity is determined on the polarity reversal feature being enabled.
773 * This function is only called by other family-specific
776 static s32
e1000_check_polarity_ife_ich8lan(struct e1000_hw
*hw
)
778 struct e1000_phy_info
*phy
= &hw
->phy
;
780 u16 phy_data
, offset
, mask
;
783 * Polarity is determined based on the reversal feature being enabled.
785 if (phy
->polarity_correction
) {
786 offset
= IFE_PHY_EXTENDED_STATUS_CONTROL
;
787 mask
= IFE_PESC_POLARITY_REVERSED
;
789 offset
= IFE_PHY_SPECIAL_CONTROL
;
790 mask
= IFE_PSC_FORCE_POLARITY
;
793 ret_val
= e1e_rphy(hw
, offset
, &phy_data
);
796 phy
->cable_polarity
= (phy_data
& mask
)
797 ? e1000_rev_polarity_reversed
798 : e1000_rev_polarity_normal
;
804 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
805 * @hw: pointer to the HW structure
806 * @active: TRUE to enable LPLU, FALSE to disable
808 * Sets the LPLU D0 state according to the active flag. When
809 * activating LPLU this function also disables smart speed
810 * and vice versa. LPLU will not be activated unless the
811 * device autonegotiation advertisement meets standards of
812 * either 10 or 10/100 or 10/100/1000 at all duplexes.
813 * This is a function pointer entry point only called by
814 * PHY setup routines.
816 static s32
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
818 struct e1000_phy_info
*phy
= &hw
->phy
;
823 if (phy
->type
== e1000_phy_ife
)
826 phy_ctrl
= er32(PHY_CTRL
);
829 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
;
830 ew32(PHY_CTRL
, phy_ctrl
);
833 * Call gig speed drop workaround on LPLU before accessing
836 if ((hw
->mac
.type
== e1000_ich8lan
) &&
837 (hw
->phy
.type
== e1000_phy_igp_3
))
838 e1000e_gig_downshift_workaround_ich8lan(hw
);
840 /* When LPLU is enabled, we should disable SmartSpeed */
841 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
842 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
843 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
847 phy_ctrl
&= ~E1000_PHY_CTRL_D0A_LPLU
;
848 ew32(PHY_CTRL
, phy_ctrl
);
851 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
852 * during Dx states where the power conservation is most
853 * important. During driver activity we should enable
854 * SmartSpeed, so performance is maintained.
856 if (phy
->smart_speed
== e1000_smart_speed_on
) {
857 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
862 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
863 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
867 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
868 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
873 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
874 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
885 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
886 * @hw: pointer to the HW structure
887 * @active: TRUE to enable LPLU, FALSE to disable
889 * Sets the LPLU D3 state according to the active flag. When
890 * activating LPLU this function also disables smart speed
891 * and vice versa. LPLU will not be activated unless the
892 * device autonegotiation advertisement meets standards of
893 * either 10 or 10/100 or 10/100/1000 at all duplexes.
894 * This is a function pointer entry point only called by
895 * PHY setup routines.
897 static s32
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
899 struct e1000_phy_info
*phy
= &hw
->phy
;
904 phy_ctrl
= er32(PHY_CTRL
);
907 phy_ctrl
&= ~E1000_PHY_CTRL_NOND0A_LPLU
;
908 ew32(PHY_CTRL
, phy_ctrl
);
910 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
911 * during Dx states where the power conservation is most
912 * important. During driver activity we should enable
913 * SmartSpeed, so performance is maintained.
915 if (phy
->smart_speed
== e1000_smart_speed_on
) {
916 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
921 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
922 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
926 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
927 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
932 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
933 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
938 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
939 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
940 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
941 phy_ctrl
|= E1000_PHY_CTRL_NOND0A_LPLU
;
942 ew32(PHY_CTRL
, phy_ctrl
);
945 * Call gig speed drop workaround on LPLU before accessing
948 if ((hw
->mac
.type
== e1000_ich8lan
) &&
949 (hw
->phy
.type
== e1000_phy_igp_3
))
950 e1000e_gig_downshift_workaround_ich8lan(hw
);
952 /* When LPLU is enabled, we should disable SmartSpeed */
953 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
957 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
958 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
965 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
966 * @hw: pointer to the HW structure
967 * @bank: pointer to the variable that returns the active bank
969 * Reads signature byte from the NVM using the flash access registers.
970 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
972 static s32
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw
*hw
, u32
*bank
)
975 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
976 u32 bank1_offset
= nvm
->flash_bank_size
* sizeof(u16
);
977 u32 act_offset
= E1000_ICH_NVM_SIG_WORD
* 2 + 1;
981 switch (hw
->mac
.type
) {
985 if ((eecd
& E1000_EECD_SEC1VAL_VALID_MASK
) ==
986 E1000_EECD_SEC1VAL_VALID_MASK
) {
987 if (eecd
& E1000_EECD_SEC1VAL
)
994 hw_dbg(hw
, "Unable to determine valid NVM bank via EEC - "
995 "reading flash signature\n");
998 /* set bank to 0 in case flash read fails */
1002 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
,
1006 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
1007 E1000_ICH_NVM_SIG_VALUE
) {
1013 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
+
1018 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
1019 E1000_ICH_NVM_SIG_VALUE
) {
1024 hw_dbg(hw
, "ERROR: No valid NVM bank present\n");
1025 return -E1000_ERR_NVM
;
1032 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1033 * @hw: pointer to the HW structure
1034 * @offset: The offset (in bytes) of the word(s) to read.
1035 * @words: Size of data to read in words
1036 * @data: Pointer to the word(s) to read at offset.
1038 * Reads a word(s) from the NVM using the flash access registers.
1040 static s32
e1000_read_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
1043 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1044 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1050 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
1052 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
1053 return -E1000_ERR_NVM
;
1056 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1060 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
1064 act_offset
= (bank
) ? nvm
->flash_bank_size
: 0;
1065 act_offset
+= offset
;
1067 for (i
= 0; i
< words
; i
++) {
1068 if ((dev_spec
->shadow_ram
) &&
1069 (dev_spec
->shadow_ram
[offset
+i
].modified
)) {
1070 data
[i
] = dev_spec
->shadow_ram
[offset
+i
].value
;
1072 ret_val
= e1000_read_flash_word_ich8lan(hw
,
1082 e1000_release_swflag_ich8lan(hw
);
1086 hw_dbg(hw
, "NVM read error: %d\n", ret_val
);
1092 * e1000_flash_cycle_init_ich8lan - Initialize flash
1093 * @hw: pointer to the HW structure
1095 * This function does initial flash setup so that a new read/write/erase cycle
1098 static s32
e1000_flash_cycle_init_ich8lan(struct e1000_hw
*hw
)
1100 union ich8_hws_flash_status hsfsts
;
1101 s32 ret_val
= -E1000_ERR_NVM
;
1104 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1106 /* Check if the flash descriptor is valid */
1107 if (hsfsts
.hsf_status
.fldesvalid
== 0) {
1108 hw_dbg(hw
, "Flash descriptor invalid. "
1109 "SW Sequencing must be used.");
1110 return -E1000_ERR_NVM
;
1113 /* Clear FCERR and DAEL in hw status by writing 1 */
1114 hsfsts
.hsf_status
.flcerr
= 1;
1115 hsfsts
.hsf_status
.dael
= 1;
1117 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1120 * Either we should have a hardware SPI cycle in progress
1121 * bit to check against, in order to start a new cycle or
1122 * FDONE bit should be changed in the hardware so that it
1123 * is 1 after hardware reset, which can then be used as an
1124 * indication whether a cycle is in progress or has been
1128 if (hsfsts
.hsf_status
.flcinprog
== 0) {
1130 * There is no cycle running at present,
1131 * so we can start a cycle
1132 * Begin by setting Flash Cycle Done.
1134 hsfsts
.hsf_status
.flcdone
= 1;
1135 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1139 * otherwise poll for sometime so the current
1140 * cycle has a chance to end before giving up.
1142 for (i
= 0; i
< ICH_FLASH_READ_COMMAND_TIMEOUT
; i
++) {
1143 hsfsts
.regval
= __er16flash(hw
, ICH_FLASH_HSFSTS
);
1144 if (hsfsts
.hsf_status
.flcinprog
== 0) {
1152 * Successful in waiting for previous cycle to timeout,
1153 * now set the Flash Cycle Done.
1155 hsfsts
.hsf_status
.flcdone
= 1;
1156 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1158 hw_dbg(hw
, "Flash controller busy, cannot get access");
1166 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1167 * @hw: pointer to the HW structure
1168 * @timeout: maximum time to wait for completion
1170 * This function starts a flash cycle and waits for its completion.
1172 static s32
e1000_flash_cycle_ich8lan(struct e1000_hw
*hw
, u32 timeout
)
1174 union ich8_hws_flash_ctrl hsflctl
;
1175 union ich8_hws_flash_status hsfsts
;
1176 s32 ret_val
= -E1000_ERR_NVM
;
1179 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1180 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1181 hsflctl
.hsf_ctrl
.flcgo
= 1;
1182 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1184 /* wait till FDONE bit is set to 1 */
1186 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1187 if (hsfsts
.hsf_status
.flcdone
== 1)
1190 } while (i
++ < timeout
);
1192 if (hsfsts
.hsf_status
.flcdone
== 1 && hsfsts
.hsf_status
.flcerr
== 0)
1199 * e1000_read_flash_word_ich8lan - Read word from flash
1200 * @hw: pointer to the HW structure
1201 * @offset: offset to data location
1202 * @data: pointer to the location for storing the data
1204 * Reads the flash word at offset into data. Offset is converted
1205 * to bytes before read.
1207 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1210 /* Must convert offset into bytes. */
1213 return e1000_read_flash_data_ich8lan(hw
, offset
, 2, data
);
1217 * e1000_read_flash_byte_ich8lan - Read byte from flash
1218 * @hw: pointer to the HW structure
1219 * @offset: The offset of the byte to read.
1220 * @data: Pointer to a byte to store the value read.
1222 * Reads a single byte from the NVM using the flash access registers.
1224 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1230 ret_val
= e1000_read_flash_data_ich8lan(hw
, offset
, 1, &word
);
1240 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1241 * @hw: pointer to the HW structure
1242 * @offset: The offset (in bytes) of the byte or word to read.
1243 * @size: Size of data to read, 1=byte 2=word
1244 * @data: Pointer to the word to store the value read.
1246 * Reads a byte or word from the NVM using the flash access registers.
1248 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1251 union ich8_hws_flash_status hsfsts
;
1252 union ich8_hws_flash_ctrl hsflctl
;
1253 u32 flash_linear_addr
;
1255 s32 ret_val
= -E1000_ERR_NVM
;
1258 if (size
< 1 || size
> 2 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
1259 return -E1000_ERR_NVM
;
1261 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
1262 hw
->nvm
.flash_base_addr
;
1267 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1271 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1272 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1273 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
1274 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_READ
;
1275 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1277 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1279 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1280 ICH_FLASH_READ_COMMAND_TIMEOUT
);
1283 * Check if FCERR is set to 1, if set to 1, clear it
1284 * and try the whole sequence a few more times, else
1285 * read in (shift in) the Flash Data0, the order is
1286 * least significant byte first msb to lsb
1289 flash_data
= er32flash(ICH_FLASH_FDATA0
);
1291 *data
= (u8
)(flash_data
& 0x000000FF);
1292 } else if (size
== 2) {
1293 *data
= (u16
)(flash_data
& 0x0000FFFF);
1298 * If we've gotten here, then things are probably
1299 * completely hosed, but if the error condition is
1300 * detected, it won't hurt to give it another try...
1301 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1303 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1304 if (hsfsts
.hsf_status
.flcerr
== 1) {
1305 /* Repeat for some time before giving up. */
1307 } else if (hsfsts
.hsf_status
.flcdone
== 0) {
1308 hw_dbg(hw
, "Timeout error - flash cycle "
1309 "did not complete.");
1313 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
1319 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1320 * @hw: pointer to the HW structure
1321 * @offset: The offset (in bytes) of the word(s) to write.
1322 * @words: Size of data to write in words
1323 * @data: Pointer to the word(s) to write at offset.
1325 * Writes a byte or word to the NVM using the flash access registers.
1327 static s32
e1000_write_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
1330 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1331 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1335 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
1337 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
1338 return -E1000_ERR_NVM
;
1341 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1345 for (i
= 0; i
< words
; i
++) {
1346 dev_spec
->shadow_ram
[offset
+i
].modified
= 1;
1347 dev_spec
->shadow_ram
[offset
+i
].value
= data
[i
];
1350 e1000_release_swflag_ich8lan(hw
);
1356 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1357 * @hw: pointer to the HW structure
1359 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1360 * which writes the checksum to the shadow ram. The changes in the shadow
1361 * ram are then committed to the EEPROM by processing each bank at a time
1362 * checking for the modified bit and writing only the pending changes.
1363 * After a successful commit, the shadow ram is cleared and is ready for
1366 static s32
e1000_update_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
1368 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1369 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1370 u32 i
, act_offset
, new_bank_offset
, old_bank_offset
, bank
;
1374 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
1378 if (nvm
->type
!= e1000_nvm_flash_sw
)
1381 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1386 * We're writing to the opposite bank so if we're on bank 1,
1387 * write to bank 0 etc. We also need to erase the segment that
1388 * is going to be written
1390 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
1392 e1000_release_swflag_ich8lan(hw
);
1397 new_bank_offset
= nvm
->flash_bank_size
;
1398 old_bank_offset
= 0;
1399 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 1);
1401 e1000_release_swflag_ich8lan(hw
);
1405 old_bank_offset
= nvm
->flash_bank_size
;
1406 new_bank_offset
= 0;
1407 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 0);
1409 e1000_release_swflag_ich8lan(hw
);
1414 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
1416 * Determine whether to write the value stored
1417 * in the other NVM bank or a modified value stored
1420 if (dev_spec
->shadow_ram
[i
].modified
) {
1421 data
= dev_spec
->shadow_ram
[i
].value
;
1423 ret_val
= e1000_read_flash_word_ich8lan(hw
, i
+
1431 * If the word is 0x13, then make sure the signature bits
1432 * (15:14) are 11b until the commit has completed.
1433 * This will allow us to write 10b which indicates the
1434 * signature is valid. We want to do this after the write
1435 * has completed so that we don't mark the segment valid
1436 * while the write is still in progress
1438 if (i
== E1000_ICH_NVM_SIG_WORD
)
1439 data
|= E1000_ICH_NVM_SIG_MASK
;
1441 /* Convert offset to bytes. */
1442 act_offset
= (i
+ new_bank_offset
) << 1;
1445 /* Write the bytes to the new bank. */
1446 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1453 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1461 * Don't bother writing the segment valid bits if sector
1462 * programming failed.
1465 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1466 hw_dbg(hw
, "Flash commit failed.\n");
1467 e1000_release_swflag_ich8lan(hw
);
1472 * Finally validate the new segment by setting bit 15:14
1473 * to 10b in word 0x13 , this can be done without an
1474 * erase as well since these bits are 11 to start with
1475 * and we need to change bit 14 to 0b
1477 act_offset
= new_bank_offset
+ E1000_ICH_NVM_SIG_WORD
;
1478 ret_val
= e1000_read_flash_word_ich8lan(hw
, act_offset
, &data
);
1480 e1000_release_swflag_ich8lan(hw
);
1484 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1488 e1000_release_swflag_ich8lan(hw
);
1493 * And invalidate the previously valid segment by setting
1494 * its signature word (0x13) high_byte to 0b. This can be
1495 * done without an erase because flash erase sets all bits
1496 * to 1's. We can write 1's to 0's without an erase
1498 act_offset
= (old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
) * 2 + 1;
1499 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
, act_offset
, 0);
1501 e1000_release_swflag_ich8lan(hw
);
1505 /* Great! Everything worked, we can now clear the cached entries. */
1506 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
1507 dev_spec
->shadow_ram
[i
].modified
= 0;
1508 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
1511 e1000_release_swflag_ich8lan(hw
);
1514 * Reload the EEPROM, or else modifications will not appear
1515 * until after the next adapter reset.
1517 e1000e_reload_nvm(hw
);
1522 hw_dbg(hw
, "NVM update error: %d\n", ret_val
);
1528 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1529 * @hw: pointer to the HW structure
1531 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1532 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1533 * calculated, in which case we need to calculate the checksum and set bit 6.
1535 static s32
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
1541 * Read 0x19 and check bit 6. If this bit is 0, the checksum
1542 * needs to be fixed. This bit is an indication that the NVM
1543 * was prepared by OEM software and did not calculate the
1544 * checksum...a likely scenario.
1546 ret_val
= e1000_read_nvm(hw
, 0x19, 1, &data
);
1550 if ((data
& 0x40) == 0) {
1552 ret_val
= e1000_write_nvm(hw
, 0x19, 1, &data
);
1555 ret_val
= e1000e_update_nvm_checksum(hw
);
1560 return e1000e_validate_nvm_checksum_generic(hw
);
1564 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1565 * @hw: pointer to the HW structure
1567 * To prevent malicious write/erase of the NVM, set it to be read-only
1568 * so that the hardware ignores all write/erase cycles of the NVM via
1569 * the flash control registers. The shadow-ram copy of the NVM will
1570 * still be updated, however any updates to this copy will not stick
1571 * across driver reloads.
1573 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw
*hw
)
1575 union ich8_flash_protected_range pr0
;
1576 union ich8_hws_flash_status hsfsts
;
1580 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1584 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
1586 /* Write-protect GbE Sector of NVM */
1587 pr0
.regval
= er32flash(ICH_FLASH_PR0
);
1588 pr0
.range
.base
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
1589 pr0
.range
.limit
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
);
1590 pr0
.range
.wpe
= true;
1591 ew32flash(ICH_FLASH_PR0
, pr0
.regval
);
1594 * Lock down a subset of GbE Flash Control Registers, e.g.
1595 * PR0 to prevent the write-protection from being lifted.
1596 * Once FLOCKDN is set, the registers protected by it cannot
1597 * be written until FLOCKDN is cleared by a hardware reset.
1599 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1600 hsfsts
.hsf_status
.flockdn
= true;
1601 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1603 e1000_release_swflag_ich8lan(hw
);
1607 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1608 * @hw: pointer to the HW structure
1609 * @offset: The offset (in bytes) of the byte/word to read.
1610 * @size: Size of data to read, 1=byte 2=word
1611 * @data: The byte(s) to write to the NVM.
1613 * Writes one/two bytes to the NVM using the flash access registers.
1615 static s32
e1000_write_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1618 union ich8_hws_flash_status hsfsts
;
1619 union ich8_hws_flash_ctrl hsflctl
;
1620 u32 flash_linear_addr
;
1625 if (size
< 1 || size
> 2 || data
> size
* 0xff ||
1626 offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
1627 return -E1000_ERR_NVM
;
1629 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
1630 hw
->nvm
.flash_base_addr
;
1635 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1639 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1640 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1641 hsflctl
.hsf_ctrl
.fldbcount
= size
-1;
1642 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_WRITE
;
1643 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1645 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1648 flash_data
= (u32
)data
& 0x00FF;
1650 flash_data
= (u32
)data
;
1652 ew32flash(ICH_FLASH_FDATA0
, flash_data
);
1655 * check if FCERR is set to 1 , if set to 1, clear it
1656 * and try the whole sequence a few more times else done
1658 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1659 ICH_FLASH_WRITE_COMMAND_TIMEOUT
);
1664 * If we're here, then things are most likely
1665 * completely hosed, but if the error condition
1666 * is detected, it won't hurt to give it another
1667 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1669 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1670 if (hsfsts
.hsf_status
.flcerr
== 1)
1671 /* Repeat for some time before giving up. */
1673 if (hsfsts
.hsf_status
.flcdone
== 0) {
1674 hw_dbg(hw
, "Timeout error - flash cycle "
1675 "did not complete.");
1678 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
1684 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1685 * @hw: pointer to the HW structure
1686 * @offset: The index of the byte to read.
1687 * @data: The byte to write to the NVM.
1689 * Writes a single byte to the NVM using the flash access registers.
1691 static s32
e1000_write_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1694 u16 word
= (u16
)data
;
1696 return e1000_write_flash_data_ich8lan(hw
, offset
, 1, word
);
1700 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1701 * @hw: pointer to the HW structure
1702 * @offset: The offset of the byte to write.
1703 * @byte: The byte to write to the NVM.
1705 * Writes a single byte to the NVM using the flash access registers.
1706 * Goes through a retry algorithm before giving up.
1708 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
1709 u32 offset
, u8 byte
)
1712 u16 program_retries
;
1714 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
1718 for (program_retries
= 0; program_retries
< 100; program_retries
++) {
1719 hw_dbg(hw
, "Retrying Byte %2.2X at offset %u\n", byte
, offset
);
1721 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
1725 if (program_retries
== 100)
1726 return -E1000_ERR_NVM
;
1732 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1733 * @hw: pointer to the HW structure
1734 * @bank: 0 for first bank, 1 for second bank, etc.
1736 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1737 * bank N is 4096 * N + flash_reg_addr.
1739 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
)
1741 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1742 union ich8_hws_flash_status hsfsts
;
1743 union ich8_hws_flash_ctrl hsflctl
;
1744 u32 flash_linear_addr
;
1745 /* bank size is in 16bit words - adjust to bytes */
1746 u32 flash_bank_size
= nvm
->flash_bank_size
* 2;
1753 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1756 * Determine HW Sector size: Read BERASE bits of hw flash status
1758 * 00: The Hw sector is 256 bytes, hence we need to erase 16
1759 * consecutive sectors. The start index for the nth Hw sector
1760 * can be calculated as = bank * 4096 + n * 256
1761 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1762 * The start index for the nth Hw sector can be calculated
1764 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1765 * (ich9 only, otherwise error condition)
1766 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1768 switch (hsfsts
.hsf_status
.berasesz
) {
1770 /* Hw sector size 256 */
1771 sector_size
= ICH_FLASH_SEG_SIZE_256
;
1772 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_256
;
1775 sector_size
= ICH_FLASH_SEG_SIZE_4K
;
1776 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_4K
;
1779 if (hw
->mac
.type
== e1000_ich9lan
) {
1780 sector_size
= ICH_FLASH_SEG_SIZE_8K
;
1781 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_8K
;
1783 return -E1000_ERR_NVM
;
1787 sector_size
= ICH_FLASH_SEG_SIZE_64K
;
1788 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_64K
;
1791 return -E1000_ERR_NVM
;
1794 /* Start with the base address, then add the sector offset. */
1795 flash_linear_addr
= hw
->nvm
.flash_base_addr
;
1796 flash_linear_addr
+= (bank
) ? (sector_size
* iteration
) : 0;
1798 for (j
= 0; j
< iteration
; j
++) {
1801 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1806 * Write a value 11 (block Erase) in Flash
1807 * Cycle field in hw flash control
1809 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1810 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_ERASE
;
1811 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1814 * Write the last 24 bits of an index within the
1815 * block into Flash Linear address field in Flash
1818 flash_linear_addr
+= (j
* sector_size
);
1819 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1821 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1822 ICH_FLASH_ERASE_COMMAND_TIMEOUT
);
1827 * Check if FCERR is set to 1. If 1,
1828 * clear it and try the whole sequence
1829 * a few more times else Done
1831 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1832 if (hsfsts
.hsf_status
.flcerr
== 1)
1833 /* repeat for some time before giving up */
1835 else if (hsfsts
.hsf_status
.flcdone
== 0)
1837 } while (++count
< ICH_FLASH_CYCLE_REPEAT_COUNT
);
1844 * e1000_valid_led_default_ich8lan - Set the default LED settings
1845 * @hw: pointer to the HW structure
1846 * @data: Pointer to the LED settings
1848 * Reads the LED default settings from the NVM to data. If the NVM LED
1849 * settings is all 0's or F's, set the LED default to a valid LED default
1852 static s32
e1000_valid_led_default_ich8lan(struct e1000_hw
*hw
, u16
*data
)
1856 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1858 hw_dbg(hw
, "NVM Read Error\n");
1862 if (*data
== ID_LED_RESERVED_0000
||
1863 *data
== ID_LED_RESERVED_FFFF
)
1864 *data
= ID_LED_DEFAULT_ICH8LAN
;
1870 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1871 * @hw: pointer to the HW structure
1873 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1874 * register, so the the bus width is hard coded.
1876 static s32
e1000_get_bus_info_ich8lan(struct e1000_hw
*hw
)
1878 struct e1000_bus_info
*bus
= &hw
->bus
;
1881 ret_val
= e1000e_get_bus_info_pcie(hw
);
1884 * ICH devices are "PCI Express"-ish. They have
1885 * a configuration space, but do not contain
1886 * PCI Express Capability registers, so bus width
1887 * must be hardcoded.
1889 if (bus
->width
== e1000_bus_width_unknown
)
1890 bus
->width
= e1000_bus_width_pcie_x1
;
1896 * e1000_reset_hw_ich8lan - Reset the hardware
1897 * @hw: pointer to the HW structure
1899 * Does a full reset of the hardware which includes a reset of the PHY and
1902 static s32
e1000_reset_hw_ich8lan(struct e1000_hw
*hw
)
1908 * Prevent the PCI-E bus from sticking if there is no TLP connection
1909 * on the last TLP read/write transaction when MAC is reset.
1911 ret_val
= e1000e_disable_pcie_master(hw
);
1913 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
1916 hw_dbg(hw
, "Masking off all interrupts\n");
1917 ew32(IMC
, 0xffffffff);
1920 * Disable the Transmit and Receive units. Then delay to allow
1921 * any pending transactions to complete before we hit the MAC
1922 * with the global reset.
1925 ew32(TCTL
, E1000_TCTL_PSP
);
1930 /* Workaround for ICH8 bit corruption issue in FIFO memory */
1931 if (hw
->mac
.type
== e1000_ich8lan
) {
1932 /* Set Tx and Rx buffer allocation to 8k apiece. */
1933 ew32(PBA
, E1000_PBA_8K
);
1934 /* Set Packet Buffer Size to 16k. */
1935 ew32(PBS
, E1000_PBS_16K
);
1940 if (!e1000_check_reset_block(hw
)) {
1942 * PHY HW reset requires MAC CORE reset at the same
1943 * time to make sure the interface between MAC and the
1944 * external PHY is reset.
1946 ctrl
|= E1000_CTRL_PHY_RST
;
1948 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1949 /* Whether or not the swflag was acquired, we need to reset the part */
1950 hw_dbg(hw
, "Issuing a global reset to ich8lan\n");
1951 ew32(CTRL
, (ctrl
| E1000_CTRL_RST
));
1955 /* release the swflag because it is not reset by
1958 e1000_release_swflag_ich8lan(hw
);
1961 ret_val
= e1000e_get_auto_rd_done(hw
);
1964 * When auto config read does not complete, do not
1965 * return with an error. This can happen in situations
1966 * where there is no eeprom and prevents getting link.
1968 hw_dbg(hw
, "Auto Read Done did not complete\n");
1971 ew32(IMC
, 0xffffffff);
1974 kab
= er32(KABGTXD
);
1975 kab
|= E1000_KABGTXD_BGSQLBIAS
;
1982 * e1000_init_hw_ich8lan - Initialize the hardware
1983 * @hw: pointer to the HW structure
1985 * Prepares the hardware for transmit and receive by doing the following:
1986 * - initialize hardware bits
1987 * - initialize LED identification
1988 * - setup receive address registers
1989 * - setup flow control
1990 * - setup transmit descriptors
1991 * - clear statistics
1993 static s32
e1000_init_hw_ich8lan(struct e1000_hw
*hw
)
1995 struct e1000_mac_info
*mac
= &hw
->mac
;
1996 u32 ctrl_ext
, txdctl
, snoop
;
2000 e1000_initialize_hw_bits_ich8lan(hw
);
2002 /* Initialize identification LED */
2003 ret_val
= e1000e_id_led_init(hw
);
2005 hw_dbg(hw
, "Error initializing identification LED\n");
2009 /* Setup the receive address. */
2010 e1000e_init_rx_addrs(hw
, mac
->rar_entry_count
);
2012 /* Zero out the Multicast HASH table */
2013 hw_dbg(hw
, "Zeroing the MTA\n");
2014 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
2015 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
2017 /* Setup link and flow control */
2018 ret_val
= e1000_setup_link_ich8lan(hw
);
2020 /* Set the transmit descriptor write-back policy for both queues */
2021 txdctl
= er32(TXDCTL(0));
2022 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
2023 E1000_TXDCTL_FULL_TX_DESC_WB
;
2024 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
2025 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
2026 ew32(TXDCTL(0), txdctl
);
2027 txdctl
= er32(TXDCTL(1));
2028 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
2029 E1000_TXDCTL_FULL_TX_DESC_WB
;
2030 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
2031 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
2032 ew32(TXDCTL(1), txdctl
);
2035 * ICH8 has opposite polarity of no_snoop bits.
2036 * By default, we should use snoop behavior.
2038 if (mac
->type
== e1000_ich8lan
)
2039 snoop
= PCIE_ICH8_SNOOP_ALL
;
2041 snoop
= (u32
) ~(PCIE_NO_SNOOP_ALL
);
2042 e1000e_set_pcie_no_snoop(hw
, snoop
);
2044 ctrl_ext
= er32(CTRL_EXT
);
2045 ctrl_ext
|= E1000_CTRL_EXT_RO_DIS
;
2046 ew32(CTRL_EXT
, ctrl_ext
);
2049 * Clear all of the statistics registers (clear on read). It is
2050 * important that we do this after we have tried to establish link
2051 * because the symbol error count will increment wildly if there
2054 e1000_clear_hw_cntrs_ich8lan(hw
);
2059 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2060 * @hw: pointer to the HW structure
2062 * Sets/Clears required hardware bits necessary for correctly setting up the
2063 * hardware for transmit and receive.
2065 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
)
2069 /* Extended Device Control */
2070 reg
= er32(CTRL_EXT
);
2072 ew32(CTRL_EXT
, reg
);
2074 /* Transmit Descriptor Control 0 */
2075 reg
= er32(TXDCTL(0));
2077 ew32(TXDCTL(0), reg
);
2079 /* Transmit Descriptor Control 1 */
2080 reg
= er32(TXDCTL(1));
2082 ew32(TXDCTL(1), reg
);
2084 /* Transmit Arbitration Control 0 */
2085 reg
= er32(TARC(0));
2086 if (hw
->mac
.type
== e1000_ich8lan
)
2087 reg
|= (1 << 28) | (1 << 29);
2088 reg
|= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2091 /* Transmit Arbitration Control 1 */
2092 reg
= er32(TARC(1));
2093 if (er32(TCTL
) & E1000_TCTL_MULR
)
2097 reg
|= (1 << 24) | (1 << 26) | (1 << 30);
2101 if (hw
->mac
.type
== e1000_ich8lan
) {
2109 * e1000_setup_link_ich8lan - Setup flow control and link settings
2110 * @hw: pointer to the HW structure
2112 * Determines which flow control settings to use, then configures flow
2113 * control. Calls the appropriate media-specific link configuration
2114 * function. Assuming the adapter has a valid link partner, a valid link
2115 * should be established. Assumes the hardware has previously been reset
2116 * and the transmitter and receiver are not enabled.
2118 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
)
2122 if (e1000_check_reset_block(hw
))
2126 * ICH parts do not have a word in the NVM to determine
2127 * the default flow control setting, so we explicitly
2130 if (hw
->fc
.requested_mode
== e1000_fc_default
)
2131 hw
->fc
.requested_mode
= e1000_fc_full
;
2134 * Save off the requested flow control mode for use later. Depending
2135 * on the link partner's capabilities, we may or may not use this mode.
2137 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
2139 hw_dbg(hw
, "After fix-ups FlowControl is now = %x\n",
2140 hw
->fc
.current_mode
);
2142 /* Continue to configure the copper link. */
2143 ret_val
= e1000_setup_copper_link_ich8lan(hw
);
2147 ew32(FCTTV
, hw
->fc
.pause_time
);
2149 return e1000e_set_fc_watermarks(hw
);
2153 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2154 * @hw: pointer to the HW structure
2156 * Configures the kumeran interface to the PHY to wait the appropriate time
2157 * when polling the PHY, then call the generic setup_copper_link to finish
2158 * configuring the copper link.
2160 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
)
2167 ctrl
|= E1000_CTRL_SLU
;
2168 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
2172 * Set the mac to wait the maximum time between each iteration
2173 * and increase the max iterations when polling the phy;
2174 * this fixes erroneous timeouts at 10Mbps.
2176 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 4), 0xFFFF);
2179 ret_val
= e1000e_read_kmrn_reg(hw
, GG82563_REG(0x34, 9), ®_data
);
2183 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 9), reg_data
);
2187 if (hw
->phy
.type
== e1000_phy_igp_3
) {
2188 ret_val
= e1000e_copper_link_setup_igp(hw
);
2191 } else if (hw
->phy
.type
== e1000_phy_bm
) {
2192 ret_val
= e1000e_copper_link_setup_m88(hw
);
2197 if (hw
->phy
.type
== e1000_phy_ife
) {
2198 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, ®_data
);
2202 reg_data
&= ~IFE_PMC_AUTO_MDIX
;
2204 switch (hw
->phy
.mdix
) {
2206 reg_data
&= ~IFE_PMC_FORCE_MDIX
;
2209 reg_data
|= IFE_PMC_FORCE_MDIX
;
2213 reg_data
|= IFE_PMC_AUTO_MDIX
;
2216 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, reg_data
);
2220 return e1000e_setup_copper_link(hw
);
2224 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2225 * @hw: pointer to the HW structure
2226 * @speed: pointer to store current link speed
2227 * @duplex: pointer to store the current link duplex
2229 * Calls the generic get_speed_and_duplex to retrieve the current link
2230 * information and then calls the Kumeran lock loss workaround for links at
2233 static s32
e1000_get_link_up_info_ich8lan(struct e1000_hw
*hw
, u16
*speed
,
2238 ret_val
= e1000e_get_speed_and_duplex_copper(hw
, speed
, duplex
);
2242 if ((hw
->mac
.type
== e1000_ich8lan
) &&
2243 (hw
->phy
.type
== e1000_phy_igp_3
) &&
2244 (*speed
== SPEED_1000
)) {
2245 ret_val
= e1000_kmrn_lock_loss_workaround_ich8lan(hw
);
2252 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2253 * @hw: pointer to the HW structure
2255 * Work-around for 82566 Kumeran PCS lock loss:
2256 * On link status change (i.e. PCI reset, speed change) and link is up and
2258 * 0) if workaround is optionally disabled do nothing
2259 * 1) wait 1ms for Kumeran link to come up
2260 * 2) check Kumeran Diagnostic register PCS lock loss bit
2261 * 3) if not set the link is locked (all is good), otherwise...
2263 * 5) repeat up to 10 times
2264 * Note: this is only called for IGP3 copper when speed is 1gb.
2266 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
)
2268 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2274 if (!dev_spec
->kmrn_lock_loss_workaround_enabled
)
2278 * Make sure link is up before proceeding. If not just return.
2279 * Attempting this while link is negotiating fouled up link
2282 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
2286 for (i
= 0; i
< 10; i
++) {
2287 /* read once to clear */
2288 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
2291 /* and again to get new status */
2292 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
2296 /* check for PCS lock */
2297 if (!(data
& IGP3_KMRN_DIAG_PCS_LOCK_LOSS
))
2300 /* Issue PHY reset */
2301 e1000_phy_hw_reset(hw
);
2304 /* Disable GigE link negotiation */
2305 phy_ctrl
= er32(PHY_CTRL
);
2306 phy_ctrl
|= (E1000_PHY_CTRL_GBE_DISABLE
|
2307 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
2308 ew32(PHY_CTRL
, phy_ctrl
);
2311 * Call gig speed drop workaround on Gig disable before accessing
2314 e1000e_gig_downshift_workaround_ich8lan(hw
);
2316 /* unable to acquire PCS lock */
2317 return -E1000_ERR_PHY
;
2321 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2322 * @hw: pointer to the HW structure
2323 * @state: boolean value used to set the current Kumeran workaround state
2325 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
2326 * /disabled - FALSE).
2328 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
,
2331 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2333 if (hw
->mac
.type
!= e1000_ich8lan
) {
2334 hw_dbg(hw
, "Workaround applies to ICH8 only.\n");
2338 dev_spec
->kmrn_lock_loss_workaround_enabled
= state
;
2342 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2343 * @hw: pointer to the HW structure
2345 * Workaround for 82566 power-down on D3 entry:
2346 * 1) disable gigabit link
2347 * 2) write VR power-down enable
2349 * Continue if successful, else issue LCD reset and repeat
2351 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw
*hw
)
2357 if (hw
->phy
.type
!= e1000_phy_igp_3
)
2360 /* Try the workaround twice (if needed) */
2363 reg
= er32(PHY_CTRL
);
2364 reg
|= (E1000_PHY_CTRL_GBE_DISABLE
|
2365 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
2366 ew32(PHY_CTRL
, reg
);
2369 * Call gig speed drop workaround on Gig disable before
2370 * accessing any PHY registers
2372 if (hw
->mac
.type
== e1000_ich8lan
)
2373 e1000e_gig_downshift_workaround_ich8lan(hw
);
2375 /* Write VR power-down enable */
2376 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
2377 data
&= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
2378 e1e_wphy(hw
, IGP3_VR_CTRL
, data
| IGP3_VR_CTRL_MODE_SHUTDOWN
);
2380 /* Read it back and test */
2381 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
2382 data
&= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
2383 if ((data
== IGP3_VR_CTRL_MODE_SHUTDOWN
) || retry
)
2386 /* Issue PHY reset and repeat at most one more time */
2388 ew32(CTRL
, reg
| E1000_CTRL_PHY_RST
);
2394 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2395 * @hw: pointer to the HW structure
2397 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2398 * LPLU, Gig disable, MDIC PHY reset):
2399 * 1) Set Kumeran Near-end loopback
2400 * 2) Clear Kumeran Near-end loopback
2401 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2403 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw
*hw
)
2408 if ((hw
->mac
.type
!= e1000_ich8lan
) ||
2409 (hw
->phy
.type
!= e1000_phy_igp_3
))
2412 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2416 reg_data
|= E1000_KMRNCTRLSTA_DIAG_NELPBK
;
2417 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2421 reg_data
&= ~E1000_KMRNCTRLSTA_DIAG_NELPBK
;
2422 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2427 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2428 * @hw: pointer to the HW structure
2430 * During S0 to Sx transition, it is possible the link remains at gig
2431 * instead of negotiating to a lower speed. Before going to Sx, set
2432 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2435 * Should only be called for ICH9 and ICH10 devices.
2437 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw
*hw
)
2441 if ((hw
->mac
.type
== e1000_ich10lan
) ||
2442 (hw
->mac
.type
== e1000_ich9lan
)) {
2443 phy_ctrl
= er32(PHY_CTRL
);
2444 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
|
2445 E1000_PHY_CTRL_GBE_DISABLE
;
2446 ew32(PHY_CTRL
, phy_ctrl
);
2453 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2454 * @hw: pointer to the HW structure
2456 * Return the LED back to the default configuration.
2458 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
)
2460 if (hw
->phy
.type
== e1000_phy_ife
)
2461 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
, 0);
2463 ew32(LEDCTL
, hw
->mac
.ledctl_default
);
2468 * e1000_led_on_ich8lan - Turn LEDs on
2469 * @hw: pointer to the HW structure
2473 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
)
2475 if (hw
->phy
.type
== e1000_phy_ife
)
2476 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
2477 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_ON
));
2479 ew32(LEDCTL
, hw
->mac
.ledctl_mode2
);
2484 * e1000_led_off_ich8lan - Turn LEDs off
2485 * @hw: pointer to the HW structure
2487 * Turn off the LEDs.
2489 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
)
2491 if (hw
->phy
.type
== e1000_phy_ife
)
2492 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
2493 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_OFF
));
2495 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
2500 * e1000_get_cfg_done_ich8lan - Read config done bit
2501 * @hw: pointer to the HW structure
2503 * Read the management control register for the config done bit for
2504 * completion status. NOTE: silicon which is EEPROM-less will fail trying
2505 * to read the config done bit, so an error is *ONLY* logged and returns
2506 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
2507 * would not be able to be reset or change link.
2509 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
)
2513 e1000e_get_cfg_done(hw
);
2515 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2516 if (hw
->mac
.type
!= e1000_ich10lan
) {
2517 if (((er32(EECD
) & E1000_EECD_PRES
) == 0) &&
2518 (hw
->phy
.type
== e1000_phy_igp_3
)) {
2519 e1000e_phy_init_script_igp3(hw
);
2522 if (e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
)) {
2523 /* Maybe we should do a basic PHY config */
2524 hw_dbg(hw
, "EEPROM not present\n");
2525 return -E1000_ERR_CONFIG
;
2533 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2534 * @hw: pointer to the HW structure
2536 * Clears hardware counters specific to the silicon family and calls
2537 * clear_hw_cntrs_generic to clear all general purpose counters.
2539 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
)
2543 e1000e_clear_hw_cntrs_base(hw
);
2545 temp
= er32(ALGNERRC
);
2546 temp
= er32(RXERRC
);
2548 temp
= er32(CEXTERR
);
2550 temp
= er32(TSCTFC
);
2552 temp
= er32(MGTPRC
);
2553 temp
= er32(MGTPDC
);
2554 temp
= er32(MGTPTC
);
2557 temp
= er32(ICRXOC
);
2561 static struct e1000_mac_operations ich8_mac_ops
= {
2562 .check_mng_mode
= e1000_check_mng_mode_ich8lan
,
2563 .check_for_link
= e1000e_check_for_copper_link
,
2564 .cleanup_led
= e1000_cleanup_led_ich8lan
,
2565 .clear_hw_cntrs
= e1000_clear_hw_cntrs_ich8lan
,
2566 .get_bus_info
= e1000_get_bus_info_ich8lan
,
2567 .get_link_up_info
= e1000_get_link_up_info_ich8lan
,
2568 .led_on
= e1000_led_on_ich8lan
,
2569 .led_off
= e1000_led_off_ich8lan
,
2570 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
2571 .reset_hw
= e1000_reset_hw_ich8lan
,
2572 .init_hw
= e1000_init_hw_ich8lan
,
2573 .setup_link
= e1000_setup_link_ich8lan
,
2574 .setup_physical_interface
= e1000_setup_copper_link_ich8lan
,
2577 static struct e1000_phy_operations ich8_phy_ops
= {
2578 .acquire_phy
= e1000_acquire_swflag_ich8lan
,
2579 .check_reset_block
= e1000_check_reset_block_ich8lan
,
2581 .force_speed_duplex
= e1000_phy_force_speed_duplex_ich8lan
,
2582 .get_cfg_done
= e1000_get_cfg_done_ich8lan
,
2583 .get_cable_length
= e1000e_get_cable_length_igp_2
,
2584 .get_phy_info
= e1000_get_phy_info_ich8lan
,
2585 .read_phy_reg
= e1000e_read_phy_reg_igp
,
2586 .release_phy
= e1000_release_swflag_ich8lan
,
2587 .reset_phy
= e1000_phy_hw_reset_ich8lan
,
2588 .set_d0_lplu_state
= e1000_set_d0_lplu_state_ich8lan
,
2589 .set_d3_lplu_state
= e1000_set_d3_lplu_state_ich8lan
,
2590 .write_phy_reg
= e1000e_write_phy_reg_igp
,
2593 static struct e1000_nvm_operations ich8_nvm_ops
= {
2594 .acquire_nvm
= e1000_acquire_swflag_ich8lan
,
2595 .read_nvm
= e1000_read_nvm_ich8lan
,
2596 .release_nvm
= e1000_release_swflag_ich8lan
,
2597 .update_nvm
= e1000_update_nvm_checksum_ich8lan
,
2598 .valid_led_default
= e1000_valid_led_default_ich8lan
,
2599 .validate_nvm
= e1000_validate_nvm_checksum_ich8lan
,
2600 .write_nvm
= e1000_write_nvm_ich8lan
,
2603 struct e1000_info e1000_ich8_info
= {
2604 .mac
= e1000_ich8lan
,
2605 .flags
= FLAG_HAS_WOL
2607 | FLAG_RX_CSUM_ENABLED
2608 | FLAG_HAS_CTRLEXT_ON_LOAD
2613 .get_variants
= e1000_get_variants_ich8lan
,
2614 .mac_ops
= &ich8_mac_ops
,
2615 .phy_ops
= &ich8_phy_ops
,
2616 .nvm_ops
= &ich8_nvm_ops
,
2619 struct e1000_info e1000_ich9_info
= {
2620 .mac
= e1000_ich9lan
,
2621 .flags
= FLAG_HAS_JUMBO_FRAMES
2624 | FLAG_RX_CSUM_ENABLED
2625 | FLAG_HAS_CTRLEXT_ON_LOAD
2631 .get_variants
= e1000_get_variants_ich8lan
,
2632 .mac_ops
= &ich8_mac_ops
,
2633 .phy_ops
= &ich8_phy_ops
,
2634 .nvm_ops
= &ich8_nvm_ops
,
2637 struct e1000_info e1000_ich10_info
= {
2638 .mac
= e1000_ich10lan
,
2639 .flags
= FLAG_HAS_JUMBO_FRAMES
2642 | FLAG_RX_CSUM_ENABLED
2643 | FLAG_HAS_CTRLEXT_ON_LOAD
2649 .get_variants
= e1000_get_variants_ich8lan
,
2650 .mac_ops
= &ich8_mac_ops
,
2651 .phy_ops
= &ich8_phy_ops
,
2652 .nvm_ops
= &ich8_nvm_ops
,