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MERGE-master-patchset-edits
[linux-2.6/openmoko-kernel.git] / drivers / net / au1000_eth.c
blob9c875bb3f76c642f93203f9096942af72a0e3e53
1 /*
2 *
3 * Alchemy Au1x00 ethernet driver
4 *
5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
11 * ioctls (SIOCGMIIPHY)
12 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
13 * converted to use linux-2.6.x's PHY framework
14 *
15 * Author: MontaVista Software, Inc.
16 * ppopov@mvista.com or source@mvista.com
17 *
18 * ########################################################################
19 *
20 * This program is free software; you can distribute it and/or modify it
21 * under the terms of the GNU General Public License (Version 2) as
22 * published by the Free Software Foundation.
23 *
24 * This program is distributed in the hope it will be useful, but WITHOUT
25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * for more details.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
32 *
33 * ########################################################################
34 *
35 *
36 */
37 #include <linux/dma-mapping.h>
38 #include <linux/module.h>
39 #include <linux/kernel.h>
40 #include <linux/string.h>
41 #include <linux/timer.h>
42 #include <linux/errno.h>
43 #include <linux/in.h>
44 #include <linux/ioport.h>
45 #include <linux/bitops.h>
46 #include <linux/slab.h>
47 #include <linux/interrupt.h>
48 #include <linux/init.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/ethtool.h>
52 #include <linux/mii.h>
53 #include <linux/skbuff.h>
54 #include <linux/delay.h>
55 #include <linux/crc32.h>
56 #include <linux/phy.h>
57
58 #include <asm/cpu.h>
59 #include <asm/mipsregs.h>
60 #include <asm/irq.h>
61 #include <asm/io.h>
62 #include <asm/processor.h>
63
64 #include <au1000.h>
65 #include <prom.h>
66
67 #include "au1000_eth.h"
68
69 #ifdef AU1000_ETH_DEBUG
70 static int au1000_debug = 5;
71 #else
72 static int au1000_debug = 3;
73 #endif
74
75 #define DRV_NAME "au1000_eth"
76 #define DRV_VERSION "1.6"
77 #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
78 #define DRV_DESC "Au1xxx on-chip Ethernet driver"
79
80 MODULE_AUTHOR(DRV_AUTHOR);
81 MODULE_DESCRIPTION(DRV_DESC);
82 MODULE_LICENSE("GPL");
83
84 // prototypes
85 static void hard_stop(struct net_device *);
86 static void enable_rx_tx(struct net_device *dev);
87 static struct net_device * au1000_probe(int port_num);
88 static int au1000_init(struct net_device *);
89 static int au1000_open(struct net_device *);
90 static int au1000_close(struct net_device *);
91 static int au1000_tx(struct sk_buff *, struct net_device *);
92 static int au1000_rx(struct net_device *);
93 static irqreturn_t au1000_interrupt(int, void *);
94 static void au1000_tx_timeout(struct net_device *);
95 static void set_rx_mode(struct net_device *);
96 static int au1000_ioctl(struct net_device *, struct ifreq *, int);
97 static int au1000_mdio_read(struct net_device *, int, int);
98 static void au1000_mdio_write(struct net_device *, int, int, u16);
99 static void au1000_adjust_link(struct net_device *);
100 static void enable_mac(struct net_device *, int);
101
102 /*
103 * Theory of operation
104 *
105 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
106 * There are four receive and four transmit descriptors. These
107 * descriptors are not in memory; rather, they are just a set of
108 * hardware registers.
109 *
110 * Since the Au1000 has a coherent data cache, the receive and
111 * transmit buffers are allocated from the KSEG0 segment. The
112 * hardware registers, however, are still mapped at KSEG1 to
113 * make sure there's no out-of-order writes, and that all writes
114 * complete immediately.
115 */
116
117 /* These addresses are only used if yamon doesn't tell us what
118 * the mac address is, and the mac address is not passed on the
119 * command line.
120 */
121 static unsigned char au1000_mac_addr[6] __devinitdata = {
122 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00
123 };
124
125 struct au1000_private *au_macs[NUM_ETH_INTERFACES];
126
127 /*
128 * board-specific configurations
129 *
130 * PHY detection algorithm
131 *
132 * If AU1XXX_PHY_STATIC_CONFIG is undefined, the PHY setup is
133 * autodetected:
134 *
135 * mii_probe() first searches the current MAC's MII bus for a PHY,
136 * selecting the first (or last, if AU1XXX_PHY_SEARCH_HIGHEST_ADDR is
137 * defined) PHY address not already claimed by another netdev.
138 *
139 * If nothing was found that way when searching for the 2nd ethernet
140 * controller's PHY and AU1XXX_PHY1_SEARCH_ON_MAC0 is defined, then
141 * the first MII bus is searched as well for an unclaimed PHY; this is
142 * needed in case of a dual-PHY accessible only through the MAC0's MII
143 * bus.
144 *
145 * Finally, if no PHY is found, then the corresponding ethernet
146 * controller is not registered to the network subsystem.
147 */
148
149 /* autodetection defaults */
150 #undef AU1XXX_PHY_SEARCH_HIGHEST_ADDR
151 #define AU1XXX_PHY1_SEARCH_ON_MAC0
152
153 /* static PHY setup
154 *
155 * most boards PHY setup should be detectable properly with the
156 * autodetection algorithm in mii_probe(), but in some cases (e.g. if
157 * you have a switch attached, or want to use the PHY's interrupt
158 * notification capabilities) you can provide a static PHY
159 * configuration here
160 *
161 * IRQs may only be set, if a PHY address was configured
162 * If a PHY address is given, also a bus id is required to be set
163 *
164 * ps: make sure the used irqs are configured properly in the board
165 * specific irq-map
166 */
167
168 #if defined(CONFIG_MIPS_BOSPORUS)
169 /*
170 * Micrel/Kendin 5 port switch attached to MAC0,
171 * MAC0 is associated with PHY address 5 (== WAN port)
172 * MAC1 is not associated with any PHY, since it's connected directly
173 * to the switch.
174 * no interrupts are used
175 */
176 # define AU1XXX_PHY_STATIC_CONFIG
177
178 # define AU1XXX_PHY0_ADDR 5
179 # define AU1XXX_PHY0_BUSID 0
180 # undef AU1XXX_PHY0_IRQ
181
182 # undef AU1XXX_PHY1_ADDR
183 # undef AU1XXX_PHY1_BUSID
184 # undef AU1XXX_PHY1_IRQ
185 #endif
186
187 #if defined(AU1XXX_PHY0_BUSID) && (AU1XXX_PHY0_BUSID > 0)
188 # error MAC0-associated PHY attached 2nd MACs MII bus not supported yet
189 #endif
190
191 /*
192 * MII operations
193 */
194 static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
195 {
196 struct au1000_private *aup = netdev_priv(dev);
197 volatile u32 *const mii_control_reg = &aup->mac->mii_control;
198 volatile u32 *const mii_data_reg = &aup->mac->mii_data;
199 u32 timedout = 20;
200 u32 mii_control;
201
202 while (*mii_control_reg & MAC_MII_BUSY) {
203 mdelay(1);
204 if (--timedout == 0) {
205 printk(KERN_ERR "%s: read_MII busy timeout!!\n",
206 dev->name);
207 return -1;
208 }
209 }
210
211 mii_control = MAC_SET_MII_SELECT_REG(reg) |
212 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
213
214 *mii_control_reg = mii_control;
215
216 timedout = 20;
217 while (*mii_control_reg & MAC_MII_BUSY) {
218 mdelay(1);
219 if (--timedout == 0) {
220 printk(KERN_ERR "%s: mdio_read busy timeout!!\n",
221 dev->name);
222 return -1;
223 }
224 }
225 return (int)*mii_data_reg;
226 }
227
228 static void au1000_mdio_write(struct net_device *dev, int phy_addr,
229 int reg, u16 value)
230 {
231 struct au1000_private *aup = netdev_priv(dev);
232 volatile u32 *const mii_control_reg = &aup->mac->mii_control;
233 volatile u32 *const mii_data_reg = &aup->mac->mii_data;
234 u32 timedout = 20;
235 u32 mii_control;
236
237 while (*mii_control_reg & MAC_MII_BUSY) {
238 mdelay(1);
239 if (--timedout == 0) {
240 printk(KERN_ERR "%s: mdio_write busy timeout!!\n",
241 dev->name);
242 return;
243 }
244 }
245
246 mii_control = MAC_SET_MII_SELECT_REG(reg) |
247 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
248
249 *mii_data_reg = value;
250 *mii_control_reg = mii_control;
251 }
252
253 static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
254 {
255 /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
256 * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */
257 struct net_device *const dev = bus->priv;
258
259 enable_mac(dev, 0); /* make sure the MAC associated with this
260 * mii_bus is enabled */
261 return au1000_mdio_read(dev, phy_addr, regnum);
262 }
263
264 static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
265 u16 value)
266 {
267 struct net_device *const dev = bus->priv;
268
269 enable_mac(dev, 0); /* make sure the MAC associated with this
270 * mii_bus is enabled */
271 au1000_mdio_write(dev, phy_addr, regnum, value);
272 return 0;
273 }
274
275 static int au1000_mdiobus_reset(struct mii_bus *bus)
276 {
277 struct net_device *const dev = bus->priv;
278
279 enable_mac(dev, 0); /* make sure the MAC associated with this
280 * mii_bus is enabled */
281 return 0;
282 }
283
284 static int mii_probe (struct net_device *dev)
285 {
286 struct au1000_private *const aup = netdev_priv(dev);
287 struct phy_device *phydev = NULL;
288
289 #if defined(AU1XXX_PHY_STATIC_CONFIG)
290 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
291
292 if(aup->mac_id == 0) { /* get PHY0 */
293 # if defined(AU1XXX_PHY0_ADDR)
294 phydev = au_macs[AU1XXX_PHY0_BUSID]->mii_bus->phy_map[AU1XXX_PHY0_ADDR];
295 # else
296 printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n",
297 dev->name);
298 return 0;
299 # endif /* defined(AU1XXX_PHY0_ADDR) */
300 } else if (aup->mac_id == 1) { /* get PHY1 */
301 # if defined(AU1XXX_PHY1_ADDR)
302 phydev = au_macs[AU1XXX_PHY1_BUSID]->mii_bus->phy_map[AU1XXX_PHY1_ADDR];
303 # else
304 printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n",
305 dev->name);
306 return 0;
307 # endif /* defined(AU1XXX_PHY1_ADDR) */
308 }
309
310 #else /* defined(AU1XXX_PHY_STATIC_CONFIG) */
311 int phy_addr;
312
313 /* find the first (lowest address) PHY on the current MAC's MII bus */
314 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
315 if (aup->mii_bus->phy_map[phy_addr]) {
316 phydev = aup->mii_bus->phy_map[phy_addr];
317 # if !defined(AU1XXX_PHY_SEARCH_HIGHEST_ADDR)
318 break; /* break out with first one found */
319 # endif
320 }
321
322 # if defined(AU1XXX_PHY1_SEARCH_ON_MAC0)
323 /* try harder to find a PHY */
324 if (!phydev && (aup->mac_id == 1)) {
325 /* no PHY found, maybe we have a dual PHY? */
326 printk (KERN_INFO DRV_NAME ": no PHY found on MAC1, "
327 "let's see if it's attached to MAC0...\n");
328
329 BUG_ON(!au_macs[0]);
330
331 /* find the first (lowest address) non-attached PHY on
332 * the MAC0 MII bus */
333 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
334 struct phy_device *const tmp_phydev =
335 au_macs[0]->mii_bus->phy_map[phy_addr];
336
337 if (!tmp_phydev)
338 continue; /* no PHY here... */
339
340 if (tmp_phydev->attached_dev)
341 continue; /* already claimed by MAC0 */
342
343 phydev = tmp_phydev;
344 break; /* found it */
345 }
346 }
347 # endif /* defined(AU1XXX_PHY1_SEARCH_OTHER_BUS) */
348
349 #endif /* defined(AU1XXX_PHY_STATIC_CONFIG) */
350 if (!phydev) {
351 printk (KERN_ERR DRV_NAME ":%s: no PHY found\n", dev->name);
352 return -1;
353 }
354
355 /* now we are supposed to have a proper phydev, to attach to... */
356 BUG_ON(phydev->attached_dev);
357
358 phydev = phy_connect(dev, phydev->dev.bus_id, &au1000_adjust_link, 0,
359 PHY_INTERFACE_MODE_MII);
360
361 if (IS_ERR(phydev)) {
362 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
363 return PTR_ERR(phydev);
364 }
365
366 /* mask with MAC supported features */
367 phydev->supported &= (SUPPORTED_10baseT_Half
368 | SUPPORTED_10baseT_Full
369 | SUPPORTED_100baseT_Half
370 | SUPPORTED_100baseT_Full
371 | SUPPORTED_Autoneg
372 /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
373 | SUPPORTED_MII
374 | SUPPORTED_TP);
375
376 phydev->advertising = phydev->supported;
377
378 aup->old_link = 0;
379 aup->old_speed = 0;
380 aup->old_duplex = -1;
381 aup->phy_dev = phydev;
382
383 printk(KERN_INFO "%s: attached PHY driver [%s] "
384 "(mii_bus:phy_addr=%s, irq=%d)\n",
385 dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
386
387 return 0;
388 }
389
390
391 /*
392 * Buffer allocation/deallocation routines. The buffer descriptor returned
393 * has the virtual and dma address of a buffer suitable for
394 * both, receive and transmit operations.
395 */
396 static db_dest_t *GetFreeDB(struct au1000_private *aup)
397 {
398 db_dest_t *pDB;
399 pDB = aup->pDBfree;
400
401 if (pDB) {
402 aup->pDBfree = pDB->pnext;
403 }
404 return pDB;
405 }
406
407 void ReleaseDB(struct au1000_private *aup, db_dest_t *pDB)
408 {
409 db_dest_t *pDBfree = aup->pDBfree;
410 if (pDBfree)
411 pDBfree->pnext = pDB;
412 aup->pDBfree = pDB;
413 }
414
415 static void enable_rx_tx(struct net_device *dev)
416 {
417 struct au1000_private *aup = netdev_priv(dev);
418
419 if (au1000_debug > 4)
420 printk(KERN_INFO "%s: enable_rx_tx\n", dev->name);
421
422 aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
423 au_sync_delay(10);
424 }
425
426 static void hard_stop(struct net_device *dev)
427 {
428 struct au1000_private *aup = netdev_priv(dev);
429
430 if (au1000_debug > 4)
431 printk(KERN_INFO "%s: hard stop\n", dev->name);
432
433 aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
434 au_sync_delay(10);
435 }
436
437 static void enable_mac(struct net_device *dev, int force_reset)
438 {
439 unsigned long flags;
440 struct au1000_private *aup = netdev_priv(dev);
441
442 spin_lock_irqsave(&aup->lock, flags);
443
444 if(force_reset || (!aup->mac_enabled)) {
445 *aup->enable = MAC_EN_CLOCK_ENABLE;
446 au_sync_delay(2);
447 *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
448 | MAC_EN_CLOCK_ENABLE);
449 au_sync_delay(2);
450
451 aup->mac_enabled = 1;
452 }
453
454 spin_unlock_irqrestore(&aup->lock, flags);
455 }
456
457 static void reset_mac_unlocked(struct net_device *dev)
458 {
459 struct au1000_private *const aup = netdev_priv(dev);
460 int i;
461
462 hard_stop(dev);
463
464 *aup->enable = MAC_EN_CLOCK_ENABLE;
465 au_sync_delay(2);
466 *aup->enable = 0;
467 au_sync_delay(2);
468
469 aup->tx_full = 0;
470 for (i = 0; i < NUM_RX_DMA; i++) {
471 /* reset control bits */
472 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
473 }
474 for (i = 0; i < NUM_TX_DMA; i++) {
475 /* reset control bits */
476 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
477 }
478
479 aup->mac_enabled = 0;
480
481 }
482
483 static void reset_mac(struct net_device *dev)
484 {
485 struct au1000_private *const aup = netdev_priv(dev);
486 unsigned long flags;
487
488 if (au1000_debug > 4)
489 printk(KERN_INFO "%s: reset mac, aup %x\n",
490 dev->name, (unsigned)aup);
491
492 spin_lock_irqsave(&aup->lock, flags);
493
494 reset_mac_unlocked (dev);
495
496 spin_unlock_irqrestore(&aup->lock, flags);
497 }
498
499 /*
500 * Setup the receive and transmit "rings". These pointers are the addresses
501 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
502 * these are not descriptors sitting in memory.
503 */
504 static void
505 setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
506 {
507 int i;
508
509 for (i = 0; i < NUM_RX_DMA; i++) {
510 aup->rx_dma_ring[i] =
511 (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
512 }
513 for (i = 0; i < NUM_TX_DMA; i++) {
514 aup->tx_dma_ring[i] =
515 (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
516 }
517 }
518
519 static struct {
520 u32 base_addr;
521 u32 macen_addr;
522 int irq;
523 struct net_device *dev;
524 } iflist[2] = {
525 #ifdef CONFIG_SOC_AU1000
526 {AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT},
527 {AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT}
528 #endif
529 #ifdef CONFIG_SOC_AU1100
530 {AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT}
531 #endif
532 #ifdef CONFIG_SOC_AU1500
533 {AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT},
534 {AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT}
535 #endif
536 #ifdef CONFIG_SOC_AU1550
537 {AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT},
538 {AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT}
539 #endif
540 };
541
542 static int num_ifs;
543
544 /*
545 * Setup the base address and interrupt of the Au1xxx ethernet macs
546 * based on cpu type and whether the interface is enabled in sys_pinfunc
547 * register. The last interface is enabled if SYS_PF_NI2 (bit 4) is 0.
548 */
549 static int __init au1000_init_module(void)
550 {
551 int ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4);
552 struct net_device *dev;
553 int i, found_one = 0;
554
555 num_ifs = NUM_ETH_INTERFACES - ni;
556
557 for(i = 0; i < num_ifs; i++) {
558 dev = au1000_probe(i);
559 iflist[i].dev = dev;
560 if (dev)
561 found_one++;
562 }
563 if (!found_one)
564 return -ENODEV;
565 return 0;
566 }
567
568 /*
569 * ethtool operations
570 */
571
572 static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
573 {
574 struct au1000_private *aup = netdev_priv(dev);
575
576 if (aup->phy_dev)
577 return phy_ethtool_gset(aup->phy_dev, cmd);
578
579 return -EINVAL;
580 }
581
582 static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
583 {
584 struct au1000_private *aup = netdev_priv(dev);
585
586 if (!capable(CAP_NET_ADMIN))
587 return -EPERM;
588
589 if (aup->phy_dev)
590 return phy_ethtool_sset(aup->phy_dev, cmd);
591
592 return -EINVAL;
593 }
594
595 static void
596 au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
597 {
598 struct au1000_private *aup = netdev_priv(dev);
599
600 strcpy(info->driver, DRV_NAME);
601 strcpy(info->version, DRV_VERSION);
602 info->fw_version[0] = '\0';
603 sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
604 info->regdump_len = 0;
605 }
606
607 static const struct ethtool_ops au1000_ethtool_ops = {
608 .get_settings = au1000_get_settings,
609 .set_settings = au1000_set_settings,
610 .get_drvinfo = au1000_get_drvinfo,
611 .get_link = ethtool_op_get_link,
612 };
613
614 static struct net_device * au1000_probe(int port_num)
615 {
616 static unsigned version_printed = 0;
617 struct au1000_private *aup = NULL;
618 struct net_device *dev = NULL;
619 db_dest_t *pDB, *pDBfree;
620 char ethaddr[6];
621 int irq, i, err;
622 u32 base, macen;
623
624 if (port_num >= NUM_ETH_INTERFACES)
625 return NULL;
626
627 base = CPHYSADDR(iflist[port_num].base_addr );
628 macen = CPHYSADDR(iflist[port_num].macen_addr);
629 irq = iflist[port_num].irq;
630
631 if (!request_mem_region( base, MAC_IOSIZE, "Au1x00 ENET") ||
632 !request_mem_region(macen, 4, "Au1x00 ENET"))
633 return NULL;
634
635 if (version_printed++ == 0)
636 printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
637
638 dev = alloc_etherdev(sizeof(struct au1000_private));
639 if (!dev) {
640 printk(KERN_ERR "%s: alloc_etherdev failed\n", DRV_NAME);
641 return NULL;
642 }
643
644 if ((err = register_netdev(dev)) != 0) {
645 printk(KERN_ERR "%s: Cannot register net device, error %d\n",
646 DRV_NAME, err);
647 free_netdev(dev);
648 return NULL;
649 }
650
651 printk("%s: Au1xx0 Ethernet found at 0x%x, irq %d\n",
652 dev->name, base, irq);
653
654 aup = netdev_priv(dev);
655
656 spin_lock_init(&aup->lock);
657
658 /* Allocate the data buffers */
659 /* Snooping works fine with eth on all au1xxx */
660 aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
661 (NUM_TX_BUFFS + NUM_RX_BUFFS),
662 &aup->dma_addr, 0);
663 if (!aup->vaddr) {
664 free_netdev(dev);
665 release_mem_region( base, MAC_IOSIZE);
666 release_mem_region(macen, 4);
667 return NULL;
668 }
669
670 /* aup->mac is the base address of the MAC's registers */
671 aup->mac = (volatile mac_reg_t *)iflist[port_num].base_addr;
672
673 /* Setup some variables for quick register address access */
674 aup->enable = (volatile u32 *)iflist[port_num].macen_addr;
675 aup->mac_id = port_num;
676 au_macs[port_num] = aup;
677
678 if (port_num == 0) {
679 if (prom_get_ethernet_addr(ethaddr) == 0)
680 memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr));
681 else {
682 printk(KERN_INFO "%s: No MAC address found\n",
683 dev->name);
684 /* Use the hard coded MAC addresses */
685 }
686
687 setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
688 } else if (port_num == 1)
689 setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
690
691 /*
692 * Assign to the Ethernet ports two consecutive MAC addresses
693 * to match those that are printed on their stickers
694 */
695 memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr));
696 dev->dev_addr[5] += port_num;
697
698 *aup->enable = 0;
699 aup->mac_enabled = 0;
700
701 aup->mii_bus = mdiobus_alloc();
702 if (aup->mii_bus == NULL)
703 goto err_out;
704
705 aup->mii_bus->priv = dev;
706 aup->mii_bus->read = au1000_mdiobus_read;
707 aup->mii_bus->write = au1000_mdiobus_write;
708 aup->mii_bus->reset = au1000_mdiobus_reset;
709 aup->mii_bus->name = "au1000_eth_mii";
710 snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id);
711 aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
712 for(i = 0; i < PHY_MAX_ADDR; ++i)
713 aup->mii_bus->irq[i] = PHY_POLL;
714
715 /* if known, set corresponding PHY IRQs */
716 #if defined(AU1XXX_PHY_STATIC_CONFIG)
717 # if defined(AU1XXX_PHY0_IRQ)
718 if (AU1XXX_PHY0_BUSID == aup->mac_id)
719 aup->mii_bus->irq[AU1XXX_PHY0_ADDR] = AU1XXX_PHY0_IRQ;
720 # endif
721 # if defined(AU1XXX_PHY1_IRQ)
722 if (AU1XXX_PHY1_BUSID == aup->mac_id)
723 aup->mii_bus->irq[AU1XXX_PHY1_ADDR] = AU1XXX_PHY1_IRQ;
724 # endif
725 #endif
726 mdiobus_register(aup->mii_bus);
727
728 if (mii_probe(dev) != 0) {
729 goto err_out;
730 }
731
732 pDBfree = NULL;
733 /* setup the data buffer descriptors and attach a buffer to each one */
734 pDB = aup->db;
735 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
736 pDB->pnext = pDBfree;
737 pDBfree = pDB;
738 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
739 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
740 pDB++;
741 }
742 aup->pDBfree = pDBfree;
743
744 for (i = 0; i < NUM_RX_DMA; i++) {
745 pDB = GetFreeDB(aup);
746 if (!pDB) {
747 goto err_out;
748 }
749 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
750 aup->rx_db_inuse[i] = pDB;
751 }
752 for (i = 0; i < NUM_TX_DMA; i++) {
753 pDB = GetFreeDB(aup);
754 if (!pDB) {
755 goto err_out;
756 }
757 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
758 aup->tx_dma_ring[i]->len = 0;
759 aup->tx_db_inuse[i] = pDB;
760 }
761
762 dev->base_addr = base;
763 dev->irq = irq;
764 dev->open = au1000_open;
765 dev->hard_start_xmit = au1000_tx;
766 dev->stop = au1000_close;
767 dev->set_multicast_list = &set_rx_mode;
768 dev->do_ioctl = &au1000_ioctl;
769 SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
770 dev->tx_timeout = au1000_tx_timeout;
771 dev->watchdog_timeo = ETH_TX_TIMEOUT;
772
773 /*
774 * The boot code uses the ethernet controller, so reset it to start
775 * fresh. au1000_init() expects that the device is in reset state.
776 */
777 reset_mac(dev);
778
779 return dev;
780
781 err_out:
782 if (aup->mii_bus != NULL) {
783 mdiobus_unregister(aup->mii_bus);
784 mdiobus_free(aup->mii_bus);
785 }
786
787 /* here we should have a valid dev plus aup-> register addresses
788 * so we can reset the mac properly.*/
789 reset_mac(dev);
790
791 for (i = 0; i < NUM_RX_DMA; i++) {
792 if (aup->rx_db_inuse[i])
793 ReleaseDB(aup, aup->rx_db_inuse[i]);
794 }
795 for (i = 0; i < NUM_TX_DMA; i++) {
796 if (aup->tx_db_inuse[i])
797 ReleaseDB(aup, aup->tx_db_inuse[i]);
798 }
799 dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
800 (void *)aup->vaddr, aup->dma_addr);
801 unregister_netdev(dev);
802 free_netdev(dev);
803 release_mem_region( base, MAC_IOSIZE);
804 release_mem_region(macen, 4);
805 return NULL;
806 }
807
808 /*
809 * Initialize the interface.
810 *
811 * When the device powers up, the clocks are disabled and the
812 * mac is in reset state. When the interface is closed, we
813 * do the same -- reset the device and disable the clocks to
814 * conserve power. Thus, whenever au1000_init() is called,
815 * the device should already be in reset state.
816 */
817 static int au1000_init(struct net_device *dev)
818 {
819 struct au1000_private *aup = netdev_priv(dev);
820 unsigned long flags;
821 int i;
822 u32 control;
823
824 if (au1000_debug > 4)
825 printk("%s: au1000_init\n", dev->name);
826
827 /* bring the device out of reset */
828 enable_mac(dev, 1);
829
830 spin_lock_irqsave(&aup->lock, flags);
831
832 aup->mac->control = 0;
833 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
834 aup->tx_tail = aup->tx_head;
835 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
836
837 aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
838 aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
839 dev->dev_addr[1]<<8 | dev->dev_addr[0];
840
841 for (i = 0; i < NUM_RX_DMA; i++) {
842 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
843 }
844 au_sync();
845
846 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
847 #ifndef CONFIG_CPU_LITTLE_ENDIAN
848 control |= MAC_BIG_ENDIAN;
849 #endif
850 if (aup->phy_dev) {
851 if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
852 control |= MAC_FULL_DUPLEX;
853 else
854 control |= MAC_DISABLE_RX_OWN;
855 } else { /* PHY-less op, assume full-duplex */
856 control |= MAC_FULL_DUPLEX;
857 }
858
859 aup->mac->control = control;
860 aup->mac->vlan1_tag = 0x8100; /* activate vlan support */
861 au_sync();
862
863 spin_unlock_irqrestore(&aup->lock, flags);
864 return 0;
865 }
866
867 static void
868 au1000_adjust_link(struct net_device *dev)
869 {
870 struct au1000_private *aup = netdev_priv(dev);
871 struct phy_device *phydev = aup->phy_dev;
872 unsigned long flags;
873
874 int status_change = 0;
875
876 BUG_ON(!aup->phy_dev);
877
878 spin_lock_irqsave(&aup->lock, flags);
879
880 if (phydev->link && (aup->old_speed != phydev->speed)) {
881 // speed changed
882
883 switch(phydev->speed) {
884 case SPEED_10:
885 case SPEED_100:
886 break;
887 default:
888 printk(KERN_WARNING
889 "%s: Speed (%d) is not 10/100 ???\n",
890 dev->name, phydev->speed);
891 break;
892 }
893
894 aup->old_speed = phydev->speed;
895
896 status_change = 1;
897 }
898
899 if (phydev->link && (aup->old_duplex != phydev->duplex)) {
900 // duplex mode changed
901
902 /* switching duplex mode requires to disable rx and tx! */
903 hard_stop(dev);
904
905 if (DUPLEX_FULL == phydev->duplex)
906 aup->mac->control = ((aup->mac->control
907 | MAC_FULL_DUPLEX)
908 & ~MAC_DISABLE_RX_OWN);
909 else
910 aup->mac->control = ((aup->mac->control
911 & ~MAC_FULL_DUPLEX)
912 | MAC_DISABLE_RX_OWN);
913 au_sync_delay(1);
914
915 enable_rx_tx(dev);
916 aup->old_duplex = phydev->duplex;
917
918 status_change = 1;
919 }
920
921 if(phydev->link != aup->old_link) {
922 // link state changed
923
924 if (!phydev->link) {
925 /* link went down */
926 aup->old_speed = 0;
927 aup->old_duplex = -1;
928 }
929
930 aup->old_link = phydev->link;
931 status_change = 1;
932 }
933
934 spin_unlock_irqrestore(&aup->lock, flags);
935
936 if (status_change) {
937 if (phydev->link)
938 printk(KERN_INFO "%s: link up (%d/%s)\n",
939 dev->name, phydev->speed,
940 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
941 else
942 printk(KERN_INFO "%s: link down\n", dev->name);
943 }
944 }
945
946 static int au1000_open(struct net_device *dev)
947 {
948 int retval;
949 struct au1000_private *aup = netdev_priv(dev);
950
951 if (au1000_debug > 4)
952 printk("%s: open: dev=%p\n", dev->name, dev);
953
954 if ((retval = request_irq(dev->irq, &au1000_interrupt, 0,
955 dev->name, dev))) {
956 printk(KERN_ERR "%s: unable to get IRQ %d\n",
957 dev->name, dev->irq);
958 return retval;
959 }
960
961 if ((retval = au1000_init(dev))) {
962 printk(KERN_ERR "%s: error in au1000_init\n", dev->name);
963 free_irq(dev->irq, dev);
964 return retval;
965 }
966
967 if (aup->phy_dev) {
968 /* cause the PHY state machine to schedule a link state check */
969 aup->phy_dev->state = PHY_CHANGELINK;
970 phy_start(aup->phy_dev);
971 }
972
973 netif_start_queue(dev);
974
975 if (au1000_debug > 4)
976 printk("%s: open: Initialization done.\n", dev->name);
977
978 return 0;
979 }
980
981 static int au1000_close(struct net_device *dev)
982 {
983 unsigned long flags;
984 struct au1000_private *const aup = netdev_priv(dev);
985
986 if (au1000_debug > 4)
987 printk("%s: close: dev=%p\n", dev->name, dev);
988
989 if (aup->phy_dev)
990 phy_stop(aup->phy_dev);
991
992 spin_lock_irqsave(&aup->lock, flags);
993
994 reset_mac_unlocked (dev);
995
996 /* stop the device */
997 netif_stop_queue(dev);
998
999 /* disable the interrupt */
1000 free_irq(dev->irq, dev);
1001 spin_unlock_irqrestore(&aup->lock, flags);
1002
1003 return 0;
1004 }
1005
1006 static void __exit au1000_cleanup_module(void)
1007 {
1008 int i, j;
1009 struct net_device *dev;
1010 struct au1000_private *aup;
1011
1012 for (i = 0; i < num_ifs; i++) {
1013 dev = iflist[i].dev;
1014 if (dev) {
1015 aup = netdev_priv(dev);
1016 unregister_netdev(dev);
1017 mdiobus_unregister(aup->mii_bus);
1018 mdiobus_free(aup->mii_bus);
1019 for (j = 0; j < NUM_RX_DMA; j++)
1020 if (aup->rx_db_inuse[j])
1021 ReleaseDB(aup, aup->rx_db_inuse[j]);
1022 for (j = 0; j < NUM_TX_DMA; j++)
1023 if (aup->tx_db_inuse[j])
1024 ReleaseDB(aup, aup->tx_db_inuse[j]);
1025 dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1026 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1027 (void *)aup->vaddr, aup->dma_addr);
1028 release_mem_region(dev->base_addr, MAC_IOSIZE);
1029 release_mem_region(CPHYSADDR(iflist[i].macen_addr), 4);
1030 free_netdev(dev);
1031 }
1032 }
1033 }
1034
1035 static void update_tx_stats(struct net_device *dev, u32 status)
1036 {
1037 struct au1000_private *aup = netdev_priv(dev);
1038 struct net_device_stats *ps = &dev->stats;
1039
1040 if (status & TX_FRAME_ABORTED) {
1041 if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
1042 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
1043 /* any other tx errors are only valid
1044 * in half duplex mode */
1045 ps->tx_errors++;
1046 ps->tx_aborted_errors++;
1047 }
1048 }
1049 else {
1050 ps->tx_errors++;
1051 ps->tx_aborted_errors++;
1052 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
1053 ps->tx_carrier_errors++;
1054 }
1055 }
1056 }
1057
1058
1059 /*
1060 * Called from the interrupt service routine to acknowledge
1061 * the TX DONE bits. This is a must if the irq is setup as
1062 * edge triggered.
1063 */
1064 static void au1000_tx_ack(struct net_device *dev)
1065 {
1066 struct au1000_private *aup = netdev_priv(dev);
1067 volatile tx_dma_t *ptxd;
1068
1069 ptxd = aup->tx_dma_ring[aup->tx_tail];
1070
1071 while (ptxd->buff_stat & TX_T_DONE) {
1072 update_tx_stats(dev, ptxd->status);
1073 ptxd->buff_stat &= ~TX_T_DONE;
1074 ptxd->len = 0;
1075 au_sync();
1076
1077 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
1078 ptxd = aup->tx_dma_ring[aup->tx_tail];
1079
1080 if (aup->tx_full) {
1081 aup->tx_full = 0;
1082 netif_wake_queue(dev);
1083 }
1084 }
1085 }
1086
1087
1088 /*
1089 * Au1000 transmit routine.
1090 */
1091 static int au1000_tx(struct sk_buff *skb, struct net_device *dev)
1092 {
1093 struct au1000_private *aup = netdev_priv(dev);
1094 struct net_device_stats *ps = &dev->stats;
1095 volatile tx_dma_t *ptxd;
1096 u32 buff_stat;
1097 db_dest_t *pDB;
1098 int i;
1099
1100 if (au1000_debug > 5)
1101 printk("%s: tx: aup %x len=%d, data=%p, head %d\n",
1102 dev->name, (unsigned)aup, skb->len,
1103 skb->data, aup->tx_head);
1104
1105 ptxd = aup->tx_dma_ring[aup->tx_head];
1106 buff_stat = ptxd->buff_stat;
1107 if (buff_stat & TX_DMA_ENABLE) {
1108 /* We've wrapped around and the transmitter is still busy */
1109 netif_stop_queue(dev);
1110 aup->tx_full = 1;
1111 return 1;
1112 }
1113 else if (buff_stat & TX_T_DONE) {
1114 update_tx_stats(dev, ptxd->status);
1115 ptxd->len = 0;
1116 }
1117
1118 if (aup->tx_full) {
1119 aup->tx_full = 0;
1120 netif_wake_queue(dev);
1121 }
1122
1123 pDB = aup->tx_db_inuse[aup->tx_head];
1124 skb_copy_from_linear_data(skb, pDB->vaddr, skb->len);
1125 if (skb->len < ETH_ZLEN) {
1126 for (i=skb->len; i<ETH_ZLEN; i++) {
1127 ((char *)pDB->vaddr)[i] = 0;
1128 }
1129 ptxd->len = ETH_ZLEN;
1130 }
1131 else
1132 ptxd->len = skb->len;
1133
1134 ps->tx_packets++;
1135 ps->tx_bytes += ptxd->len;
1136
1137 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1138 au_sync();
1139 dev_kfree_skb(skb);
1140 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1141 dev->trans_start = jiffies;
1142 return 0;
1143 }
1144
1145 static inline void update_rx_stats(struct net_device *dev, u32 status)
1146 {
1147 struct au1000_private *aup = netdev_priv(dev);
1148 struct net_device_stats *ps = &dev->stats;
1149
1150 ps->rx_packets++;
1151 if (status & RX_MCAST_FRAME)
1152 ps->multicast++;
1153
1154 if (status & RX_ERROR) {
1155 ps->rx_errors++;
1156 if (status & RX_MISSED_FRAME)
1157 ps->rx_missed_errors++;
1158 if (status & (RX_OVERLEN | RX_OVERLEN | RX_LEN_ERROR))
1159 ps->rx_length_errors++;
1160 if (status & RX_CRC_ERROR)
1161 ps->rx_crc_errors++;
1162 if (status & RX_COLL)
1163 ps->collisions++;
1164 }
1165 else
1166 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
1167
1168 }
1169
1170 /*
1171 * Au1000 receive routine.
1172 */
1173 static int au1000_rx(struct net_device *dev)
1174 {
1175 struct au1000_private *aup = netdev_priv(dev);
1176 struct sk_buff *skb;
1177 volatile rx_dma_t *prxd;
1178 u32 buff_stat, status;
1179 db_dest_t *pDB;
1180 u32 frmlen;
1181
1182 if (au1000_debug > 5)
1183 printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head);
1184
1185 prxd = aup->rx_dma_ring[aup->rx_head];
1186 buff_stat = prxd->buff_stat;
1187 while (buff_stat & RX_T_DONE) {
1188 status = prxd->status;
1189 pDB = aup->rx_db_inuse[aup->rx_head];
1190 update_rx_stats(dev, status);
1191 if (!(status & RX_ERROR)) {
1192
1193 /* good frame */
1194 frmlen = (status & RX_FRAME_LEN_MASK);
1195 frmlen -= 4; /* Remove FCS */
1196 skb = dev_alloc_skb(frmlen + 2);
1197 if (skb == NULL) {
1198 printk(KERN_ERR
1199 "%s: Memory squeeze, dropping packet.\n",
1200 dev->name);
1201 dev->stats.rx_dropped++;
1202 continue;
1203 }
1204 skb_reserve(skb, 2); /* 16 byte IP header align */
1205 skb_copy_to_linear_data(skb,
1206 (unsigned char *)pDB->vaddr, frmlen);
1207 skb_put(skb, frmlen);
1208 skb->protocol = eth_type_trans(skb, dev);
1209 netif_rx(skb); /* pass the packet to upper layers */
1210 }
1211 else {
1212 if (au1000_debug > 4) {
1213 if (status & RX_MISSED_FRAME)
1214 printk("rx miss\n");
1215 if (status & RX_WDOG_TIMER)
1216 printk("rx wdog\n");
1217 if (status & RX_RUNT)
1218 printk("rx runt\n");
1219 if (status & RX_OVERLEN)
1220 printk("rx overlen\n");
1221 if (status & RX_COLL)
1222 printk("rx coll\n");
1223 if (status & RX_MII_ERROR)
1224 printk("rx mii error\n");
1225 if (status & RX_CRC_ERROR)
1226 printk("rx crc error\n");
1227 if (status & RX_LEN_ERROR)
1228 printk("rx len error\n");
1229 if (status & RX_U_CNTRL_FRAME)
1230 printk("rx u control frame\n");
1231 if (status & RX_MISSED_FRAME)
1232 printk("rx miss\n");
1233 }
1234 }
1235 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
1236 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
1237 au_sync();
1238
1239 /* next descriptor */
1240 prxd = aup->rx_dma_ring[aup->rx_head];
1241 buff_stat = prxd->buff_stat;
1242 }
1243 return 0;
1244 }
1245
1246
1247 /*
1248 * Au1000 interrupt service routine.
1249 */
1250 static irqreturn_t au1000_interrupt(int irq, void *dev_id)
1251 {
1252 struct net_device *dev = dev_id;
1253
1254 /* Handle RX interrupts first to minimize chance of overrun */
1255
1256 au1000_rx(dev);
1257 au1000_tx_ack(dev);
1258 return IRQ_RETVAL(1);
1259 }
1260
1261
1262 /*
1263 * The Tx ring has been full longer than the watchdog timeout
1264 * value. The transmitter must be hung?
1265 */
1266 static void au1000_tx_timeout(struct net_device *dev)
1267 {
1268 printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev);
1269 reset_mac(dev);
1270 au1000_init(dev);
1271 dev->trans_start = jiffies;
1272 netif_wake_queue(dev);
1273 }
1274
1275 static void set_rx_mode(struct net_device *dev)
1276 {
1277 struct au1000_private *aup = netdev_priv(dev);
1278
1279 if (au1000_debug > 4)
1280 printk("%s: set_rx_mode: flags=%x\n", dev->name, dev->flags);
1281
1282 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1283 aup->mac->control |= MAC_PROMISCUOUS;
1284 } else if ((dev->flags & IFF_ALLMULTI) ||
1285 dev->mc_count > MULTICAST_FILTER_LIMIT) {
1286 aup->mac->control |= MAC_PASS_ALL_MULTI;
1287 aup->mac->control &= ~MAC_PROMISCUOUS;
1288 printk(KERN_INFO "%s: Pass all multicast\n", dev->name);
1289 } else {
1290 int i;
1291 struct dev_mc_list *mclist;
1292 u32 mc_filter[2]; /* Multicast hash filter */
1293
1294 mc_filter[1] = mc_filter[0] = 0;
1295 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1296 i++, mclist = mclist->next) {
1297 set_bit(ether_crc(ETH_ALEN, mclist->dmi_addr)>>26,
1298 (long *)mc_filter);
1299 }
1300 aup->mac->multi_hash_high = mc_filter[1];
1301 aup->mac->multi_hash_low = mc_filter[0];
1302 aup->mac->control &= ~MAC_PROMISCUOUS;
1303 aup->mac->control |= MAC_HASH_MODE;
1304 }
1305 }
1306
1307 static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1308 {
1309 struct au1000_private *aup = netdev_priv(dev);
1310
1311 if (!netif_running(dev)) return -EINVAL;
1312
1313 if (!aup->phy_dev) return -EINVAL; // PHY not controllable
1314
1315 return phy_mii_ioctl(aup->phy_dev, if_mii(rq), cmd);
1316 }
1317
1318 module_init(au1000_init_module);
1319 module_exit(au1000_cleanup_module);
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