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[Blackfin] arch: Enable both edge triggered GPIO IRQs on BF54x and use irq_to_gpio()
[linux-2.6/openmoko-kernel.git] / arch / blackfin / mach-common / ints-priority-sc.c
blobdec42acb5de0f346a434bdd5e916ceea5d23bb9f
1 /*
2 * File: arch/blackfin/mach-common/ints-priority-sc.c
3 * Based on:
4 * Author:
5 *
6 * Created: ?
7 * Description: Set up the interrupt priorities
8 *
9 * Modified:
10 * 1996 Roman Zippel
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2007 Analog Devices Inc.
17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/seq_file.h>
39 #include <linux/irq.h>
40 #ifdef CONFIG_KGDB
41 #include <linux/kgdb.h>
42 #endif
43 #include <asm/traps.h>
44 #include <asm/blackfin.h>
45 #include <asm/gpio.h>
46 #include <asm/irq_handler.h>
47
48 #ifdef BF537_FAMILY
49 # define BF537_GENERIC_ERROR_INT_DEMUX
50 #else
51 # undef BF537_GENERIC_ERROR_INT_DEMUX
52 #endif
53
54 /*
55 * NOTES:
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
58 * -
59 */
60
61 /* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
66 */
67 unsigned long irq_flags = 0x1f;
68
69 /* The number of spurious interrupts */
70 atomic_t num_spurious;
71
72 struct ivgx {
73 /* irq number for request_irq, available in mach-bf533/irq.h */
74 unsigned int irqno;
75 /* corresponding bit in the SIC_ISR register */
76 unsigned int isrflag;
77 } ivg_table[NR_PERI_INTS];
78
79 struct ivg_slice {
80 /* position of first irq in ivg_table for given ivg */
81 struct ivgx *ifirst;
82 struct ivgx *istop;
83 } ivg7_13[IVG13 - IVG7 + 1];
84
85 static void search_IAR(void);
86
87 /*
88 * Search SIC_IAR and fill tables with the irqvalues
89 * and their positions in the SIC_ISR register.
90 */
91 static void __init search_IAR(void)
92 {
93 unsigned ivg, irq_pos = 0;
94 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
95 int irqn;
96
97 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
98
99 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
100 int iar_shift = (irqn & 7) * 4;
101 if (ivg ==
102 (0xf &
103 #ifndef CONFIG_BF52x
104 bfin_read32((unsigned long *)SIC_IAR0 +
105 (irqn >> 3)) >> iar_shift)) {
106 #else
107 bfin_read32((unsigned long *)SIC_IAR0 +
108 ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
109 #endif
110 ivg_table[irq_pos].irqno = IVG7 + irqn;
111 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
112 ivg7_13[ivg].istop++;
113 irq_pos++;
114 }
115 }
116 }
117 }
118
119 /*
120 * This is for BF533 internal IRQs
121 */
122
123 static void ack_noop(unsigned int irq)
124 {
125 /* Dummy function. */
126 }
127
128 static void bfin_core_mask_irq(unsigned int irq)
129 {
130 irq_flags &= ~(1 << irq);
131 if (!irqs_disabled())
132 local_irq_enable();
133 }
134
135 static void bfin_core_unmask_irq(unsigned int irq)
136 {
137 irq_flags |= 1 << irq;
138 /*
139 * If interrupts are enabled, IMASK must contain the same value
140 * as irq_flags. Make sure that invariant holds. If interrupts
141 * are currently disabled we need not do anything; one of the
142 * callers will take care of setting IMASK to the proper value
143 * when reenabling interrupts.
144 * local_irq_enable just does "STI irq_flags", so it's exactly
145 * what we need.
146 */
147 if (!irqs_disabled())
148 local_irq_enable();
149 return;
150 }
151
152 static void bfin_internal_mask_irq(unsigned int irq)
153 {
154 #ifdef CONFIG_BF53x
155 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
156 ~(1 << (irq - (IRQ_CORETMR + 1))));
157 #else
158 unsigned mask_bank, mask_bit;
159 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
160 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
161 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
162 ~(1 << mask_bit));
163 #endif
164 SSYNC();
165 }
166
167 static void bfin_internal_unmask_irq(unsigned int irq)
168 {
169 #ifdef CONFIG_BF53x
170 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
171 (1 << (irq - (IRQ_CORETMR + 1))));
172 #else
173 unsigned mask_bank, mask_bit;
174 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
175 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
176 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
177 (1 << mask_bit));
178 #endif
179 SSYNC();
180 }
181
182 static struct irq_chip bfin_core_irqchip = {
183 .ack = ack_noop,
184 .mask = bfin_core_mask_irq,
185 .unmask = bfin_core_unmask_irq,
186 };
187
188 static struct irq_chip bfin_internal_irqchip = {
189 .ack = ack_noop,
190 .mask = bfin_internal_mask_irq,
191 .unmask = bfin_internal_unmask_irq,
192 };
193
194 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
195 static int error_int_mask;
196
197 static void bfin_generic_error_ack_irq(unsigned int irq)
198 {
199
200 }
201
202 static void bfin_generic_error_mask_irq(unsigned int irq)
203 {
204 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
205
206 if (!error_int_mask) {
207 local_irq_disable();
208 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
209 ~(1 <<
210 (IRQ_GENERIC_ERROR -
211 (IRQ_CORETMR + 1))));
212 SSYNC();
213 local_irq_enable();
214 }
215 }
216
217 static void bfin_generic_error_unmask_irq(unsigned int irq)
218 {
219 local_irq_disable();
220 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 <<
221 (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1)));
222 SSYNC();
223 local_irq_enable();
224
225 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
226 }
227
228 static struct irq_chip bfin_generic_error_irqchip = {
229 .ack = bfin_generic_error_ack_irq,
230 .mask = bfin_generic_error_mask_irq,
231 .unmask = bfin_generic_error_unmask_irq,
232 };
233
234 static void bfin_demux_error_irq(unsigned int int_err_irq,
235 struct irq_desc *intb_desc)
236 {
237 int irq = 0;
238
239 SSYNC();
240
241 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
242 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
243 irq = IRQ_MAC_ERROR;
244 else
245 #endif
246 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
247 irq = IRQ_SPORT0_ERROR;
248 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
249 irq = IRQ_SPORT1_ERROR;
250 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
251 irq = IRQ_PPI_ERROR;
252 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
253 irq = IRQ_CAN_ERROR;
254 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
255 irq = IRQ_SPI_ERROR;
256 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
257 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
258 irq = IRQ_UART0_ERROR;
259 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
260 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
261 irq = IRQ_UART1_ERROR;
262
263 if (irq) {
264 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
265 struct irq_desc *desc = irq_desc + irq;
266 desc->handle_irq(irq, desc);
267 } else {
268
269 switch (irq) {
270 case IRQ_PPI_ERROR:
271 bfin_write_PPI_STATUS(PPI_ERR_MASK);
272 break;
273 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
274 case IRQ_MAC_ERROR:
275 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
276 break;
277 #endif
278 case IRQ_SPORT0_ERROR:
279 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
280 break;
281
282 case IRQ_SPORT1_ERROR:
283 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
284 break;
285
286 case IRQ_CAN_ERROR:
287 bfin_write_CAN_GIS(CAN_ERR_MASK);
288 break;
289
290 case IRQ_SPI_ERROR:
291 bfin_write_SPI_STAT(SPI_ERR_MASK);
292 break;
293
294 default:
295 break;
296 }
297
298 pr_debug("IRQ %d:"
299 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
300 irq);
301 }
302 } else
303 printk(KERN_ERR
304 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
305 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
306 __FUNCTION__, __FILE__, __LINE__);
307
308 }
309 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
310
311 #if !defined(CONFIG_BF54x)
312
313 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
314 static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
315
316
317 static void bfin_gpio_ack_irq(unsigned int irq)
318 {
319 u16 gpionr = irq - IRQ_PF0;
320
321 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
322 set_gpio_data(gpionr, 0);
323 SSYNC();
324 }
325 }
326
327 static void bfin_gpio_mask_ack_irq(unsigned int irq)
328 {
329 u16 gpionr = irq - IRQ_PF0;
330
331 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
332 set_gpio_data(gpionr, 0);
333 SSYNC();
334 }
335
336 set_gpio_maska(gpionr, 0);
337 SSYNC();
338 }
339
340 static void bfin_gpio_mask_irq(unsigned int irq)
341 {
342 set_gpio_maska(irq - IRQ_PF0, 0);
343 SSYNC();
344 }
345
346 static void bfin_gpio_unmask_irq(unsigned int irq)
347 {
348 set_gpio_maska(irq - IRQ_PF0, 1);
349 SSYNC();
350 }
351
352 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
353 {
354 unsigned int ret;
355 u16 gpionr = irq - IRQ_PF0;
356 char buf[8];
357
358 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
359 snprintf(buf, sizeof buf, "IRQ %d", irq);
360 ret = gpio_request(gpionr, buf);
361 if (ret)
362 return ret;
363 }
364
365 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
366 bfin_gpio_unmask_irq(irq);
367
368 return ret;
369 }
370
371 static void bfin_gpio_irq_shutdown(unsigned int irq)
372 {
373 bfin_gpio_mask_irq(irq);
374 gpio_free(irq - IRQ_PF0);
375 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
376 }
377
378 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
379 {
380
381 unsigned int ret;
382 char buf[8];
383 u16 gpionr = irq - IRQ_PF0;
384
385 if (type == IRQ_TYPE_PROBE) {
386 /* only probe unenabled GPIO interrupt lines */
387 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
388 return 0;
389 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
390 }
391
392 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
393 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
394 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
395 snprintf(buf, sizeof buf, "IRQ %d", irq);
396 ret = gpio_request(gpionr, buf);
397 if (ret)
398 return ret;
399 }
400
401 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
402 } else {
403 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
404 return 0;
405 }
406
407 set_gpio_dir(gpionr, 0);
408 set_gpio_inen(gpionr, 1);
409
410 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
411 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
412 set_gpio_edge(gpionr, 1);
413 } else {
414 set_gpio_edge(gpionr, 0);
415 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
416 }
417
418 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
419 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
420 set_gpio_both(gpionr, 1);
421 else
422 set_gpio_both(gpionr, 0);
423
424 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
425 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
426 else
427 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
428
429 SSYNC();
430
431 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
432 set_irq_handler(irq, handle_edge_irq);
433 else
434 set_irq_handler(irq, handle_level_irq);
435
436 return 0;
437 }
438
439 static struct irq_chip bfin_gpio_irqchip = {
440 .ack = bfin_gpio_ack_irq,
441 .mask = bfin_gpio_mask_irq,
442 .mask_ack = bfin_gpio_mask_ack_irq,
443 .unmask = bfin_gpio_unmask_irq,
444 .set_type = bfin_gpio_irq_type,
445 .startup = bfin_gpio_irq_startup,
446 .shutdown = bfin_gpio_irq_shutdown
447 };
448
449 static void bfin_demux_gpio_irq(unsigned int intb_irq,
450 struct irq_desc *intb_desc)
451 {
452 u16 i;
453 struct irq_desc *desc;
454
455 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
456 int irq = IRQ_PF0 + i;
457 int flag_d = get_gpiop_data(i);
458 int mask =
459 flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i));
460
461 while (mask) {
462 if (mask & 1) {
463 desc = irq_desc + irq;
464 desc->handle_irq(irq, desc);
465 }
466 irq++;
467 mask >>= 1;
468 }
469 }
470 }
471
472 #else /* CONFIG_BF54x */
473
474 #define NR_PINT_SYS_IRQS 4
475 #define NR_PINT_BITS 32
476 #define NR_PINTS 160
477 #define IRQ_NOT_AVAIL 0xFF
478
479 #define PINT_2_BANK(x) ((x) >> 5)
480 #define PINT_2_BIT(x) ((x) & 0x1F)
481 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
482
483 static unsigned char irq2pint_lut[NR_PINTS];
484 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
485
486 static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
487 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
488
489
490 struct pin_int_t {
491 unsigned int mask_set;
492 unsigned int mask_clear;
493 unsigned int request;
494 unsigned int assign;
495 unsigned int edge_set;
496 unsigned int edge_clear;
497 unsigned int invert_set;
498 unsigned int invert_clear;
499 unsigned int pinstate;
500 unsigned int latch;
501 };
502
503 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
504 (struct pin_int_t *)PINT0_MASK_SET,
505 (struct pin_int_t *)PINT1_MASK_SET,
506 (struct pin_int_t *)PINT2_MASK_SET,
507 (struct pin_int_t *)PINT3_MASK_SET,
508 };
509
510 unsigned short get_irq_base(u8 bank, u8 bmap)
511 {
512
513 u16 irq_base;
514
515 if (bank < 2) { /*PA-PB */
516 irq_base = IRQ_PA0 + bmap * 16;
517 } else { /*PC-PJ */
518 irq_base = IRQ_PC0 + bmap * 16;
519 }
520
521 return irq_base;
522
523 }
524
525 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
526 void init_pint_lut(void)
527 {
528 u16 bank, bit, irq_base, bit_pos;
529 u32 pint_assign;
530 u8 bmap;
531
532 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
533
534 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
535
536 pint_assign = pint[bank]->assign;
537
538 for (bit = 0; bit < NR_PINT_BITS; bit++) {
539
540 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
541
542 irq_base = get_irq_base(bank, bmap);
543
544 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
545 bit_pos = bit + bank * NR_PINT_BITS;
546
547 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
548 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
549
550 }
551
552 }
553
554 }
555
556 static void bfin_gpio_ack_irq(unsigned int irq)
557 {
558 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
559 u32 pintbit = PINT_BIT(pint_val);
560 u8 bank = PINT_2_BANK(pint_val);
561
562 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
563 if (pint[bank]->invert_set & pintbit)
564 pint[bank]->invert_clear = pintbit;
565 else
566 pint[bank]->invert_set = pintbit;
567 }
568 pint[bank]->request = pintbit;
569
570 SSYNC();
571 }
572
573 static void bfin_gpio_mask_ack_irq(unsigned int irq)
574 {
575 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
576 u32 pintbit = PINT_BIT(pint_val);
577 u8 bank = PINT_2_BANK(pint_val);
578
579 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
580 if (pint[bank]->invert_set & pintbit)
581 pint[bank]->invert_clear = pintbit;
582 else
583 pint[bank]->invert_set = pintbit;
584 }
585
586 pint[bank]->request = pintbit;
587 pint[bank]->mask_clear = pintbit;
588 SSYNC();
589 }
590
591 static void bfin_gpio_mask_irq(unsigned int irq)
592 {
593 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
594
595 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
596 SSYNC();
597 }
598
599 static void bfin_gpio_unmask_irq(unsigned int irq)
600 {
601 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
602 u32 pintbit = PINT_BIT(pint_val);
603 u8 bank = PINT_2_BANK(pint_val);
604
605 pint[bank]->request = pintbit;
606 pint[bank]->mask_set = pintbit;
607 SSYNC();
608 }
609
610 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
611 {
612 unsigned int ret;
613 char buf[8];
614 u16 gpionr = irq_to_gpio(irq);
615 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
616
617 if (pint_val == IRQ_NOT_AVAIL) {
618 printk(KERN_ERR
619 "GPIO IRQ %d :Not in PINT Assign table "
620 "Reconfigure Interrupt to Port Assignemt\n", irq);
621 return -ENODEV;
622 }
623
624 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
625 snprintf(buf, sizeof buf, "IRQ %d", irq);
626 ret = gpio_request(gpionr, buf);
627 if (ret)
628 return ret;
629 }
630
631 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
632 bfin_gpio_unmask_irq(irq);
633
634 return ret;
635 }
636
637 static void bfin_gpio_irq_shutdown(unsigned int irq)
638 {
639 u16 gpionr = irq_to_gpio(irq);
640
641 bfin_gpio_mask_irq(irq);
642 gpio_free(gpionr);
643 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
644 }
645
646 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
647 {
648
649 unsigned int ret;
650 char buf[8];
651 u16 gpionr = irq_to_gpio(irq);
652 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
653 u32 pintbit = PINT_BIT(pint_val);
654 u8 bank = PINT_2_BANK(pint_val);
655
656 if (pint_val == IRQ_NOT_AVAIL)
657 return -ENODEV;
658
659 if (type == IRQ_TYPE_PROBE) {
660 /* only probe unenabled GPIO interrupt lines */
661 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
662 return 0;
663 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
664 }
665
666 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
667 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
668 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
669 snprintf(buf, sizeof buf, "IRQ %d", irq);
670 ret = gpio_request(gpionr, buf);
671 if (ret)
672 return ret;
673 }
674
675 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
676 } else {
677 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
678 return 0;
679 }
680
681 gpio_direction_input(gpionr);
682
683 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
684 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
685 else
686 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
687
688 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
689 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
690
691 gpio_both_edge_triggered[bank] |= pintbit;
692
693 if (gpio_get_value(gpionr))
694 pint[bank]->invert_set = pintbit;
695 else
696 pint[bank]->invert_clear = pintbit;
697 } else {
698 gpio_both_edge_triggered[bank] &= ~pintbit;
699 }
700
701 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
702 pint[bank]->edge_set = pintbit;
703 set_irq_handler(irq, handle_edge_irq);
704 } else {
705 pint[bank]->edge_clear = pintbit;
706 set_irq_handler(irq, handle_level_irq);
707 }
708
709 SSYNC();
710
711 return 0;
712 }
713
714 static struct irq_chip bfin_gpio_irqchip = {
715 .ack = bfin_gpio_ack_irq,
716 .mask = bfin_gpio_mask_irq,
717 .mask_ack = bfin_gpio_mask_ack_irq,
718 .unmask = bfin_gpio_unmask_irq,
719 .set_type = bfin_gpio_irq_type,
720 .startup = bfin_gpio_irq_startup,
721 .shutdown = bfin_gpio_irq_shutdown
722 };
723
724 static void bfin_demux_gpio_irq(unsigned int intb_irq,
725 struct irq_desc *intb_desc)
726 {
727 u8 bank, pint_val;
728 u32 request, irq;
729 struct irq_desc *desc;
730
731 switch (intb_irq) {
732 case IRQ_PINT0:
733 bank = 0;
734 break;
735 case IRQ_PINT2:
736 bank = 2;
737 break;
738 case IRQ_PINT3:
739 bank = 3;
740 break;
741 case IRQ_PINT1:
742 bank = 1;
743 break;
744 default:
745 return;
746 }
747
748 pint_val = bank * NR_PINT_BITS;
749
750 request = pint[bank]->request;
751
752 while (request) {
753 if (request & 1) {
754 irq = pint2irq_lut[pint_val] + SYS_IRQS;
755 desc = irq_desc + irq;
756 desc->handle_irq(irq, desc);
757 }
758 pint_val++;
759 request >>= 1;
760 }
761
762 }
763 #endif
764
765 void __init init_exception_vectors(void)
766 {
767 SSYNC();
768
769 /* cannot program in software:
770 * evt0 - emulation (jtag)
771 * evt1 - reset
772 */
773 bfin_write_EVT2(evt_nmi);
774 bfin_write_EVT3(trap);
775 bfin_write_EVT5(evt_ivhw);
776 bfin_write_EVT6(evt_timer);
777 bfin_write_EVT7(evt_evt7);
778 bfin_write_EVT8(evt_evt8);
779 bfin_write_EVT9(evt_evt9);
780 bfin_write_EVT10(evt_evt10);
781 bfin_write_EVT11(evt_evt11);
782 bfin_write_EVT12(evt_evt12);
783 bfin_write_EVT13(evt_evt13);
784 bfin_write_EVT14(evt14_softirq);
785 bfin_write_EVT15(evt_system_call);
786 CSYNC();
787 }
788
789 /*
790 * This function should be called during kernel startup to initialize
791 * the BFin IRQ handling routines.
792 */
793 int __init init_arch_irq(void)
794 {
795 int irq;
796 unsigned long ilat = 0;
797 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
798 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
799 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
800 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
801 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
802 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
803 # ifdef CONFIG_BF54x
804 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
805 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
806 # endif
807 #else
808 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
809 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
810 #endif
811 SSYNC();
812
813 local_irq_disable();
814
815 #ifdef CONFIG_BF54x
816 # ifdef CONFIG_PINTx_REASSIGN
817 pint[0]->assign = CONFIG_PINT0_ASSIGN;
818 pint[1]->assign = CONFIG_PINT1_ASSIGN;
819 pint[2]->assign = CONFIG_PINT2_ASSIGN;
820 pint[3]->assign = CONFIG_PINT3_ASSIGN;
821 # endif
822 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
823 init_pint_lut();
824 #endif
825
826 for (irq = 0; irq <= SYS_IRQS; irq++) {
827 if (irq <= IRQ_CORETMR)
828 set_irq_chip(irq, &bfin_core_irqchip);
829 else
830 set_irq_chip(irq, &bfin_internal_irqchip);
831 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
832 if (irq != IRQ_GENERIC_ERROR) {
833 #endif
834
835 switch (irq) {
836 #if defined(CONFIG_BF53x)
837 case IRQ_PROG_INTA:
838 set_irq_chained_handler(irq,
839 bfin_demux_gpio_irq);
840 break;
841 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
842 case IRQ_MAC_RX:
843 set_irq_chained_handler(irq,
844 bfin_demux_gpio_irq);
845 break;
846 # endif
847 #elif defined(CONFIG_BF54x)
848 case IRQ_PINT0:
849 set_irq_chained_handler(irq,
850 bfin_demux_gpio_irq);
851 break;
852 case IRQ_PINT1:
853 set_irq_chained_handler(irq,
854 bfin_demux_gpio_irq);
855 break;
856 case IRQ_PINT2:
857 set_irq_chained_handler(irq,
858 bfin_demux_gpio_irq);
859 break;
860 case IRQ_PINT3:
861 set_irq_chained_handler(irq,
862 bfin_demux_gpio_irq);
863 break;
864 #elif defined(CONFIG_BF52x)
865 case IRQ_PORTF_INTA:
866 set_irq_chained_handler(irq,
867 bfin_demux_gpio_irq);
868 break;
869 case IRQ_PORTG_INTA:
870 set_irq_chained_handler(irq,
871 bfin_demux_gpio_irq);
872 break;
873 case IRQ_PORTH_INTA:
874 set_irq_chained_handler(irq,
875 bfin_demux_gpio_irq);
876 break;
877 #endif
878 default:
879 set_irq_handler(irq, handle_simple_irq);
880 break;
881 }
882
883 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
884 } else {
885 set_irq_handler(irq, bfin_demux_error_irq);
886 }
887 #endif
888 }
889 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
890 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) {
891 set_irq_chip(irq, &bfin_generic_error_irqchip);
892 set_irq_handler(irq, handle_level_irq);
893 }
894 #endif
895
896 #ifndef CONFIG_BF54x
897 for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
898 #else
899 for (irq = IRQ_PA0; irq < NR_IRQS; irq++) {
900 #endif
901 set_irq_chip(irq, &bfin_gpio_irqchip);
902 /* if configured as edge, then will be changed to do_edge_IRQ */
903 set_irq_handler(irq, handle_level_irq);
904 }
905
906 bfin_write_IMASK(0);
907 CSYNC();
908 ilat = bfin_read_ILAT();
909 CSYNC();
910 bfin_write_ILAT(ilat);
911 CSYNC();
912
913 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
914 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
915 * local_irq_enable()
916 */
917 program_IAR();
918 /* Therefore it's better to setup IARs before interrupts enabled */
919 search_IAR();
920
921 /* Enable interrupts IVG7-15 */
922 irq_flags = irq_flags | IMASK_IVG15 |
923 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
924 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
925
926 return 0;
927 }
928
929 #ifdef CONFIG_DO_IRQ_L1
930 __attribute__((l1_text))
931 #endif
932 void do_irq(int vec, struct pt_regs *fp)
933 {
934 if (vec == EVT_IVTMR_P) {
935 vec = IRQ_CORETMR;
936 } else {
937 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
938 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
939 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
940 unsigned long sic_status[3];
941
942 SSYNC();
943 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
944 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
945 #ifdef CONFIG_BF54x
946 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
947 #endif
948 for (;; ivg++) {
949 if (ivg >= ivg_stop) {
950 atomic_inc(&num_spurious);
951 return;
952 }
953 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
954 break;
955 }
956 #else
957 unsigned long sic_status;
958 SSYNC();
959 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
960
961 for (;; ivg++) {
962 if (ivg >= ivg_stop) {
963 atomic_inc(&num_spurious);
964 return;
965 } else if (sic_status & ivg->isrflag)
966 break;
967 }
968 #endif
969 vec = ivg->irqno;
970 }
971 asm_do_IRQ(vec, fp);
972
973 #ifdef CONFIG_KGDB
974 kgdb_process_breakpoint();
975 #endif
976 }
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