arch/arm/plat-s3c/pwm-clock.c

   1 /* linux/arch/arm/plat-s3c24xx/pwm-clock.c
   2  *
   3  * Copyright (c) 2007 Simtec Electronics
   4  * Copyright (c) 2007, 2008 Ben Dooks
   5  *      Ben Dooks <ben-linux@fluff.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10 */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/list.h>
  16 #include <linux/errno.h>
  17 #include <linux/log2.h>
  18 #include <linux/clk.h>
  19 #include <linux/err.h>
  20 #include <linux/io.h>
  21
  22 #include <mach/hardware.h>
  23 #include <mach/map.h>
  24 #include <asm/irq.h>
  25
  26 #include <plat/clock.h>
  27 #include <plat/cpu.h>
  28
  29 #include <plat/regs-timer.h>
  30 #include <mach/pwm-clock.h>
  31
  32 /* Each of the timers 0 through 5 go through the following
  33  * clock tree, with the inputs depending on the timers.
  34  *
  35  * pclk ---- [ prescaler 0 ] -+---> timer 0
  36  *                            +---> timer 1
  37  *
  38  * pclk ---- [ prescaler 1 ] -+---> timer 2
  39  *                            +---> timer 3
  40  *                            \---> timer 4
  41  *
  42  * Which are fed into the timers as so:
  43  *
  44  * prescaled 0 ---- [ div 2,4,8,16 ] ---\
  45  *                                     [mux] -> timer 0
  46  * tclk 0 ------------------------------/
  47  *
  48  * prescaled 0 ---- [ div 2,4,8,16 ] ---\
  49  *                                     [mux] -> timer 1
  50  * tclk 0 ------------------------------/
  51  *
  52  *
  53  * prescaled 1 ---- [ div 2,4,8,16 ] ---\
  54  *                                     [mux] -> timer 2
  55  * tclk 1 ------------------------------/
  56  *
  57  * prescaled 1 ---- [ div 2,4,8,16 ] ---\
  58  *                                     [mux] -> timer 3
  59  * tclk 1 ------------------------------/
  60  *
  61  * prescaled 1 ---- [ div 2,4,8, 16 ] --\
  62  *                                     [mux] -> timer 4
  63  * tclk 1 ------------------------------/
  64  *
  65  * Since the mux and the divider are tied together in the
  66  * same register space, it is impossible to set the parent
  67  * and the rate at the same time. To avoid this, we add an
  68  * intermediate 'prescaled-and-divided' clock to select
  69  * as the parent for the timer input clock called tdiv.
  70  *
  71  * prescaled clk --> pwm-tdiv ---\
  72  *                             [ mux ] --> timer X
  73  * tclk -------------------------/
  74 */
  75
  76 static unsigned long clk_pwm_scaler_getrate(struct clk *clk)
  77 {
  78         unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
  79
  80         if (clk->id == 1) {
  81                 tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
  82                 tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
  83         } else {
  84                 tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
  85         }
  86
  87         return clk_get_rate(clk->parent) / (tcfg0 + 1);
  88 }
  89
  90 /* TODO - add set rate calls. */
  91
  92 static struct clk clk_timer_scaler[] = {
  93         [0]     = {
  94                 .name           = "pwm-scaler0",
  95                 .id             = -1,
  96                 .get_rate       = clk_pwm_scaler_getrate,
  97         },
  98         [1]     = {
  99                 .name           = "pwm-scaler1",
 100                 .id             = -1,
 101                 .get_rate       = clk_pwm_scaler_getrate,
 102         },
 103 };
 104
 105 static struct clk clk_timer_tclk[] = {
 106         [0]     = {
 107                 .name           = "pwm-tclk0",
 108                 .id             = -1,
 109         },
 110         [1]     = {
 111                 .name           = "pwm-tclk1",
 112                 .id             = -1,
 113         },
 114 };
 115
 116 struct pwm_tdiv_clk {
 117         struct clk      clk;
 118         unsigned int    divisor;
 119 };
 120
 121 static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
 122 {
 123         return container_of(clk, struct pwm_tdiv_clk, clk);
 124 }
 125
 126 static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
 127 {
 128         unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
 129         unsigned int divisor;
 130
 131         tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
 132         tcfg1 &= S3C2410_TCFG1_MUX_MASK;
 133
 134         if (pwm_cfg_src_is_tclk(tcfg1))
 135                 divisor = to_tdiv(clk)->divisor;
 136         else
 137                 divisor = tcfg_to_divisor(tcfg1);
 138
 139         return clk_get_rate(clk->parent) / divisor;
 140 }
 141
 142 static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
 143                                              unsigned long rate)
 144 {
 145         unsigned long parent_rate;
 146         unsigned long divisor;
 147
 148         parent_rate = clk_get_rate(clk->parent);
 149         divisor = parent_rate / rate;
 150
 151         if (divisor <= 1 && pwm_tdiv_has_div1())
 152                 divisor = 1;
 153         else if (divisor <= 2)
 154                 divisor = 2;
 155         else if (divisor <= 4)
 156                 divisor = 4;
 157         else if (divisor <= 8)
 158                 divisor = 8;
 159         else
 160                 divisor = 16;
 161
 162         return parent_rate / divisor;
 163 }
 164
 165 static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
 166 {
 167         return pwm_tdiv_div_bits(divclk->divisor);
 168 }
 169
 170 static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
 171 {
 172         unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
 173         unsigned long bits = clk_pwm_tdiv_bits(divclk);
 174         unsigned long flags;
 175         unsigned long shift =  S3C2410_TCFG1_SHIFT(divclk->clk.id);
 176
 177         local_irq_save(flags);
 178
 179         tcfg1 = __raw_readl(S3C2410_TCFG1);
 180         tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
 181         tcfg1 |= bits << shift;
 182         __raw_writel(tcfg1, S3C2410_TCFG1);
 183
 184         local_irq_restore(flags);
 185 }
 186
 187 static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
 188 {
 189         struct pwm_tdiv_clk *divclk = to_tdiv(clk);
 190         unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
 191         unsigned long parent_rate = clk_get_rate(clk->parent);
 192         unsigned long divisor;
 193
 194         tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
 195         tcfg1 &= S3C2410_TCFG1_MUX_MASK;
 196
 197         rate = clk_round_rate(clk, rate);
 198         divisor = parent_rate / rate;
 199
 200         if (divisor > 16)
 201                 return -EINVAL;
 202
 203         divclk->divisor = divisor;
 204
 205         /* Update the current MUX settings if we are currently
 206          * selected as the clock source for this clock. */
 207
 208         if (!pwm_cfg_src_is_tclk(tcfg1))
 209                 clk_pwm_tdiv_update(divclk);
 210
 211         return 0;
 212 }
 213
 214 static struct pwm_tdiv_clk clk_timer_tdiv[] = {
 215         [0]     = {
 216                 .clk    = {
 217                         .name           = "pwm-tdiv",
 218                         .parent         = &clk_timer_scaler[0],
 219                         .get_rate       = clk_pwm_tdiv_get_rate,
 220                         .set_rate       = clk_pwm_tdiv_set_rate,
 221                         .round_rate     = clk_pwm_tdiv_round_rate,
 222                 },
 223         },
 224         [1]     = {
 225                 .clk    = {
 226                         .name           = "pwm-tdiv",
 227                         .parent         = &clk_timer_scaler[0],
 228                         .get_rate       = clk_pwm_tdiv_get_rate,
 229                         .set_rate       = clk_pwm_tdiv_set_rate,
 230                         .round_rate     = clk_pwm_tdiv_round_rate,
 231                 }
 232         },
 233         [2]     = {
 234                 .clk    = {
 235                         .name           = "pwm-tdiv",
 236                         .parent         = &clk_timer_scaler[1],
 237                         .get_rate       = clk_pwm_tdiv_get_rate,
 238                         .set_rate       = clk_pwm_tdiv_set_rate,
 239                         .round_rate     = clk_pwm_tdiv_round_rate,
 240                 },
 241         },
 242         [3]     = {
 243                 .clk    = {
 244                         .name           = "pwm-tdiv",
 245                         .parent         = &clk_timer_scaler[1],
 246                         .get_rate       = clk_pwm_tdiv_get_rate,
 247                         .set_rate       = clk_pwm_tdiv_set_rate,
 248                         .round_rate     = clk_pwm_tdiv_round_rate,
 249                 },
 250         },
 251         [4]     = {
 252                 .clk    = {
 253                         .name           = "pwm-tdiv",
 254                         .parent         = &clk_timer_scaler[1],
 255                         .get_rate       = clk_pwm_tdiv_get_rate,
 256                         .set_rate       = clk_pwm_tdiv_set_rate,
 257                         .round_rate     = clk_pwm_tdiv_round_rate,
 258                 },
 259         },
 260 };
 261
 262 static int __init clk_pwm_tdiv_register(unsigned int id)
 263 {
 264         struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
 265         unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
 266
 267         tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
 268         tcfg1 &= S3C2410_TCFG1_MUX_MASK;
 269
 270         divclk->clk.id = id;
 271         divclk->divisor = tcfg_to_divisor(tcfg1);
 272
 273         return s3c24xx_register_clock(&divclk->clk);
 274 }
 275
 276 static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
 277 {
 278         return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
 279 }
 280
 281 static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
 282 {
 283         return &clk_timer_tdiv[id].clk;
 284 }
 285
 286 static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
 287 {
 288         unsigned int id = clk->id;
 289         unsigned long tcfg1;
 290         unsigned long flags;
 291         unsigned long bits;
 292         unsigned long shift = S3C2410_TCFG1_SHIFT(id);
 293
 294         if (parent == s3c24xx_pwmclk_tclk(id))
 295                 bits = S3C_TCFG1_MUX_TCLK << shift;
 296         else if (parent == s3c24xx_pwmclk_tdiv(id))
 297                 bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
 298         else
 299                 return -EINVAL;
 300
 301         clk->parent = parent;
 302
 303         local_irq_save(flags);
 304
 305         tcfg1 = __raw_readl(S3C2410_TCFG1);
 306         tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
 307         __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
 308
 309         local_irq_restore(flags);
 310
 311         return 0;
 312 }
 313
 314 static struct clk clk_tin[] = {
 315         [0]     = {
 316                 .name           = "pwm-tin",
 317                 .id             = 0,
 318                 .set_parent     = clk_pwm_tin_set_parent,
 319         },
 320         [1]     = {
 321                 .name           = "pwm-tin",
 322                 .id             = 1,
 323                 .set_parent     = clk_pwm_tin_set_parent,
 324         },
 325         [2]     = {
 326                 .name           = "pwm-tin",
 327                 .id             = 2,
 328                 .set_parent     = clk_pwm_tin_set_parent,
 329         },
 330         [3]     = {
 331                 .name           = "pwm-tin",
 332                 .id             = 3,
 333                 .set_parent     = clk_pwm_tin_set_parent,
 334         },
 335         [4]     = {
 336                 .name           = "pwm-tin",
 337                 .id             = 4,
 338                 .set_parent     = clk_pwm_tin_set_parent,
 339         },
 340 };
 341
 342 static __init int clk_pwm_tin_register(struct clk *pwm)
 343 {
 344         unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
 345         unsigned int id = pwm->id;
 346
 347         struct clk *parent;
 348         int ret;
 349
 350         ret = s3c24xx_register_clock(pwm);
 351         if (ret < 0)
 352                 return ret;
 353
 354         tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
 355         tcfg1 &= S3C2410_TCFG1_MUX_MASK;
 356
 357         if (pwm_cfg_src_is_tclk(tcfg1))
 358                 parent = s3c24xx_pwmclk_tclk(id);
 359         else
 360                 parent = s3c24xx_pwmclk_tdiv(id);
 361
 362         return clk_set_parent(pwm, parent);
 363 }
 364
 365 static __init int s3c24xx_pwmclk_init(void)
 366 {
 367         struct clk *clk_timers;
 368         unsigned int clk;
 369         int ret;
 370
 371         clk_timers = clk_get(NULL, "timers");
 372         if (IS_ERR(clk_timers)) {
 373                 printk(KERN_ERR "%s: no parent clock\n", __func__);
 374                 return -EINVAL;
 375         }
 376
 377         for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) {
 378                 clk_timer_scaler[clk].parent = clk_timers;
 379                 ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
 380                 if (ret < 0) {
 381                         printk(KERN_ERR "error adding pwm scaler%d clock\n", clk);
 382                         goto err;
 383                 }
 384         }
 385
 386         for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) {
 387                 ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
 388                 if (ret < 0) {
 389                         printk(KERN_ERR "error adding pww tclk%d\n", clk);
 390                         goto err;
 391                 }
 392         }
 393
 394         for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
 395                 ret = clk_pwm_tdiv_register(clk);
 396                 if (ret < 0) {
 397                         printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
 398                         goto err;
 399                 }
 400         }
 401
 402         for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
 403                 ret = clk_pwm_tin_register(&clk_tin[clk]);
 404                 if (ret < 0) {
 405                         printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
 406                         goto err;
 407                 }
 408         }
 409
 410         return 0;
 411
 412  err:
 413         return ret;
 414 }
 415
 416 arch_initcall(s3c24xx_pwmclk_init);